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  to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
v850e/if3, v850e/ig3 32-bit single-chip microcontrollers hardware user?s manual v850e/if3: pd70f3451 pd70f3452 v850e/ig3: pd70f3453 pd70f3454 printed in japan document no. u18279ej3v0ud00 (3rd edition) date published march 2010 n 2007
user?s manual u18279ej3v0ud 2 [memo]
user?s manual u18279ej3v0ud 3 notes for cmos devices (1) voltage application waveform at input pin: wa veform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cm os device stays in the ar ea between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the i nput level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input le vel may be generated due to noise, etc., causing malfunction. cmos devices behave differently t han bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fiel d, when exposed to a mos dev ice, can cause destruction of the gate oxide and ultimately degr ade the device operation. steps mu st be taken to stop generation of static electricity as much as possible, and quickly dissi pate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electric ity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operat or should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not nece ssarily define the initial st atus of a mos device. immediately after the power source is turned on, devic es with reset functions have not yet been initialized. hence, power-on does not guar antee output pin levels, i/o settings or cont ents of registers. a device is not initialized until the reset signal is received. a rese t operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device t hat uses different power supplies for the internal operation and external interface, as a rule, switch on t he external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal element s of the device, causing malfuncti on and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related spec ifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abno rmal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power o ff state must be judged separately for each device and according to related s pecifications gover ning the device.
user?s manual u18279ej3v0ud 4 caution: this product uses superflash ? technology licensed from silicon storage technology, inc. eeprom is a trademark of nec electronics corporation. minicube is a registered trademark of nec electronics corporation in jap an and germany or a trademark in the united states of america. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. ? the information in this document is curr ent as of march, 2010. the information is subject to change without notice. for act ual design-in, refer to the latest publications of nec electr onics data sheets or data books, etc., for the most up-to-date specifications of nec el ectronics products. not all products and/or types are av ailable in every country. please check with a n nec electronics sales representative for av ailability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the pr ior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights o f third parties by or arising from the use of nec electronics pr oducts listed in this document or any other liability arising fro m the use of such products. no licens e, express, implied or otherwise, is granted under any patents, copyrights or other intellectua l property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and app lication examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third par ties arising from the use of these circuits, software and information. ? while nec electronics endeavors to enhance the quality, reliab ility and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to mini mize risks of damage to property or injury (including death) to persons arising from def ects in nec electronics products, cust omers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. ? nec electronics products are cl assified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a cu stomer-designated "quality assurance program" for a specific app lication. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. custom ers must check the quality grade of each ne c electronics product before using it in a particular application. "standard": computers, office equipm ent, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, ma chine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti- crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reacto r control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expre ssly specified in nec electronics data sheets or data books, etc. if customers wish to use nec elec tronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note 1) "nec electronics" as used in this statement means nec electronics cor poration and also includes its majority- owned subsidiaries. (note 2) "nec electronics products" m eans any product developed or manufactured by or for nec electronics (as defined above). (m8e0909e)
user?s manual u18279ej3v0ud 5 preface readers this manual is intended for users who wish to understand the functi ons of the v850e/if3 ( pd70f3451, 70f3452) and v850e/ig3 ( pd70f3453, 70f3454) and design application systems using the v850e/if3 and v850e/ig3. purpose this manual is intended to give users an under standing of the hardw are functions of the v850e/if3 and v850e/ig3 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850e1 architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? electrical specifications ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the over all functions of t he v850e/if3 and v850e/ig3 read this manual according to the contents . to find the details of a register where the name is known see appendix b register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the details of an instruction function refer to the v850e1 architecture user?s manual . to know the electrical specificat ions of the v850e/if3 and v850e/ig3 see chapter 28 electrical specifications . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that even if ?xxx.yyy? is descri bed as is in a program, however, the compiler/assembler cannot recognize it correctly.
user?s manual u18279ej3v0ud 6 the mark ?? shows major revised points. the revised points can be easily searched by copying an ?? in the pdf file and s pecifying it in the ?find what:? field. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ? 32 bits halfword ? 16 bits byte ? 8 bits
user?s manual u18279ej3v0ud 7 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/if3 and v850e/ig3 document name document no. v850e1 architecture user?s manual u14559e v850e/if3, v850e/ig3 hardware user?s manual this manual v850e/if3, v850e/ig3 sample pr ograms for serial communication (uarta) application note u18723e v850e/if3, v850e/ig3 sample pr ograms for serial communication (uartb) application note u18724e v850e/if3, v850e/ig3 sample programs for serial communication (csib) application note u18725e v850e/if3, v850e/ig3 sample progr ams for serial communication (i 2 c) application note u18726e v850e/if3, v850e/ig3 sample program s for dma function application note u18727e v850e/if3, v850e/ig3 sample programs for timer m application note u18728e v850e/if3, v850e/ig3 sample programs for watchdog timer application note u18729e v850e/if3, v850e/ig3 sample programs for timer aa application note u18730e v850e/if3, v850e/ig3 sample programs for timer ab application note u18731e v850e/if3, v850e/ig3 sample programs fo r timer t application note u18732e v850e/if3, v850e/ig3 sample programs for port function application note u18733e v850e/if3, v850e/ig3 sample programs for clock generator application note u18734e v850e/if3, v850e/ig3 sample programs for standby function application note u18735e v850e/if3, v850e/ig3 sample programs for interrupt function application note u18736e v850e/if3, v850e/ig3 sample programs for a/d converters 0 and 1 application note u18737e v850e/if3, v850e/ig3 sample programs for a/d converter 2 application note u18738e v850e/if3, v850e/ig3 sample program s for low-voltage detector (lvi) function application note u18739e v850e/if3, v850e/ig3 6-phase pwm out put control by timer ab, timer q option, timer aa, a/d converters 0, 1 application note u18717e
user?s manual u18279ej3v0ud 8 documents related to developm ent tools (user?s manuals) document name document no. qb-v850eix3 in-circuit emulator u18651e qb-v850mini on-chip debug emulator u17638e qb-mini2 on-chip debug emulator with programming function u18371e qb-programmer programmi ng gui operation u18527e operation u18512e c language u18513e assembly language u18514e ca850 ver. 3.20 c compiler package link directives u18515e pm+ ver. 6.30 project manager u18416e id850qb ver. 3.40 integrated debugger operation u18604e tw850 ver. 2.00 performance analysis tuning tool u17241e operation u18601e sm+ system simulator user open interface u18212e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u18165e in-structure u18164e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e pg-fp5 flash memory programmer u18865e
user?s manual u18279ej3v0ud 9 contents chapter 1 introduction ...................................................................................................... ...........20 1.1 overview ....................................................................................................................... .............20 1.2 v850e/if3 ...................................................................................................................... .............22 1.2.1 features (v850e/if 3)........................................................................................................... ....... 22 1.2.2 application fiel ds (v850e /if3) ................................................................................................. .... 24 1.2.3 ordering informa tion (v850e /if3) ............................................................................................... 24 1.2.4 pin configurat ion (v850e /if3) .................................................................................................. ... 25 1.2.5 function blo cks (v850e /if3) .................................................................................................... ... 27 1.3 v850e/ig3...................................................................................................................... .............30 1.3.1 features (v850e/ig3 ) ........................................................................................................... ...... 30 1.3.2 application fiel ds (v850e /ig3)................................................................................................. .... 32 1.3.3 ordering informa tion (v850e /ig3)............................................................................................... 32 1.3.4 pin configurat ion (v850e /ig3).................................................................................................. ... 33 1.3.5 function blo cks (v850e /ig3).................................................................................................... ... 38 chapter 2 pin funct ions.................................................................................................... ............42 2.1 list of pin functions .......................................................................................................... ......42 2.2 pin status..................................................................................................................... ..............54 2.3 pin i/o circuits and recommended connection of u nused pins .......................................55 2.4 pin i/o circuits ............................................................................................................... ...........59 chapter 3 cpu function..................................................................................................... ............60 3.1 features ....................................................................................................................... ..............60 3.2 cpu register set ............................................................................................................... .......61 3.2.1 program regi ster set........................................................................................................... ......... 62 3.2.2 system regi ster set............................................................................................................ .......... 63 3.3 operating modes................................................................................................................ .......69 3.3.1 operati ng m odes ................................................................................................................ ......... 69 3.3.2 operating mode s pecificat ion ................................................................................................... ... 69 3.4 address space .................................................................................................................. ........70 3.4.1 cpu address space .............................................................................................................. ...... 70 3.4.2 image .......................................................................................................................... ................ 71 3.4.3 wraparound of cpu addr ess spac e............................................................................................ 72 3.4.4 memory map ..................................................................................................................... .......... 73 3.4.5 area........................................................................................................................... .................. 74 3.4.6 recommended use of address s pace ......................................................................................... 77 3.4.7 on-chip peripheral i/o registers ............................................................................................... ... 79 3.4.8 special r egister s.............................................................................................................. ............ 93 3.4.9 system wait control register (vswc) .......................................................................................... 97 chapter 4 port f unctions................................................................................................... .........98 4.1 features ....................................................................................................................... ..............98 4.1.1 v850e/if3 ...................................................................................................................... ............. 98
user?s manual u18279ej3v0ud 10 4.1.2 v850e/ig3 ...................................................................................................................... .............98 4.2 port configuration................................................................ ............................................. ........99 4.2.1 v850e/if 3...................................................................................................................... ..............99 4.2.2 v850e/ig3 ...................................................................................................................... ...........100 4.3 port configuration................................................................ ............................................. ..... 101 4.3.1 port 0......................................................................................................................... ................106 4.3.2 port 1......................................................................................................................... ................113 4.3.3 port 2......................................................................................................................... ................119 4.3.4 port 3......................................................................................................................... ................125 4.3.5 port 4......................................................................................................................... ................131 4.3.6 port 7......................................................................................................................... ................137 4.3.7 port dl ........................................................................................................................ ..............139 4.4 output data and port read value for each setting ............................................................ 144 4.5 port register settings when alternate function is used.................................................. 157 4.6 noise eliminator ............................................................................................................... ...... 166 4.7 cautions ....................................................................................................................... ........... 172 4.7.1 cautions on se tting port pins .................................................................................................. ...172 4.7.2 cautions on bit manipulation instru ction for port n r egister (pn) ................................................173 chapter 5 clock generator .................................................................................................. .. 174 5.1 overview ....................................................................................................................... .......... 174 5.2 configuration.................................................................................................................. ........ 175 5.3 control registers .............................................................................................................. ..... 178 5.4 pll function ................................................................................................................... ....... 184 5.4.1 overvi ew....................................................................................................................... .............184 5.4.2 pll m ode ....................................................................................................................... ...........184 5.4.3 clock-thr ough m ode ............................................................................................................. .....184 5.5 operation ...................................................................................................................... .......... 185 5.5.1 operation of each cl ock ........................................................................................................ .....185 5.5.2 clock output functi on .......................................................................................................... .......185 5.5.3 operation timi ng ............................................................................................................... .........186 5.6 clock monitor .................................................................................................................. ....... 189 chapter 6 16-bit timer/event counter aa (taa) .............................................................. 190 6.1 overview ....................................................................................................................... .......... 190 6.2 functions ...................................................................................................................... .......... 191 6.3 configuration.................................................................................................................. ........ 192 6.4 registers ...................................................................................................................... ........... 199 6.5 timer output operati ons....................................................................................................... 2 12 6.6 operation ...................................................................................................................... .......... 213 6.6.1 interval timer mode (taanmd2 to taanmd0 bi ts = 000) .......................................................... 221 6.6.2 external event count mode (taa mmd2 to taammd0 bits = 001) ............................................ 233 6.6.3 external trigger pulse output mode (taammd2 to taammd 0 bits = 010) ................................244 6.6.4 one-shot pulse output mode (taa mmd2 to taammd0 bits = 011).......................................... 256 6.6.5 pwm output mode (taammd2 to taammd0 bi ts = 100) ......................................................... 263 6.6.6 free-running timer mode (taanmd2 to taanmd0 bi ts = 101) ................................................. 272 6.6.7 pulse width measurement mode (taa mmd2 to taammd0 bits = 110).................................... 288
user?s manual u18279ej3v0ud 11 chapter 7 16-bit timer/event counter ab (tab) . .............................................................294 7.1 overview ....................................................................................................................... ...........294 7.2 functions ...................................................................................................................... ...........294 7.3 configuration .................................................................................................................. ........295 7.4 registers...................................................................................................................... ............297 7.5 timer output operations ............................................. ..........................................................3 12 7.6 operation ...................................................................................................................... ...........313 7.6.1 interval timer mode (tabnmd2 to tabnmd0 bi ts = 000).......................................................... 321 7.6.2 external event count mode (tabn md2 to tabnmd0 bits = 001).............................................. 333 7.6.3 external trigger pulse output mode (tabnmd2 to tabnmd 0 bits = 010) .................................. 344 7.6.4 one-shot pulse output mode (tabn md2 to tabnmd0 bits = 011) ........................................... 357 7.6.5 pwm output mode (tabnmd2 to tabnmd0 bi ts = 100)........................................................... 366 7.6.6 free-running timer mode (tabnmd2 to tabnmd0 bi ts = 101) ................................................. 377 7.6.7 pulse width measurement mode (tabn md2 to tabnmd0 bits = 110) ..................................... 396 chapter 8 16-bit timer/event counter t (tmt)... ...............................................................402 8.1 overview ....................................................................................................................... ...........402 8.2 functions ...................................................................................................................... ...........403 8.3 configuration .................................................................................................................. ........404 8.4 registers...................................................................................................................... ............408 8.5 timer output operations ............................................. ..........................................................4 28 8.6 operation ...................................................................................................................... ...........429 8.6.1 interval timer mode (ttnmd 3 to ttnmd0 bi ts = 0000) ............................................................. 437 8.6.2 external event count mode (tt mmd3 to ttmmd0 bits = 0001) ............................................... 446 8.6.3 external trigger pulse output mode (ttmmd3 to ttmmd 0 bits = 0010) ................................... 457 8.6.4 one-shot pulse output mode (tt mmd3 to ttmmd0 bits = 0011) ............................................ 470 8.6.5 pwm output mode (ttmmd3 to ttmmd0 bits = 0100) ............................................................ 477 8.6.6 free-running timer mode (ttnmd 3 to ttnmd0 bi ts = 0101) .................................................... 486 8.6.7 pulse width measurement mode ( ttmmd3 to ttmmd0 bits = 0110) ....................................... 502 8.6.8 triangular-wave pwm output mode ( ttmmd3 to ttmmd0 bits = 0111) ................................. 508 8.6.9 encoder count func tion......................................................................................................... ..... 511 8.6.10 encoder compare mode (ttmmd 3 to ttmmd0 bi ts = 1000) ................................................... 527 chapter 9 16-bit interval timer m (tmm).......... ...................................................................535 9.1 overview ....................................................................................................................... ...........535 9.2 configuration .................................................................................................................. ........536 9.3 control register............................................................................................................... .......537 9.4 operation ...................................................................................................................... ...........538 9.4.1 interval ti mer m ode............................................................................................................ ........ 538 9.5 cautions....................................................................................................................... ............542 chapter 10 motor control function...................... .............................................................543 10.1 functional overview............................................................................................................ ...543 10.2 configuration .................................................................................................................. ........544 10.3 control registers.............................................................................................................. ......548 10.4 operation ...................................................................................................................... ...........562
user?s manual u18279ej3v0ud 12 10.4.1 system outlin e ................................................................................................................. ..........562 10.4.2 dead-time control (generation of negative-phase wa ve signal ) .................................................567 10.4.3 interrupt culli ng func tion..................................................................................................... ........574 10.4.4 operation to rewrite regist er with transfe r functi on .................................................................... 581 10.4.5 taan tuning operation for a/d conver sion start trigger signal output ........................................599 10.4.6 a/d conversion start tri gger output f unction ...............................................................................602 chapter 11 watchdog timer functions ...................... ........................................................ 607 11.1 functions ...................................................................................................................... .......... 607 11.2 configuration.................................................................................................................. ........ 607 11.3 control registers .............................................................................................................. ..... 608 11.4 operation ...................................................................................................................... .......... 609 11.5 caution ........................................................................................................................ ............ 609 chapter 12 a/d converters 0 and 1 ....................... .............................................................. 61 0 12.1 features ....................................................................................................................... ........... 610 12.2 configuration.................................................................................................................. ........ 612 12.3 control registers .............................................................................................................. ..... 622 12.4 operation ...................................................................................................................... .......... 656 12.4.1 basic oper ation................................................................................................................ ..........656 12.4.2 input voltage and conv ersion re sult ...........................................................................................6 58 12.4.3 operati on m ode................................................................................................................. ........660 12.4.4 operation setti ng .............................................................................................................. .........660 12.4.5 operation of 1-c hannel conver sion ............................................................................................66 1 12.4.6 operation of multiple channel conv ersion ..................................................................................662 12.4.7 a/d trigger mode (no rmal operati on mode) ...............................................................................664 12.4.8 a/d trigger polling mode ( normal operati on mode) ....................................................................666 12.4.9 hardware trigger mode ( normal operati on mode) ......................................................................668 12.4.10 conversion channel specification mode (extension oper ation m ode) ........................................ 670 12.4.11 extension buffer mode (ext ension operati on mode) ..................................................................672 12.5 internal equivalent circuit.................................................................................................... . 678 12.6 cautions ....................................................................................................................... ........... 680 12.6.1 stopping conversi on operat ion .................................................................................................. 680 12.6.2 interval of trigger during conversion operati on in hardware trigger mode, conversion channel specification mode, and ex tension buffe r mode .........................................................................680 12.6.3 writing to adns cm regi ster..................................................................................................... ..680 12.6.4 a/d conversion start timing.................................................................................................... ....680 12.6.5 operation in standby mode...................................................................................................... ..681 12.6.6 timing of accepting trigger in conv ersion channel specification mode and extension buffer mode ......................................................................................................... ......681 12.6.7 variation of a/d c onversion re sults............................................................................................ 681 12.6.8 a/d conversion result hyster esis characte ristic s........................................................................681 12.6.9 a/d conversion trigger interval for continuous conversi on ......................................................... 682 12.7 how to read a/d converter characteristics table .. .......................................................... 683 chapter 13 a/d converter 2 ................................................................................................ ..... 687 13.1 features ....................................................................................................................... ........... 687
user?s manual u18279ej3v0ud 13 13.2 configuration .................................................................................................................. ........688 13.3 control registers.............................................................................................................. ......691 13.4 operation ...................................................................................................................... ...........697 13.4.1 basic oper ation................................................................................................................ .......... 697 13.4.2 trigger mode ................................................................................................................... .......... 699 13.4.3 operati on m ode................................................................................................................. ........ 700 13.5 operation in software trigger mode........................... ..........................................................707 13.6 internal equivalent circuit .................................................................................................... .711 13.7 cautions....................................................................................................................... ............713 13.8 how to read a/d converter characteristics table .... .........................................................716 chapter 14 asynchronous serial interface a (uarta) ..............................................717 14.1 mode switching between uarta and other serial interface............................................717 14.1.1 mode switching between uarta0 and csib0 .......................................................................... 717 14.1.2 mode switching between uarta1 and i 2 c................................................................................ 718 14.1.3 mode switching between uarta2 and csib1 .......................................................................... 719 14.2 features ....................................................................................................................... ............720 14.3 configuration .................................................................................................................. ........721 14.4 control registers.............................................................................................................. ......723 14.5 interrupt request signals ............................................ .......................................................... 728 14.6 operation ...................................................................................................................... ...........729 14.6.1 data fo rmat .................................................................................................................... ........... 729 14.6.2 uart trans missi on .............................................................................................................. ..... 731 14.6.3 continuous transmi ssion proc edure .......................................................................................... 732 14.6.4 uart rec eptio n................................................................................................................. ........ 734 14.6.5 reception errors............................................................................................................... ......... 735 14.6.6 parity types and operat ions .................................................................................................... ... 736 14.6.7 receive data noi se f ilter ...................................................................................................... ...... 737 14.7 dedicated baud rate generator................................... .........................................................738 14.8 cautions....................................................................................................................... ............745 chapter 15 asynchronous serial interface b (uartb) ..............................................746 15.1 mode switching between uartb and csib2......................................................................746 15.2 features ....................................................................................................................... ............747 15.3 configuration .................................................................................................................. ........748 15.4 control registers.............................................................................................................. ......752 15.5 interrupt request signals ............................................ .......................................................... 768 15.6 control modes .................................................................................................................. .......771 15.7 operation ...................................................................................................................... ...........775 15.7.1 data fo rmat .................................................................................................................... ........... 775 15.7.2 transmit oper ation ............................................................................................................. ....... 776 15.7.3 continuous transmi ssion operat ion ........................................................................................... 779 15.7.4 receive oper ation .............................................................................................................. ....... 780 15.7.5 reception error................................................................................................................ .......... 783 15.7.6 parity types and corre sponding operat ion ................................................................................. 784 15.7.7 receive data noi se f ilter ...................................................................................................... ...... 785 15.8 dedicated baud rate generator (brg) ................... .............................................................786
user?s manual u18279ej3v0ud 14 15.9 control flow ................................................................................................................... ........ 793 15.10 cautions ....................................................................................................................... ........... 804 chapter 16 clocked serial interface b (csib) ............................................................... 806 16.1 mode switching between csib and other serial interface ............................................... 806 16.1.1 mode switching between csib0 and ua rta0 ..........................................................................806 16.1.2 mode switching between csib1 and ua rta2 ..........................................................................807 16.1.3 mode switching between csib2 and ua rtb ............................................................................808 16.2 features ....................................................................................................................... ........... 809 16.3 configuration.................................................................................................................. ........ 810 16.4 control registers .............................................................................................................. ..... 812 16.5 operation ...................................................................................................................... .......... 819 16.5.1 single transfer mode (master mode, transmi ssion m ode) ......................................................... 819 16.5.2 single transfer mode (master mode, recept ion m ode)............................................................... 821 16.5.3 single transfer mode (master mode, transmission/rec eption m ode).......................................... 823 16.5.4 single transfer mode (slave mode, transmi ssion m ode) ............................................................ 825 16.5.5 single transfer mode (slave mode, recept ion m ode) ................................................................. 827 16.5.6 single transfer mode (slave mode, transmission/rec eption m ode) ............................................ 829 16.5.7 continuous transfer mode (master mode, transmi ssion m ode) ................................................. 831 16.5.8 continuous transfer mode (master mode, recept ion m ode)....................................................... 833 16.5.9 continuous transfer mode (master m ode, transmission/re ception mode) ..................................836 16.5.10 continuous transfer mode (slave mode, transmi ssion m ode).................................................... 840 16.5.11 continuous transfer mode (slave mode, recept ion m ode) ......................................................... 842 16.5.12 continuous transfer mode (slave m ode, transmission/re ception mode) ....................................845 16.5.13 reception error................................................................................................................ ..........849 16.5.14 clock ti ming ................................................................................................................... ............850 16.6 output pins .................................................................................................................... ......... 852 chapter 17 i 2 c bus ......................................................................................................................... . 853 17.1 mode switching between i 2 c and uarta1 ......................................................................... 853 17.2 features ....................................................................................................................... ........... 854 17.3 configuration.................................................................................................................. ........ 857 17.4 registers ...................................................................................................................... ........... 859 17.5 functions ...................................................................................................................... .......... 873 17.5.1 pin confi guratio n.............................................................................................................. ..........873 17.6 i 2 c bus definitions and control methods ....................... ..................................................... 874 17.6.1 start c onditi on................................................................................................................ ............874 17.6.2 addre sses...................................................................................................................... ............875 17.6.3 transfer direction specific ation ............................................................................................... ...876 17.6.4 ack ............................................................................................................................ ...............877 17.6.5 stop condi tion................................................................................................................. ...........878 17.6.6 wait state ..................................................................................................................... .............879 17.6.7 wait state canc ellation method................................................................................................. .881 17.7 i 2 c interrupt request signals (intiic) .......................... ........................................................ 882 17.7.1 master devic e operat ion ........................................................................................................ ....883 17.7.2 slave device operation (when receiving sl ave address data (addr ess matc h))..........................886 17.7.3 slave device operation (when re ceiving extens ion c ode) .......................................................... 890
user?s manual u18279ej3v0ud 15 17.7.4 operation without communica tion ............................................................................................. 894 17.7.5 arbitration loss operation (operation as slave after arbi tration loss) .......................................... 895 17.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ..................... 897 17.8 interrupt request signal (intiic) generation timing and wait control ...........................904 17.9 address match detection method................ .........................................................................905 17.10 error detection................................................................................................................ ........905 17.11 extension code................................................................................................................. ......905 17.12 arbitration.................................................................................................................... ............906 17.13 wakeup function ................................................................................................................ ....907 17.14 communication reservation ........................................... ......................................................908 17.14.1 when communication reservation function is enabled (iicf0.iicr sv0 bit = 0)......................... 908 17.14.2 when communication reservation function is disabled (iicf0.ii crsv0 bit = 1) ........................ 911 17.15 cautions....................................................................................................................... ............912 17.16 communication operations...................................................................................................913 17.16.1 master operation in si ngle master system ................................................................................. 914 17.16.2 master operation in multimaste r system .................................................................................... 915 17.16.3 slave oper ation ................................................................................................................ ......... 918 17.17 timing of data communication.............................................................................................921 chapter 18 bus control function............................ .............................................................92 8 18.1 features ....................................................................................................................... ............928 18.2 bus control pins............................................................................................................... ......929 18.2.1 pin status during internal rom, internal ram, and on-chip per ipheral i/o access .................... 929 18.3 memory block function .........................................................................................................9 30 18.3.1 chip select c ontrol f unction ................................................................................................... .... 930 18.4 bus cycle type control function ................................ .........................................................931 18.5 bus access..................................................................................................................... .........932 18.5.1 number of a ccess cl ocks ........................................................................................................ .. 932 18.5.2 bus sizing functi on ............................................................................................................ ........ 933 18.5.3 endian f uncti on................................................................................................................ .......... 934 18.5.4 bus wid th...................................................................................................................... ............. 934 18.6 wait function .................................................................................................................. ........941 18.6.1 programmable wa it func tion ..................................................................................................... . 941 18.6.2 external wait func tion ......................................................................................................... ....... 944 18.6.3 relationship between programmabl e wait and exte rnal wa it ..................................................... 944 18.6.4 bus cycles in which wait function is valid ................................................................................... 94 5 18.7 idle state insertion function......................................... ......................................................... 946 18.8 bus timing..................................................................................................................... ..........948 18.9 bus priority order............................................................................................................. ......958 18.10 boundary operation conditions ..................................... ......................................................958 18.10.1 program space .................................................................................................................. ........ 958 18.10.2 data s pace ..................................................................................................................... ........... 958 chapter 19 dma functions (dma controller)..... .............................................................959 19.1 features ....................................................................................................................... ............959 19.2 configuration .................................................................................................................. ........960 19.3 control registers.............................................................................................................. ......961
user?s manual u18279ej3v0ud 16 19.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 )..............................................................961 19.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3)....................................................... 963 19.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3 )................................................................965 19.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3 ) ...................................................966 19.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3 )........................................................967 19.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3) ............................................................. 969 19.4 transfer modes................................................................................................................. ...... 973 19.4.1 single trans fer m ode ........................................................................................................... ......973 19.4.2 single-step tr ansfer mode...................................................................................................... ....975 19.4.3 block trans fer m ode............................................................................................................ .......976 19.5 transfer types................................................................................................................. ....... 977 19.5.1 2-cycle tr ansfer ............................................................................................................... ...........977 19.6 transfer target ................................................................................................................ ....... 977 19.6.1 transfer type and tr ansfer ta rget .............................................................................................. .977 19.7 dma channel priorities ......................................................................................................... 977 19.8 next address setting function......................................... .................................................... 978 19.9 dma transfer start fact ors .................................................................................................. 979 19.10 forcible termination........................................................................................................... ... 980 19.11 times related to dma transfer.................................... ........................................................ 981 19.12 cautions ....................................................................................................................... ........... 981 19.13 dma transfer end ............................................................................................................... ... 982 chapter 20 interrupt/exception processing fu nction............................................... 983 20.1 features ....................................................................................................................... ........... 983 20.2 non-maskable interrupts ....................................................................................................... 9 88 20.2.1 operat ion...................................................................................................................... .............989 20.2.2 restore ........................................................................................................................ ..............991 20.2.3 non-maskable interrupt status fl ag (np) ....................................................................................992 20.3 maskable interrupts ............................................................................................................ ... 993 20.3.1 operat ion...................................................................................................................... .............993 20.3.2 restore ........................................................................................................................ ..............995 20.3.3 priorities of ma skable inte rrupts .............................................................................................. ..996 20.3.4 interrupt control r egisters ( xxicn) ............................................................................................ 1000 20.3.5 interrupt mask registers 0 to 5 (imr0 to imr5 )........................................................................1005 20.3.6 in-service priority register (ispr)............................................................................................ .1008 20.3.7 maskable interrupt st atus flag (id)...........................................................................................1 009 20.4 external interrupt request input pins (intp 00 to intp18, intadt0, intadt1) ........... 1010 20.4.1 noise elim inatio n .............................................................................................................. .......1010 20.4.2 edge detec tion................................................................................................................. ........1010 20.5 software exception ............................................................................................................. . 1015 20.5.1 operat ion...................................................................................................................... ...........1015 20.5.2 restore ........................................................................................................................ ............1016 20.5.3 exception stat us flag (ep) ..................................................................................................... ..1017 20.6 exception trap ................................................................................................................. .... 1017 20.6.1 illegal opcode definit ion ...................................................................................................... .....1017 20.6.2 debug tr ap..................................................................................................................... ..........1019 20.7 multiple interrupt servicing cont rol................................................................................... 1021 20.8 interrupt response time of cpu ........................................................................................ 1023
user?s manual u18279ej3v0ud 17 20.9 periods in which cpu does not acknowledge interr upts ...............................................1024 20.10 caution........................................................................................................................ ...........1024 chapter 21 standby function...................................... .......................................................... .1025 21.1 overview ....................................................................................................................... .........1025 21.2 control registers.............................................................................................................. ....1027 21.3 halt mode ...................................................................................................................... ......1029 21.3.1 setting and operat ion st atus................................................................................................... . 1029 21.3.2 releasing ha lt m ode ............................................................................................................ 1029 21.4 idle mode...................................................................................................................... ........1031 21.4.1 setting and operat ion st atus................................................................................................... . 1031 21.4.2 releasing id le m ode ............................................................................................................ . 1031 21.5 stop mode ...................................................................................................................... ......1033 21.5.1 setting and operat ion st atus................................................................................................... . 1033 21.5.2 releasing st op m ode............................................................................................................ 1033 21.6 securing oscillation stabilization time .................. ...........................................................1035 chapter 22 reset functions...................................... ........................................................... ...1036 22.1 overview ....................................................................................................................... .........1036 22.2 control register............................................................................................................... .....1036 22.3 operation ...................................................................................................................... .........1038 chapter 23 low-voltage detector........................... ...........................................................1041 23.1 functions ...................................................................................................................... .........1041 23.2 configuration .................................................................................................................. ......1041 23.3 control registers.............................................................................................................. ....1042 23.4 operation ...................................................................................................................... .........1044 23.4.1 to use for inter nal rese t signal ............................................................................................... . 1044 23.4.2 to use for interr upt ........................................................................................................... ....... 1046 chapter 24 power-on clear ci rcuit ...................................................................................1047 24.1 function ....................................................................................................................... ..........1047 24.2 configuration .................................................................................................................. ......1047 24.3 operation ...................................................................................................................... .........1048 chapter 25 regulator ........................................................................................................ ........1049 25.1 overview ....................................................................................................................... .........1049 25.2 operation ...................................................................................................................... .........1050 chapter 26 on-chip debug function....................... .............................................................1051 26.1 debugging using dcu .........................................................................................................105 2 26.1.1 circuit connecti on exam ples.................................................................................................... 1052 26.1.2 interface signal s .............................................................................................................. ........ 1056 26.1.3 maskable f uncti ons............................................................................................................. ..... 1057 26.1.4 cauti ons ....................................................................................................................... ........... 1058
user?s manual u18279ej3v0ud 18 26.2 debugging without using dcu ........................................ .................................................. 1059 26.2.1 circuit connecti on exam ples.................................................................................................... 1059 26.2.2 maskable f uncti ons............................................................................................................. .....1062 26.2.3 securing of user resour ces..................................................................................................... .1062 26.2.4 cauti ons ....................................................................................................................... ...........1068 26.3 rom security function ....................................................................................................... 106 9 26.3.1 security id .................................................................................................................... ...........1069 26.3.2 setti ng ........................................................................................................................ .............1070 chapter 27 flash memory .................................................................................................... .... 1071 27.1 features ....................................................................................................................... ......... 1071 27.2 memory configuratio n......................................................................................................... 10 72 27.3 functional overview ............................................................................................................ 1073 27.3.1 erase units.................................................................................................................... ...........1075 27.3.2 security functi on .............................................................................................................. ........1075 27.4 writing with flash memory progr ammer........................................................................... 1077 27.5 flash memory programming environment .................... ................................................... 1078 27.6 communication method of flash memory programmi ng................................................ 1079 27.7 pin processing during flash memory programming.... ................................................... 1085 27.7.1 power s upply ................................................................................................................... ........1085 27.7.2 pins used...................................................................................................................... ...........1085 27.7.3 reset pin...................................................................................................................... .........1088 27.7.4 flmd0 and flmd 1 pins ..........................................................................................................1 088 27.7.5 port pins ...................................................................................................................... ............1089 27.7.6 other signal pi ns.............................................................................................................. ........1089 27.8 flash memory programming mode .................................................................................... 1090 27.8.1 flash memory cont rol ........................................................................................................... ...1090 27.8.2 selection of comm unication mode ...........................................................................................1091 27.8.3 communication commands ..................................................................................................... 1092 27.9 rewriting by self programming.. ........................................................................................ 1094 27.9.1 overvi ew....................................................................................................................... ...........1094 27.9.2 featur es ....................................................................................................................... ...........1095 27.9.3 standard self progr amming fl ow ..............................................................................................109 6 27.9.4 flash f uncti ons ................................................................................................................ ........1097 27.9.5 pin proc essi ng ................................................................................................................. ........1097 27.9.6 internal res ources used ........................................................................................................ ...1098 chapter 28 electrical specifications ....................... ........................................................ 1099 28.1 v850e/if3 ...................................................................................................................... ........ 1099 28.1.1 absolute maxi mum rati ngs ......................................................................................................1 099 28.1.2 capacit ance.................................................................................................................... .........1100 28.1.3 operating conditi ons........................................................................................................... .....1100 28.1.4 clock oscillator c haracteri stics............................................................................................... ..1101 28.1.5 regulator char acterist ics ...................................................................................................... ...1102 28.1.6 dc characte ristics ............................................................................................................. ......1103 28.1.7 data retention c haracteri stics ................................................................................................. .1105 28.1.8 ac characte ristics............................................................................................................. .......1106
user?s manual u18279ej3v0ud 19 28.1.9 characteristics of a/d converters 0 and 1 ............................................................................... 1116 28.1.10 characteristics of a/d conver ter 2........................................................................................... 11 17 28.1.11 operational amplifier characteri stics ....................................................................................... 111 8 28.1.12 comparator char acterist ics..................................................................................................... . 1119 28.1.13 power-on-clear ci rcuit (poc)................................................................................................... 1120 28.1.14 low-voltage detec tor (l vi) ..................................................................................................... . 1121 28.1.15 flash memory programmi ng characteri stics ............................................................................ 1122 28.2 v850e/ig3...................................................................................................................... .........1123 28.2.1 absolute maxi mum rati ngs ...................................................................................................... 1 123 28.2.2 capacit ance .................................................................................................................... ........ 1124 28.2.3 operating conditi ons ........................................................................................................... .... 1124 28.2.4 clock oscillator c haracteri stics ............................................................................................... . 1125 28.2.5 regulator char acterist ics ...................................................................................................... ... 1126 28.2.6 dc characte ristics ............................................................................................................. ...... 1127 28.2.7 data retention c haracteri stics ................................................................................................. . 1129 28.2.8 ac characte ristics ............................................................................................................. ...... 1130 28.2.9 characteristics of a/d converters 0, 1 ..................................................................................... 1148 28.2.10 characteristics of a/d conver ter 2........................................................................................... 11 49 28.2.11 operational amplifier characteri stics ....................................................................................... 115 0 28.2.12 comparator char acterist ics..................................................................................................... . 1151 28.2.13 power-on-clear ci rcuit (poc)................................................................................................... 1152 28.2.14 low-voltage detec tor (l vi) ..................................................................................................... . 1153 28.2.15 flash memory programmi ng characteri stics ............................................................................ 1154 chapter 29 package drawings....................................... ........................................................1 155 chapter 30 recommended soldering conditions .. .......................................................1159 appendix a cautions......................................................................................................... ............1161 a.1 restriction on conflict between sld instruction a nd interrupt request.........................1161 a.1.1 descrip tion .................................................................................................................... .......... 1161 a.1.2 counterm easur e................................................................................................................. ..... 1161 appendix b register index .................................................................................................. ......1162 appendix c instruction set list........................................................................................... .1175 c.1 conventions .................................................................................................................... ......1175 c.2 instruction set (in alphabetical order).................... ...........................................................1178 appendix d revision history ................................................................................................ ....1185 d.1 major revisions in this edition................................... ........................................................1185 d.2 revision history up to previous edition ................. ...........................................................1186
user?s manual u18279ej3v0ud 20 chapter 1 introduction the v850e/if3 and v850e/ig3 are produc ts of the nec electronics v850 si ngle-chip microcontrollers. this chapter gives an outline of the v850e/if3 and v850e/ig3. 1.1 overview the v850e/if3 and v850e/ig3 are 32-bit single-chip mi crocontrollers that use the v850e1 cpu core and incorporate rom/ram and various peripheral functions such as dma controller, timer/counter, watchdog timer, serial interfaces, a/d converter, and on-chip debug function. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850e/if3 and v850e/ig3 feature instructions such as multiply instruct ions, saturated operation instructions, and bit manipulation instructions realized by a hardware multiplier, as optimum in structions for digital servo control applications. moreover, as a real-time control system, the v850e/if3 and v850e /ig3 enable an extremely high cost-performance for applications such as motor inverter control. table 1-1 lists the v850e /if3 and v850e/ig3 products. table 1-1. v850e/if3, v850e/ig3 product list rom maskable interrupt function part number package type size ram size operating frequency (max.) external internal non-maskable interrupt pd70f3451 80gc 128 kb 8 kb v850e/if3 pd70f3452 80gc 256 kb 12 kb 15 73 pd70f3453 100gc 128 kb 8 kb pd70f3453 100gf 128 kb 8 kb pd70f3454 100gc 256 kb 12 kb pd70f3454 100gf 256 kb 12 kb v850e/ig3 pd70f3454 161f1 flash memory 256 kb 12 kb 64 mhz 21 74 1 remarks 1. 80gc (v850e/if3): 80-pin plastic lqfp (14 14) 100gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) 100gf (v850e/ig3): 100-pin plastic lqfp (14 20) 161f1(v850e/ig3): 161-pin plastic fbga (10 10) 2. the part numbers of the v850e/ig3 are shown as follows in this manual. ? gf versions pd70f3453gf-gas-ax, 70f3454gf-gas-ax
chapter 1 introduction user?s manual u18279ej3v0ud 21 table 1-2 shows the differences in func tions between the v850e/if3 and v850e/ig3. table 1-2. differences in func tions between v850e/if3 and v850e/ig3 item v850e/if3 v850e/ig3 i/o 44 56 input 4 8 port function on-chip pull-up resistor 44 56 interrupt source external interrupt: 15 internal interrupt: 74 external interrupt: 21 internal interrupt: 75 external bus function none provided ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) timers aa0 to aa4 timer aa0 (without i/o) timer aa1 (without i/o) timer aa2 timer aa3 (without i/o) timer aa4 timer aa0 (without i/o) timer aa1 (without i/o) timer aa2 timer aa3 timer aa4 timers t0, t1 timer t0 (without i/o) timer t1 timer t0 timer t1 motor control function high-impedance output control pin toa2off tob0off tob1off toa2off toa3off tob0off tob1off a/d converter 2 analog input 4 channels 8 channels on-chip debug function on-chip debug emulator nimicube2 nimicube nimicube2 power supply for external pin ev dd0 , ev dd1 ev dd0 to ev dd2 package 80-pin plastic lqfp (14 14) 100-pin plastic lqfp (14 14) 100-pin plastic lqfp (14 20) 161-pin plastic fbga (10 10)
chapter 1 introduction user?s manual u18279ej3v0ud 22 1.2 v850e/if3 1.2.1 features (v850e/if3) { minimum instruction execution time: 15.6 ns (at internal 64 mhz operation) { general-purpose registers: 32 bits u 32 { cpu features: signed multiplication (16 bits u 16 bits o 32 bits or 32 bits u 32 bits o 64 bits): 1 to 2 clocks saturated operation instructions (wit h overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions part number internal rom internal ram p pd70f3451 128 kb (flash memory) 8 kb { internal memory: p pd70f3452 256 kb (flash memory) 12 kb { on-chip debug function: supports minicube ? 2. { interrupts/exceptions: non-maskable interrupts: 1 source (external: none, internal: 1) maskable interrupts: 88 sources (external: 15, internal: 73) software exceptions: 32 sources exception traps: 2 sources { dma controller: 4 channels transfer unit: 8 bits/16 bits maximum transfer count: 65536 (2 16 ) transfer type: 2-cycle transfer modes: single/single step/block transfer targets: on-chip peripheral i/o l internal ram on-chip peripheral i/o l on-chip peripheral i/o transfer request: on-c hip peripheral i/o/software next address setting function { i/o lines: total: 48 (input ports: 4, i/o ports: 44)
chapter 1 introduction user?s manual u18279ej3v0ud 23 { timer/counter function: 16-bit interval timer m (tmm): 4 channels 16-bit timer/event counter aa (taa): 5 channels 16-bit timer/event counter ab (tab): 2 channels 16-bit timer/event counter t (tmt): 2 channels motor control function (uses timer tab: 2 channels (tab0, tab1), taa: 2 channels (taa0, taa1)) 16-bit accuracy 6-phase pwm function with deadtime: 2 channels high-impedance output control function a/d trigger generation by timer tuning operation function arbitrary cycle setting function arbitrary deadtime setting function watchdog timer: 1 channel { serial interfaces: asynchronous serial interface a (uarta) asynchronous serial interface b (uartb) clocked serial interface b (csib) i 2 c bus interface (i 2 c) uarta0/csib0: 1 channel uarta1/i 2 c: 1 channel uarta2/csib1: 1 channel uartb/csib2: 1 channel { a/d converter: 12-bit resolution a/d converters (a/d converters 0 and 1): 5 channels + 5 channels (2 units) the one a/d converter 0 channel and three a/d converter 1 channels are provided with an operational amplifier fo r input level amplification and a comparator for overvoltage detection. 10-bit resolution a/d converter (a/d converter 2): 4 channels { clock generator: 4 to 8 mhz resonator connectable (external clock input prohibited) multiplication function by pll clock synthesizer (fixed to multiplication by eight, f xx = 32 to 64 mhz) cpu clock division function (f xx , f xx /2, f xx /4, f xx /8) { power-save function: halt/idle/stop mode { power-on-clear function: { low-voltage detection function: { package: 80-pin plastic lqfp (14 u 14) o operation supply voltage: v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v (when a/d converter 0, 1 or 2 is operating) v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v (when none of a/d converters 0 to 2 is operating)
chapter 1 introduction user?s manual u18279ej3v0ud 24 1.2.2 application fields (v850e/if3) ? consumer equipment (such as inverter air condition ers, washing machines, driers, refrigerators, etc.) ? industrial equipment (such as motor cont rol, general-purpose inverters, etc.) 1.2.3 ordering information (v850e/if3) part number package internal rom pd70f3451gc-ubt-a 80-pin plastic lqfp (14 14) flash memory (128 kb) pd70f3452gc-ubt-a 80-pin plastic lqfp (14 14) flash memory (256 kb) remark the v850e/if3 microcontrollers are lead-free products.
chapter 1 introduction user?s manual u18279ej3v0ud 25 1.2.4 pin configur ation (v850e/if3) ? 80-pin plastic lqfp (14 14) pd70f3451gc-ubt-a pd70f3452gc-ubt-a top view 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ani00/ani05 ani01 ani02 ani03/cref0l ani04/cref0f av ss0 av refp0 av dd0 av dd1 av refp1 av ss1 ani14/cref1f ani13/cref1l ani12/ani17 ani11/ani16 ani10/ani15 p73/ani23 p72/ani22 p71/ani21 p70/ani20 pdl5/flmd1 pdl6 pdl7 pdl8 pdl9 ev dd0 ev ss0 p37/sckb2/intp12 p36/sob2/txdb p35/sib2/rxdb p34/sckb1/intp11 p33/sob1/txda2 p32/sib1/rxda2 p31/txda1/sda p30/rxda1/scl p47/toa41/tia41/intp18 p46/toa40/tia40/intp17 p45/tenc11/tit11/tot11/intp16 p44/tenc10/evtt1/intp15 p43/tecr1/tit10/tot10/intp14 p42/sckb0/intp13 p41/sob0/txda0 p40/sib0/rxda0 flmd0 p27 reset x2 x1 v ss0 regc0 v dd0 p26/tob10/tob1off/intp10/adtrg1/intadt1 p25/tob1b3/trgb1 p24/tob1t3/evtb1 p23/tob1b2/tib10 p22/tob1t2/tib13/tob13 p21/tob1b1/tib12/tob12 p20/tob1t1/tib11/tob11 av ss2 av dd2 pdl4 pdl3 pdl2 pdl1 pdl0 v ss1 regc1 v dd1 p01/toa21/tia21/intp01 p00/toa20/tia20/toa2off/intp00 p17/tob00/intp09 p16/tob0off/intp08/adtrg0/intadt0 p15/tob0b3/trgb0 p14/tob0t3/evtb0 p13/tob0b2/tib00 p12/tob0t2/tib03/tob03 p11/tob0b1/tib02/tob02 p10/tob0t1/tib01/tob01 ev ss1 ev dd1
chapter 1 introduction user?s manual u18279ej3v0ud 26 pin identification (v850e/if3) adtrg0, adtrg1: a/d trigger input scl: serial clock ani00 to ani05, sda: serial data ani10 to ani17, sib0 to sib2: serial input ani20 to ani23: analog input sob0 to sob2: serial output av dd0 to av dd2 : analog power supply tecr1: timer encoder clear input av refp0 , a vrefp1 : analog reference voltage tenc10, tenc11: timer encoder input av ss0 to av ss2 : analog ground tia20, tia21, cref0f, cref1f, tia40, tia41, cref0l, cref1l: comparator refer ence voltage tib00 to tib03, ev dd0 , ev dd1 : power supply for port tib10 to tib13, ev ss0 , ev ss1 : ground for port tit10, tit11: timer trigger input evtb0, evtb1, toa20, toa21, evtt1: timer event count input toa40, toa41, flmd0, flmd1: flash programming mode tob00 to tob03, intadt0, intadt1, tob0b1 to tob0b3, intp00, intp01, to b0t1 to tob0t3, intp08 to intp18: external inte rrupt input tob10 to tob13, p00, p01: port 0 tob1b1 to tob1b3, p10 to p17: port 1 tob1t1 to tob1t3, p20 to p27: port 2 tot 10, tot11: timer output p30 to p37: port 3 toa2off, p40 to p47: port 4 tob0off, tob1off: timer output off p70 to p73: port 7 trgb0, trgb1: timer trigger input pdl0 to pdl9: port dl txda0 to txda2, regc0, regc1: regulator control txdb: transmit data reset: reset v dd0 , v dd1 : power supply rxda0 to rxda2, v ss0 , v ss1 : ground rxdb: receive data x1, x2: clock oscillator pin sckb0 to sckb2: serial clock
chapter 1 introduction user?s manual u18279ej3v0ud 27 1.2.5 function blocks (v850e/if3) (1) internal block diagram intp00, intp01, intp08 to intp18 intc tmm 4 channels tab 2 channels uarta 3 channels csib 3 channels ram note 2 cpu 32-bit barrel shifter pc system register general-purpose registers (32 bits 32) alu multiplier (32 32 64) ports cg pll regulator 2 channels bcu x1 rg clm reset x2 v dd0 v ss0 regc0 toa20, toa21, toa40, toa41 taa 5 channels tia20, tia21, tia40, tia41, toa2off tot10, tot11 tmt 2 channels tecr1, tenc10, tenc11, evtt1, tit10, tit11 tib00 to tib03, tib10 to tib13, evtb0, evtb1, trgb0, trgb1, tob0off, tob1off tob00 to tob03, tob10 to tob13, tob0t1 to tob0t3, tob1t1 to tob1t3, tob0b1 to tob0b3, tob1b1 to tob1b3 txda0 to txda2 rxda0 to rxda2 sob0 to sob2 sib0 to sib2 sckb0 to sckb2 instruction queue flmd0 flmd1 ev dd0 ev ss0 ev dd1 ev ss1 wdt uartb 1 channel txdb rxdb i 2 c 1 channel scl sda p00, p01 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p70 to p73 pdl0 to pdl09 rom note 1 poc/lvi ani00/ani05, ani01 to ani04 ani20 to ani23 adc0 adc2 adtrg0, intadt0 cref0l, cref0f av dd1 av refp1 av ss0 operational amplifier 1 comparator 1 ani10/ani15, ani11/ani16, ani12/ani17, ani13, ani14 adc1 adtrg1, intadt1 cref1l, cref1f av dd2 av ss2 av ss1 operational amplifier 3 comparator 3 dmac v dd1 v ss1 regc1 av dd0 av refp0 notes 1. pd70f3451: 128 kb (flash memory) pd70f3452: 256 kb (flash memory) 2. pd70f3451: 8 kb pd70f3452: 12 kb
chapter 1 introduction user?s manual u18279ej3v0ud 28 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. (b) bus control unit (bcu) the bcu controls the internal bus. (i) dma controller (dmac) this controller controls data transfer between on-ch ip peripheral i/o and internal ram or on-chip peripheral i/o and on-chip peripher al i/o instead of the cpu. the transfer type is two-cycle transfe r, and single transfer, single-step transfer, and block transfer are used in transfer mode. (c) rom this is flash memory that is mapped from address 00000000h. during instruction fetch, rom/flash memory can be accessed from the cpu in 1-clock cycles. the internal rom capacity and area differ as follows depending on the product. part number internal rom capacity internal rom area pd70f3451 128 kb (flash memory) x0000000h to x001ffffh pd70f3452 256 kb (flash memory) x0000000h to x003ffffh (d) ram the internal ram capacity and area differ as follows depending on the product. during instruction fetch or data access, data c an be accessed from the cpu in 1-clock cycles. part number internal ram capacity internal ram area pd70f3451 8 kb xfffc000h to xfffdfffh pd70f3452 12 kb xfffc000h to xfffefffh (e) interrupt controller (intc) this controller handles hardware interrupt reques ts (intp00, intp01, intp08 to intp18, intadt0, intadt1) from on-chip peripheral hardware and external ha rdware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple -interrupt servicing control can be performed. (f) clock generator (cg) the clock generator includes two basic operation mo des: pll mode (fixed to multiplication by eight) and clock-through mode. it generates four types of clocks (f xx , f xx /2, f xx /4, f xx /8), and supplies one of them as the operating clock for the cpu (f cpu ).
chapter 1 introduction user?s manual u18279ej3v0ud 29 (g) timer/counter the v850e/if3 incorporates four 16-bit interval ti mer m (tmm) channels, five 16-bit timer/event counter aa (taa) channels, two 16-bit timer/event counter ab (t ab) channels, and two 16-bit timer/event counter t (tmt) channels, and can measure pulse interval width s or frequency, enable an inverter function for motor control, and output a programmable pulse. (h) watchdog timer (wdt) a watchdog timer is equipped to detect program loops, system abnormalities, etc. it generates a non-maskable interrupt request signal (intwd t) or internal reset signal (wdtres) after an overflow occurs. (i) serial interface the v850e/if3 incorporates eight seri al interface channels: for three asynchronous serial interface a (uarta) channels, one asynchronous serial interface b (uartb) channel, three clocked serial interface b (csib) channels, and one i 2 c bus interface (i 2 c) channel. of these, uarta0 and csib0, uarta1 and i 2 c, uarta2 and csib1, and ua rtb and csib2 share a pin. for uarta, data is transferred via the txdan and rxdan pins (n = 0 to 2). for uartb, data is transferred via the txdb and rxdb pins. for csib, data is transferred via the sobn, sibn, and sckbn pins (n = 0 to 2). for i 2 c, data is transferred via the scl and sda pins. (j) a/d converter (adc) one channel is provided for each of the high-speed, high-resolution 12-bit a/d converters (adc0, adc1) (total of two channels), which have five analog input pi ns respectively, and one channel is provided for the 10-bit a/d converter (adc2), which has four analog input pins. both one of the adc0 channels and three of the adc1 channels include an operational amplifier and a comparator so that these a/d conv erters can amplify an analog input voltage and detect overvoltage input. (k) on-chip debug function an on-chip debug function supporting minicube2 can be used, so that a simple, inexpensive debug environment can be organized. (l) ports as shown below, the following ports have general -purpose port functions and control pin functions. port i/o alternate function port 0 2-bit i/o timer/counter i/o, external interrupt input port 1 8-bit i/o timer/counter i/o, external trigger input of a/d converter 0, external interrupt input port 2 8-bit i/o timer/counter i/o, external trigger input of a/d converter 1, external interrupt input port 3 8-bit i/o serial interfac e i/o, external interrupt input port 4 8-bit i/o serial interface i/o, ti mer/counter i/o, external interrupt input port 7 4-bit input a/d converter 2 input port dl 10-bit i/o ?
chapter 1 introduction user?s manual u18279ej3v0ud 30 1.3 v850e/ig3 1.3.1 features (v850e/ig3) { minimum instruction execution time: 15.6 ns (at internal 64 mhz operation) { general-purpose registers: 32 bits u 32 { cpu features: signed multiplication (16 bits u 16 bits o 32 bits or 32 bits u 32 bits o 64 bits): 1 to 2 clocks saturated operation instructions (wit h overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions { memory space ( p pd70f3454gc-8ea-a and 70f3454f1-da9-a only): 256 mb of linear address space (program/data sharing) chip select output function: 2 spaces memory block division function: 2 mb/block x external bus interface: multiplexed bus mode: 16-bit address bus 8-bit/16-bit data bus separate bus mode: 8-bit address bus 8-bit/16-bit data bus 8-bit/16-bit data bus sizing function external bus frequency switch function: 32/16 mhz wait function ? programmable wait function ? external wait function idle state function address setup wait function part number internal rom internal ram p pd70f3453 128 kb (flash memory) 8 kb { internal memory: p pd70f3454 256 kb (flash memory) 12 kb { on-chip debug function: supports minicube and minicube2. { interrupts/exceptions: non-maskable interrupt s: 1 source (external: none, internal: 1) maskable interrupts: 95 sources (external: 21, internal: 74) software exceptions: 32 sources exception traps: 2 sources
chapter 1 introduction user?s manual u18279ej3v0ud 31 { dma controller: 4 channels transfer unit: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: 2-cycle transfer mode: single/single step/block transfer target: on-chip peripheral i/o l internal ram on-chip peripheral i/o l on-chip peripheral i/o transfer request: on-c hip peripheral i/o/software next address setting function { i/o lines: total: 64 (input ports: 8, i/o ports: 56) { timer/counter function: 16-bit interval timer m (tmm): 4 channels 16-bit timer/event counter aa (taa): 5 channels 16-bit timer/event counter ab (tab): 2 channels 16-bit timer/event counter t (tmt): 2 channels motor control function (uses timer tab: 2 channels (tab0 and tab1), taa: 2 channels (taa0 and taa1)) 16-bit accuracy 6-phase pwm function with deadtime: 2 channels high-impedance output control function a/d trigger generation by timer tuning operation function arbitrary cycle setting function arbitrary deadtime setting function watchdog timer: 1 channel { serial interfaces: asynchronous serial interface a (uarta) asynchronous serial interface b (uartb) clocked serial interface b (csib) i 2 c bus interface (i 2 c) uarta0/csib0: 1 channel uarta1/ i 2 c: 1 channel uarta2/csib1: 1 channel uartb/csib2: 1 channel { a/d converter: 12-bit resolution a/d converters (a/d converters 0 and 1): 5 channels + 5 channels (2 units) the one a/d converter 0 channel and three a/d converter 1 channels are provided with an operational amplifier fo r input level amplification and a comparator for overvoltage detection. 10-bit resolution a/d converter (a/d converter 2): 8 channels { clock generator: 4 to 8 mhz resonator connectable (external clock input prohibited) multiplication function by pll clock synthesizer (fixed to multiplication by eight, f xx = 32 to 64 mhz) cpu clock division function (f xx , f xx /2, f xx /4, f xx /8)
chapter 1 introduction user?s manual u18279ej3v0ud 32 { power-save function: halt/idle/stop mode { power-on-clear function { low-voltage detection function { package: 100-pin plastic lqfp (fine pitch) (14 u 14) 100-pin plastic lqfp (14 u 20) 161-pin plastic fbga (10 u 10) { operation supply voltage: v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v (when a/d converter 0, 1 or 2 is operating) v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v (when none of a/d converters 0 to 2 is operating) 1.3.2 application fields (v850e/ig3) x consumer equipment (such as inverter air condition ers, washing machines, driers, refrigerators, etc.) x industrial equipment (such as motor cont rol, general-purpose inverters, etc.) 1.3.3 ordering information (v850e/ig3) part number package internal rom p pd70f3453gc-8ea-a 100-pin plasti c lqfp (fine pitch) (14 u 14) flash memory (128 kb) p pd70f3453gf-gas-ax 100-pin plastic lqfp (14 u 20) flash memory (128 kb) p pd70f3454gc-8ea-a 100-pin plastic lqfp (fine pitch) (14 u 14) flash memory (256 kb) p pd70f3454gf-gas-ax 100-pin plastic lqfp (14 u 20) flash memory (256 kb) p pd70f3454f1-da9-a 161-pin plastic fbga (10 u 10) flash memory (256 kb) remark the v850e/ig3 microcontroller s are lead-free products.
chapter 1 introduction user?s manual u18279ej3v0ud 33 1.3.4 pin configur ation (v850e/ig3) ? 100-pin plastic lqfp (fine pitch) (14 14) pd70f3453gc-8ea-a pd70f3454gc-8ea-a top view 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ev ss1 ani00/ani05 ani01 ani02 ani03/cref0l ani04/cref0f av ss0 av refp0 av dd0 av dd1 av refp1 av ss1 ani14/cref1f ani13/cref1l ani12/ani17 ani11/ani16 ani10/ani15 p77/ani27 p76/ani26 p75/ani25 p74/ani24 p73/ani23 p72/ani22 p71/ani21 p70/ani20 pdl6/ad6 note pdl7/ad7 note pdl8/ad8 note pdl9/ad9 note pdl10/ad10 note pdl11/ad11 note pdl12/ad12 note pdl13/ad13 note pdl14/ad14 note pdl15/ad15 note ev dd0 ev ss0 p07/intp07/clkout note p37/sckb2/intp12/astb note p36/sob2/txdb p35/sib2/rxdb p34/sckb1/intp11/cs0 note p33/sob1/txda2 p32/sib1/rxda2/cs1 note p31/txda1/sda p30/rxda1/scl p47/toa41/tia41/intp18/rd note p46/toa40/tia40/intp17/wr0 note p45/tenc11/tit11/tot11/intp16/wr1 note p44/tenc10/evtt1/intp15/wait note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pdl5/ad5 note /flmd1 pdl4/ad4 note pdl3/ad3 note pdl2/ad2 note pdl1/ad1 note pdl0/ad0 note p06/tenc01/tit01/tot01/intp06 p05/tenc00/evtt0/intp05 p04/tecr0/tit00/tot00/intp04 v ss1 regc1 v dd1 p03/toa31/tia31/intp03 p02/toa30/tia30/toa3off/intp02 p01/toa21/tia21/intp01 p00/toa20/tia20/toa2off/intp00 p17/tob00/intp09/a7 note p16/tob0off/intp08/adtrg0/intadt0/a6 note p15/tob0b3/trgb0/a5 note p14/tob0t3/evtb0/a4 note p13/tob0b2/tib00/a3 note p12/tob0t2/tib03/tob03/a2 note p11/tob0b1/tib02/tob02/a1 note p10/tob0t1/tib01/tob01/a0 note ev dd1 p43/tecr1/tit10/tot10/intp14 p42/sckb0/intp13/ddi p41/sob0/txda0/dck p40/sib0/rxda0 flmd0 p27/dms ddo drst ev ss2 ev dd2 reset x2 x1 v ss0 regc0 v dd0 p26/tob10/tob1off/intp10/adtrg1/intadt1 p25/tob1b3/trgb1 p24/tob1t3/evtb1 p23/tob1b2/tib10 p22/tob1t2/tib13/tob13 p21/tob1b1/tib12/tob12 p20/tob1t1/tib11/tob11 av ss2 av dd2 note available in pd70f3454gc-8ea-a and 70f3454f1-da9-a only.
chapter 1 introduction user?s manual u18279ej3v0ud 34 ? 100-pin plastic lqfp (14 20) pd70f3453gf-gas-ax pd70f3454gf-gas-ax top view p46/toa40/tia40/intp17 p47/toa41/tia41/intp18 p30/rxda1/scl p31/txda1/sda p32/sib1/rxda2 p33/sob1/txda2 p34/sckb1/intp11 p35/sib2/rxdb p36/sob2/txdb p37/sckb2/intp12 p07/intp07 ev ss0 ev dd0 pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p45/tenc11/tit11/tot11/intp16 p44/tenc10/evtt1/intp15 p43/tecr1/tit10/tot10/intp14 p42/sckb0/intp13/ddi p41/sob0/txda0/dck p40/sib0/rxda0 flmd0 p27/dms ddo drst ev ss2 ev dd2 reset x2 x1 v ss0 regc0 v dd0 p26/tob10/tob1off/intp10/adtrg1/intadt1 p25/tob1b3/trgb1 p24/tob1t3/evtb1 p23/tob1b2/tib10 p22/tob1t2/tib13/tob13 p21/tob1b1/tib12/tob12 p20/tob1t1/tib11/tob11 av ss2 av dd2 p70/ani20 p71/ani21 p72/ani22 pdl8 pdl7 pdl6 pdl5/flmd1 pdl4 pdl3 pdl2 pdl1 pdl0 p06/tenc01/tit01/tot01/intp06 p05/tenc00/evtt0/intp05 p04/tecr0/tit00/tot00/intp04 v ss1 regc1 v dd1 p03/toa31/tia31/intp03 p02/toa30/tia30/toa3off/intp02 p01/toa21/tia21/intp01 p00/toa20/tia20/toa2off/intp00 p17/tob00/intp09 p16/tob0off/intp08/adtrg0/intadt0 p15/tob0b3/trgb0 p14/tob0t3/evtb0 p13/tob0b2/tib00 p12/tob0t2/tib03/tob03 p11/tob0b1/tib02/tob02 p10/tob0t1/tib01/tob01 ev dd1 ev ss1 ani00/ani05 p73/ani23 p74/ani24 p75/ani25 p76/ani26 p77/ani27 ani10/ani15 ani11/ani16 ani12/ani17 ani13/cref1l ani14/cref1f av ss1 av refp1 av dd1 av dd0 av refp0 av ss0 ani04/cref0f ani03/cref0l ani02 ani01
chapter 1 introduction user?s manual u18279ej3v0ud 35 ? 161-pin plastic fbga (10 10) pd70f3454f1-da9-a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark (1/2) pin no. name pin no. name pin no. name a1 ev ss1 b10 pdl1/ad1 d5 ic1 a2 ic1 b11 pdl3/ad3 d6 ic1 a3 ev dd1 b12 pdl6/ad6 d7 ic1 a4 p12/tob0t2/tib03/tob03/a2 b13 ic1 d8 ic1 a5 p15/tob0b3/trgb0/a5 b14 ic1 d9 ic1 a6 p00/toa20/tia20/toa2off/intp00 c1 ev ss1 d10 ic1 a7 v dd1 c2 ev ss1 d11 ic1 a8 regc1 c3 p11/tob0b1/tib02/tob02/a1 d12 pdl11/ad11 a9 v ss1 c4 p14/tob0t3/evtb0/a4 d13 pdl10/ad10 a10 pdl0/ad0 c5 p17/tob00/intp09/a7 d14 pdl9/ad9 a11 pdl2/ad2 c6 p02/toa30/tia30/toa3off/intp02 e1 av ss0 a12 pdl5/ad5/flmd1 c7 p03/toa31/tia31/intp03 e2 av ss0 a13 ic1 c8 p04/tecr0/tit00/tot00/intp04 e3 ani02 a14 ev ss0 c9 p05/tenc00/evtt0/intp05 e4 ev ss1 b1 ev ss1 c10 p06/tenc01/tit01/tot01/intp06 e5 ic0 b2 ev dd1 c11 pdl4/ad4 e11 ic1 b3 p10/tob0t1/tib01/tob01/a0 c12 ic1 e12 pdl14/ad14 b4 p13/tob0b2/tib00/a3 c13 pdl8/ad8 e13 pdl13/ad13 b5 p16/tob0off/intp08/adtrg0/intadt0/a6 c14 pdl7/ad7 e14 pdl12/ad12 b6 p01/toa21/tia21/intp01 d1 ani00/ani05 f1 av dd0 b7 v dd1 d2 ani01 f2 av refp0 b8 regc1 d3 ev ss1 f3 ani03/cref0l b9 v ss1 d4 ic1 f4 ani04/cref0f remarks 1. connect the ic0 pin to ev ss0 , ev ss1 , or ev ss2 . 2. leave the ic1 pin open.
chapter 1 introduction user?s manual u18279ej3v0ud 36 (2/2) pin no. name pin no. name pin no. name f11 ic1 l6 ic1 p5 v dd0 f12 pdl15/ad15 l7 ic1 p6 regc0 f13 ev dd0 l8 ic1 p7 v ss0 f14 ev dd0 l9 ic1 p8 x1 g1 av dd1 l10 ic1 p9 reset g2 av refp1 l11 ic1 p10 ev dd2 g3 ani13/cref1l l12 p46/toa40/tia40/intp17/wr0 p11 ev ss2 g4 ani14/cref1f l13 p45/tenc11/tit11/tot11/intp16/wr1 p12 p40/sib0/rxda0 g11 ic1 l14 p44/tenc10/evtt1/intp15/wait p13 ic1 g12 p07/intp07/clkout m1 av dd2 p14 ev ss2 g13 ev ss0 m2 av dd2 g14 ev ss0 m3 av ss2 h1 av ss1 m4 p24/tob1t3/evtb1 h2 av ss1 m5 p25/tob1b3/trgb1 h3 ani12/ani17 m6 p26/tob10/tob1off/intp10/adtrg1/intadt 1 h4 ic2 m7 ic1 h11 ic1 m8 ic1 h12 p37/sckb2/intp12/astb m9 drst h13 p36/sob2/txdb m10 ddo h14 p35/sib2/rxdb m11 p27/dms j1 ani10/ani15 m12 ic1 j2 ani11/ani16 m13 p43/tecr1/tit10/tot10/intp14 j3 ic2 m14 p42/sckb0/intp13/ddi j4 p77/ani27 n1 ic1 j11 ic1 n2 av ss2 j12 p34/sckb1/intp11/cs0 n3 p21/tob1b1/tib12/tob12 j13 p33/sob1/txda2 n4 p23/tob1b2/tib10 j14 p32/sib1/rxda2/cs1 n5 v dd0 k1 p73/ani23 n6 regc0 k2 p74/ani24 n7 v ss0 k3 p75/ani25 n8 x2 k4 p76/ani26 n9 flmd0 k11 ic1 n10 ev dd2 k12 p31/txda1/sda n11 ev ss2 k13 p30/rxda1/scl n12 p41/sob0/txda0/dck k14 p47/toa41/tia41/intp18/rd n13 ic1 l1 p70/ani20 n14 ic1 l2 p71/ani21 p1 av ss2 l3 p72/ani22 p2 ic1 l4 av ss2 p3 p20/tob1t1/tib11/tob11 l5 ic1 p4 p22/tob1t2/tib13/tob13 remarks 1. leave the ic1 pin open. 2. independently connect the ic2 pin to av ss2 via a resistor.
chapter 1 introduction user?s manual u18279ej3v0ud 37 pin identification (v850e/ig3) a0 to a7: address bus sckb0 to sckb2: serial clock ad0 to ad15: address/data bus scl: serial clock adtrg0, adtrg1: a/d trigger input sda: serial data ani00 to ani05, sib0 to sib2: serial input ani10 to ani17, sob0 to sob2: serial output ani20 to ani27: analog input tecr0, tecr1: timer encoder clear input astb: address strobe tenc00, tenc01, av dd0 to av dd2 : analog power supply tenc10, tenc11: timer encoder input av refp0 , a vrefp1 : analog reference voltage tia20, tia21, av ss0 to av ss2 : analog ground tia30, tia31, clkout: clock output tia40, tia41, cref0f, cref1f, tib00 to tib03, cref0l, cref1l: comparator refer ence voltage tib10 to tib13, cs0, cs1: chip select tit00, tit01, dck: debug clock tit10, tit11: timer trigger input ddi: debug data input toa20, toa21, ddo: debug data output toa30, toa31, dms: debug mode select toa40, toa41, drst: debug reset tob00 to tob03, ev dd0 to ev dd2 : power supply for port tob0b1 to tob0b3, ev ss0 to ev ss2 : ground for port tob0t1 to tob0t3, evtb0, evtb1, tob10 to tob13, evtt0, evtt1: timer event count input tob1b1 to tob1b3, flmd0, flmd1: flash programmi ng mode tob1t1 to tob1t3, ic0 to ic2: internally c onnected tot00, tot01, intadt0, intadt1, tot10, tot11: timer output intp00 to intp18: external interrupt input toa2off, toa3off, p00 to p07: port 0 tob0off, tob1off: timer output off p10 to p17: port 1 trgb0, trgb1: timer trigger input p20 to p27: port 2 txda0 to txda2, p30 to p37: port 3 txdb: transmit data p40 to p47: port 4 v dd0 , v dd1 : power supply p70 to p77: port 7 v ss0 , v ss1 : ground pdl0 to pdl15: port dl wait: wait rd: read strobe wr0, wr1: write strobe regc0, regc1: regulator cont rol x1, x2: clock oscillator pin reset: reset rxda0 to rxda2, rxdb: receive data
chapter 1 introduction user?s manual u18279ej3v0ud 38 1.3.5 function blocks (v850e/ig3) (1) internal block diagram intp00 to intp18 intc tmm 4 channels tab 2 channels uarta 3 channels csib 3 channels ram note 2 cpu 32-bit barrel shifter pc system register general-purpose register (32 bits 32) alu multiplier (32 32 64) ports cg pll regulator 2 channels bcu x1 rg clm reset clkout note 3 x2 v dd0 v ss0 regc0 toa20, toa21, toa30, toa31, toa40, toa41 taa 5 channels tia20, tia21, tia30, tia31, tia40, tia41, toa2off, toa3off tot00, tot01, tot10, tot11 tmt 2 channels tecr0, tecr1, tenc00, tenc01, tenc10,tenc11, evtt0, evtt1, tit00,tit01,tit10,tit11 tib00 to tib03, tib10 to tib13, evtb0, evtb1, trgb0, trgb1, tob0off, tob1off tob00 to tob03, tob10 to tob13, tob0t1 to tob0t3, tob1t1 to tob1t3, tob0b1 to tob0b3, tob1b1 to tob1b3 txda0 to txda2 rxda0 to rxda2 sob0 to sob2 sib0 to sib2 sckb0 to sckb2 instruction queue flmd0 flmd1 ev dd0 ev ss0 ev dd1 ev ss1 ev dd2 ev ss2 wdt uartb 1 channel txdb rxdb i 2 c 1 channel scl sda p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p70 to p77 pdl0 to pdl15 rom note 1 poc/lvi ani00/ani05, ani01 to ani04 ani20 to ani27 adc0 adc2 adtrg0, intadt0 cref0l, cref0f av dd0 av refp0 av ss0 operational amplifier 1 comparator 1 ani10/ani15, ani11/ani16, ani12/ani17, ani13, ani14 adc1 adtrg1, intadt1 cref1l, cref1f av dd2 av ss2 av dd1 av refp1 av ss1 operational amplifier 3 comparator 3 dmac v dd1 v ss1 regc1 memc note 3 a0 to a7 note 3 ad0 to ad15 note 3 cs0 note 3 , cs1 note 3 astb note 3 rd note 3 wr0 note 3 , wr1 note 3 wait note 3 on-chip debug unit dck dms drst ddo ddi notes 1. pd70f3453: 128 kb (flash memory) pd70f3454: 256 kb (flash memory) 2. pd70f3453: 8 kb pd70f3454: 12 kb 3. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 1 introduction user?s manual u18279ej3v0ud 39 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. (b) bus control unit (bcu) the bcu starts the required external bus cycles in accordance with the physical address obtained by the cpu. if the cpu does not request the start of a bus cycl e when an instruction is fetched from the external memory area ( pd70f3454gc-8ea-a and 70f3454f1-da9-a on ly), the bcu generates a prefetch address and prefetches an instruction code. the pref etched instruction code is loaded to the internal instruction queue. the bcu controls a memory controller (memc) and performs external memory access ( pd70f3454gc- 8ea-a and 70f3454f1-da9-a only). (i) memory controller (memc) ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) controls access to sram, ex ternal rom, and external i/o. (ii) dma controller (dmac) this controller controls data transfer between on-ch ip peripheral i/o and internal ram or on-chip peripheral i/o and on-chip peripher al i/o instead of the cpu. the transfer type is two-cycle transfe r, and single transfer, single-step transfer, and block transfer are used in transfer mode. (c) rom this is flash memory that is mapped from address 00000000h. during instruction fetch, rom/flash memory can be accessed from the cpu in 1-clock cycles. the internal rom capacity and area differ as follows depending on the product. part number internal rom capacity internal rom area pd70f3453 128 kb (flash memory) x0000000h to x001ffffh pd70f3454 256 kb (flash memory) x0000000h to x003ffffh (d) ram the internal ram capacity and area differ as follows depending on the product. during instruction fetch or data access, data c an be accessed from the cpu in 1-clock cycles. part number internal ram capacity internal ram area pd70f3453 8 kb xfffc000h to xfffdfffh pd70f3454 12 kb xfffc000h to xfffefffh
chapter 1 introduction user?s manual u18279ej3v0ud 40 (e) interrupt controller (intc) this controller handles hardware interrupt requests (i ntp00 to intp18, intadt0, intadt1) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interru pt servicing control can be performed. (f) clock generator (cg) the clock generator includes two basic operation mo des: pll mode (fixed to multiplication by eight) and clock-through mode. it generates four types of clocks (f xx , f xx /2, f xx /4, f xx /8), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter the v850e/ig3 incorporates four 16-b it interval timer m (tmm) channels, five 16-bit timer/event counter aa (taa) channels, two 16-bit timer/event counter ab (t ab) channels, and two 16-bit timer/event counter t (tmt) channels, and can measure pulse interval width s or frequency, enable an inverter function for motor control, and output a programmable pulse. (h) watchdog timer (wdt) a watchdog timer is equipped to detect program loops, system abnormalities, etc. it generates a non-maskable interrupt request signal (intwd t) or internal reset signal (wdtres) after an overflow occurs. (i) serial interface the v850e/ig3 incorporates eight se rial interface channels: for thre e asynchronous serial interface a (uarta) channels, one asynchronous serial interface b (uartb) channel, three clocked serial interface b (csib) channels, and one i 2 c bus interface (i 2 c) channel. of these, uart0 and csib0, uarta1 and i 2 c, uart2 and csib1, and uartb and csib2 share a pin. for uarta, data is transferred via the txdan and rxdan pins (n = 0 to 2). for uartb, data is transferred via the txdb and rxdb pins. for csib, data is transferred via the sobn, sibn, and sckbn pins (n = 0 to 2). for i 2 c, data is transferred via the scl and sda pins. (j) a/d converter (adc) one channel is provided for each of the high-speed, high-resolution 12-bit a/d converters (adc0, adc1) (total of two channels), which have five analog input pi ns respectively, and one channel is provided for the 10-bit a/d converter (adc2), which has eight analog input pins. both one of the adc0 channels and three of the adc1 channels include an operational amplifier and a comparator so that these a/d conv erters can amplify an analog input voltage and detect overvoltage input. (k) on-chip debug function an on-chip debug function supporting minicube an d minicube2 can be used, so that a simple, inexpensive debug environment can be organized.
chapter 1 introduction user?s manual u18279ej3v0ud 41 (l) ports as shown below, the following ports have general -purpose port functions and control pin functions. port i/o alternate function port 0 8-bit i/o timer/counter i/o, external interrupt input, external bus interface control signal output port 1 8-bit i/o timer/counter i/o, external bus inte rface control signal output, external trigger input of a/d converter 0, external interrupt input port 2 8-bit i/o timer/counter i/o, external trigger input of a/d converter 1, external interrupt input, debug input port 3 8-bit i/o serial interface i/o, external bus interface control signal output, external interrupt input port 4 8-bit i/o serial interface i/o, timer/counter i/o, debug input, external interrupt input, external bus interface control signal i/o port 7 8-bit input a/d converter 2 input port dl 16-bit i/o external bu s interface control signal i/o
user?s manual u18279ej3v0ud 42 chapter 2 pin functions the names and functions of the pins in the v850e/if3 and v850e/ig3 are listed below. these pins can be divided into port pins and non-port pins according to their function. 2.1 list of pin functions there are two power supplies for the i/o buffer of a pin: av dd2 and ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only). the relationship between each power supply and the pins is shown below. table 2-1. i/o buffer power supplies for each pin (a) v850e/if3 power supply corresponding pins av dd2 p70 to p73 ev dd0 , ev dd1 p00, p01, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl9, reset (b) v850e/ig3 power supply corresponding pins av dd2 p70 to p77 ev dd0 , ev dd1 , ev dd2 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl15, reset, dck, ddi, ddo, dms, drst
chapter 2 pin functions user?s manual u18279ej3v0ud 43 (1) port pins (1/3) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin p00 70 91 19 a6 toa20/tia20/toa2off/intp00 p01 69 90 18 b6 toa21/tia21/intp01 p02 note 1 ? 89 17 c6 toa30 note 1 /tia30 note 1 /toa3off note 1 /intp02 note 1 p03 note 1 ? 88 16 c7 toa31 note 1 /tia31 note 1 /intp03 note 1 p04 note 1 ? 84 12 c8 tecr0 note 1 /tit00 note 1 /tot00 note 1 /intp04 note 1 p05 note 1 ? 83 11 c9 tenc00 note 1 /evtt0 note 1 /intp05 note 1 p06 note 1 ? 82 10 c10 tenc01 note 1 /tit01 note 1 /tot01 note 1 /intp06 note 1 p07 note 1 ? 63 91 g12 i/o port 0 v850e/if3: 2-bit i/o port v850e/ig3: 8-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function, and when toa21 and toa31 (v850e/ig3 only) pins (output pins of the alternate function) go into a high-impedance state). intp07 note 1 /clkout note 2 p10 78 99 27 b3 tob0t1/tib01/tob01/a0 note 2 p11 77 98 26 c3 tob0b1/tib02/tob02/a1 note 2 p12 76 97 25 a4 tob0t2/tib03/tob03/a2 note 2 p13 75 96 24 b4 tob0b2/tib00/a3 note 2 p14 74 95 23 c4 tob0t3/evtb0/a4 note 2 p15 73 94 22 a5 tob0b3/trgb0/a5 note 2 p16 72 93 21 b5 tob0off/intp08/adtrg0/intadt0/a6 note 2 p17 71 92 20 c5 i/o port 1 8-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function, and when tob0b1 to tob0b3 and tob0t1 to tob0t3 pins (output pins of the alternate function) go into a high-impedance state). tob00/intp09/a7 note 2 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 44 (2/3) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin p20 23 28 56 p3 tob1t1/tib11/tob11 p21 24 29 57 n3 tob1b1/tib12/tob12 p22 25 30 58 p4 tob1t2/tib13/tob13 p23 26 31 59 n4 tob1b2/tib10 p24 27 32 60 m4 tob1t3/evtb1 p25 28 33 61 m5 tob1b3/trgb1 p26 29 34 62 m6 tob10/tob1off/intp10/adtrg1/intadt1 p27 36 45 73 m11 i/o port 2 8-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull- up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function, and when tob1b1 to tob1b3 and tob1t1 to tob1t3 pins (output pins of the alternate function) go into a high- impedance state). dms note 1 p30 46 55 83 k13 rxda1/scl p31 47 56 84 k12 txda1/sda p32 48 57 85 j14 sib1/rxda2/cs1 note 2 p33 49 58 86 j13 sob1/txda2 p34 50 59 87 j12 sckb1/intp11/cs0 note 2 p35 51 60 88 h14 sib2/rxdb p36 52 61 89 h13 sob2/txdb p37 53 62 90 h12 i/o port 3 8-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull- up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function (including the sckb1 and sckb2 pins in the slave mode)). if the scl or sda pin is selected when the alternate function is to be used, n- ch open-drain output can be specified. sckb2/intp12/astb note 2 p40 38 47 75 p12 sib0/rxda0 p41 39 48 76 n12 sob0/txda0/dck note 1 p42 40 49 77 m14 sckb0/intp13/ddi note 1 p43 41 50 78 m13 tecr1/tit10/tot10/intp14 p44 42 51 79 l14 tenc10/evtt1/intp15/wait note 2 p45 43 52 80 l13 tenc11/tit11/tot11/intp16/wr1 note 2 p46 44 53 81 l12 toa40/tia40/intp17/wr0 note 2 p47 45 54 82 k14 i/o port 4 8-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull- up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function (including the sckb0 pin in the slave mode)). toa41/tia41/intp18/rd note 2 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 45 (3/3) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin p70 20 25 53 l1 ani20 p71 19 24 52 l2 ani21 p72 18 23 51 l3 ani22 p73 17 22 50 k1 ani23 p74 note 1 ? 21 49 k2 ani24 note 1 p75 note 1 ? 20 48 k3 ani25 note 1 p76 note 1 ? 19 47 k4 ani26 note 1 p77 note 1 ? 18 46 j4 input port 7 v850e/if3: 4-bit input port v850e/ig3: 8-bit input port ani27 note 1 pdl0 65 81 9 a10 ad0 note 2 pdl1 64 80 8 b10 ad1 note 2 pdl2 63 79 7 a11 ad2 note 2 pdl3 62 78 6 b11 ad3 note 2 pdl4 61 77 5 c11 ad4 note 2 pdl5 60 76 4 a12 ad5 note 2 /flmd1 pdl6 59 75 3 b12 ad6 note 2 pdl7 58 74 2 c14 ad7 note 2 pdl8 57 73 1 c13 ad8 note 2 pdl9 56 72 100 d14 ad9 note 2 pdl10 note 1 ? 71 99 d13 ad10 note 2 pdl11 note 1 ? 70 98 d12 ad11 note 2 pdl12 note 1 ? 69 97 e14 ad12 note 2 pdl13 note 1 ? 68 96 e13 ad13 note 2 pdl14 note 1 ? 67 95 e12 ad14 note 2 pdl15 note 1 ? 66 94 f12 i/o port dl v850e/if3: 10-bit i/o port v850e/ig3: 16-bit i/o port input data read/output data write is enabled in 1-bit units. an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected only when the pins are in the port mode and input mode). ad15 note 2 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 46 (2) non-port pins (1/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin a0 note 1 ? 99 ? b3 p10/tob0t1/tib01/tob01 a1 note 1 ? 98 ? c3 p11/tob0b1/tib02/tob02 a2 note 1 ? 97 ? a4 p12/tob0t2/tib03/tob03 a3 note 1 ? 96 ? b4 p13/tob0b2/tib00 a4 note 1 ? 95 ? c4 p14/tob0t3/evtb0 a5 note 1 ? 94 ? a5 p15/tob0b3/trgb0 a6 note 1 ? 93 ? b5 p16/tob0off/intp08/adtrg0/intadt0 a7 note 1 ? 92 ? c5 output 8-bit address bus for external memory p17/tob00/intp09 ad0 note 1 ? 81 ? a10 pdl0 ad1 note 1 ? 80 ? b10 pdl1 ad2 note 1 ? 79 ? a11 pdl2 ad3 note 1 ? 78 ? b11 pdl3 ad4 note 1 ? 77 ? c11 pdl4 ad5 note 1 ? 76 ? a12 flmd1/pdl5 ad6 note 1 ? 75 ? b12 pdl6 ad7 note 1 ? 74 ? c14 pdl7 ad8 note 1 ? 73 ? c13 pdl8 ad9 note 1 ? 72 ? d14 pdl9 ad10 note 1 ? 71 ? d13 pdl10 note 2 ad11 note 1 ? 70 ? d12 pdl11 note 2 ad12 note 1 ? 69 ? e14 pdl12 note 2 ad13 note 1 ? 68 ? e13 pdl13 note 2 ad14 note 1 ? 67 ? e12 pdl14 note 2 ad15 note 1 ? 66 ? f12 i/o 16-bit address/data bus for external memory pdl15 note 2 adtrg0 72 93 21 b5 input external trigger input for a/d converter 0 p16/tob0off/intp08/intadt0/a6 note 1 adtrg1 29 34 62 m6 input external trigger input for a/d converter 1 p26/tob10/tob1off/intp10/intadt1 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 47 (2/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin ani00 1 2 30 d1 ani05 ani01 2 3 31 d2 ? ani02 3 4 32 e3 ? ani03 4 5 33 f3 cref0l ani04 5 6 34 f4 cref0f ani05 1 2 30 d1 input analog input for a/d converter 0 ani00 ani10 16 17 45 j1 ani15 ani11 15 16 44 j2 ani16 ani12 14 15 43 h3 ani17 ani13 13 14 42 g3 cref1l ani14 12 13 41 g4 cref1f ani15 16 17 45 j1 ani10 ani16 15 16 44 j2 ani11 ani17 14 15 43 h3 input analog input for a/d converter 1 ani12 ani20 20 25 53 l1 p70 ani21 19 24 52 l2 p71 ani22 18 23 51 l3 p72 ani23 17 22 50 k1 p73 ani24 note 1 ? 21 49 k2 p74 note 1 ani25 note 1 ? 20 48 k3 p75 note 1 ani26 note 1 ? 19 47 k4 p76 note 1 ani27 note 1 ? 18 46 j4 input analog input for a/d converter 2 p77 note 1 astb note 2 ? 62 ? h12 output address strobe output of external data bus p37/sckb2/intp12 av dd0 8 9 37 f1 ? positive power supply for a/d converter 0 ? av dd1 9 10 38 g1 ? positive power supply for a/d converter 1 ? av dd2 21 26 54 m1, m2 ? positive power supply for a/d converter 2 ? av refp0 7 8 36 f2 ? reference voltage input for a/d converter 0 ? av refp1 10 11 39 g2 ? reference voltage input for a/d converter 1 ? notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 48 (3/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin av ss0 6 7 35 e1, e2 ? ground potential for a/d converter 0 ? av ss1 11 12 40 h1, h2 ? ground potential for a/d converter 1 ? av ss2 22 27 55 note 1 ? ground potential for a/d converter 2 ? clkout note 2 ? 63 ? g12 output external bus clock output p07 note 3 intp07 note 3 cref0l 4 5 33 f3 ? low range comparator reference voltage of a/d converter 0 ani03 cref1l 13 14 42 g3 ? low range comparator reference voltage of a/d converter 1 ani13 cref0f 5 6 34 f4 ? full range comparator reference voltage of a/d converter 0 ani04 cref1f 12 13 41 g4 ? full range comparator reference voltage of a/d converter 1 ani14 cs0 note 2 ? 59 ? j12 p34/sckb1/intp11 cs1 note 2 ? 57 ? j14 output chip select output p32/sib1/rxda2 dck note 3 ? 48 76 n12 input debug clock input for on- chip debug emulator p41/sob0/txda0 ddi note 3 ? 49 77 m14 input debug data input for on-chip debug emulator p42/sckb0/intp13 ddo note 3 ? 44 72 m10 output debug data output for on-chip debug emulator ? dms note 3 ? 45 73 m11 input debug mode select for on-chip debug emulator p27 drst note 3 ? 43 71 m9 input debug reset input for on-chip debug emulator ? ev dd0 55 65 93 f13, f14 ? ev dd1 80 100 28 a3, b2 ? ev dd2 note 3 ? 41 69 n10, p10 ? positive power supply for external pin ? ev ss0 54 64 92 note 4 ? ev ss1 79 1 29 note 5 ? ev ss2 note 3 ? 42 70 note 6 ? ground potential for external pin ? evtb0 74 95 23 c4 a4 note 1 /p14/tob0t3 evtb1 27 32 60 m4 input external event count input of tab0, tab1 p24/tob1t3 notes 1. l4, m3, n2, p1 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 3. v850e/ig3 only 4. a14, g13, g14 5. a1, b1, c1, c2, d3, e4 6. n11, p11, p14 remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 49 (4/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin evtt0 note 1 ? 83 11 c9 p05 note 1 /tenc00 note 1 /intp05 note 1 evtt1 42 51 79 l14 input external event count input of tmt0, tmt1/external trigger input p44/tenc10/intp15/wait note 2 flmd0 37 46 74 n9 ? flmd1 60 76 4 a12 input pin for setting flash memory programming mode pdl5/ad5 note 2 ic0 note 3 ? ? ? e5 ? ? ic1 note 3 ? ? ? note 4 ? ? ic2 note 3 ? ? ? note 5 ? internally connected pins ? intadt0 72 93 21 b5 p16/tob0off/intp08/adtrg0/a6 note 2 intadt1 29 34 62 m6 p26/tob10/tob1off/intp10/adtrg1 intp00 70 91 19 a6 p00/toa20/tia20/toa2off intp01 69 90 18 b6 p01/toa21/tia21 intp02 note 1 ? 89 17 c6 p02 note 1 /toa30 note 1 /tia30 note 1 /toa3off note 1 intp03 note 1 ? 88 16 c7 p03 note 1 /toa31 note 1 /tia31 note 1 intp04 note 1 ? 84 12 c8 p04 note 1 /tecr0 note 1 /tit00 note 1 /tot00 note 1 intp05 note 1 ? 83 11 c9 p05 note 1 /tenc00 note 1 /evtt0 note 1 intp06 note 1 ? 82 10 c10 p06 note 1 /tenc01 note 1 /tit01 note 1 /tot01 note 1 intp07 note 1 ? 63 91 g12 p07 note 1 /clkout note 2 intp08 72 93 21 b5 p16/tob0off/adtrg0/intadt0/a6 note 2 intp09 71 92 20 c5 p17/tob00/a7 note 2 intp10 29 34 62 m6 p26/tob10/tob1off/adtrg1/intadt1 intp11 50 59 87 j12 p34/sckb1/cs0 note 2 intp12 53 62 90 h12 p37/sckb2/astb note 2 intp13 40 49 77 m14 p42/sckb0/ddi note 1 intp14 41 50 78 m13 p43/tecr1/tit10/tot10 intp15 42 51 79 l14 p44/tenc10/evtt1/wait note 2 intp16 43 52 80 l13 p45/tenc11/tit11/tot11/wr1 note 2 intp17 44 53 81 l12 p46/toa40/tia40/wr0 note 2 intp18 45 54 82 k14 input external maskable interrupt request input p47/toa41/tia41/rd note 2 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 3. pd70f3454f1-da9-a only 4. a2, a13, b13, b14, c12, d4 to d11, e11, f11, g11, h11, j 11, k11, l5 to l11, m7, m8, m12, n1, n13, n14, p2, p13 5. h4, j3 remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 50 (5/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin rd note 2 ? 54 ? k14 output read strobe output of external data bus p47/toa41/tia41/intp18 regc0 31 36 64 n6, p6 ? regc1 67 86 14 a8, b8 ? regulator output stabilization capacitance connection ? reset 35 40 68 p9 input system reset input ? rxda0 38 47 75 p12 p40/sib0 rxda1 46 55 83 k13 p30/scl rxda2 48 57 85 j14 input serial receive data input of uarta0 to uarta2 p32/sib1/cs1 note 1 rxdb 51 60 88 h14 input serial receive data input of uartb0 p35/sib2 sckb0 40 49 77 m14 p42/intp13/ddi note 2 sckb1 50 59 87 j12 p34/intp11/cs0 note 1 sckb2 53 62 90 h12 i/o serial clock i/o of csib0 to csib2 p37/intp12/astb note 1 scl 46 55 83 k13 i/o serial clock i/o p30/rxda1 sda 47 56 84 k12 i/o serial transmit/recei ve data i/o p31/txda1 sib0 38 47 75 p12 p40/rxda0 sib1 48 57 85 j14 p32/rxda2/cs1 note 1 sib2 51 60 88 h14 input serial receive data input of csib0 to csib2 p35/rxdb sob0 39 48 76 n12 p41/txda0/dck note 2 sob1 49 58 86 j13 p33/txda2 sob2 52 61 89 h13 output serial transmit data output of csib0 to csib2 p36/txdb tecr0 note 2 ? 84 12 c8 p04 note 2 /tit00 note 2 /tot00 note 2 /intp04 note 2 tecr1 41 50 78 m13 input encoder clear input of tmt0, tmt1 p43/tit10/tot10/intp14 tenc00 note 2 ? 83 11 c9 p05 note 2 /evtt0 note 2 /intp05 note 2 tenc01 note 2 ? 82 10 c10 p06 note 2 /tit01 note 2 /tot01 note 2 /intp06 note 2 tenc10 42 51 79 l14 p44/evtt1/intp15/wait note 1 tenc11 43 52 80 l13 input encoder input of tmt0, tmt1 p45/tit11/tot11/intp16/wr1 note 1 tia20 70 91 19 a6 input external event count input/external trigger input/capture trigger input of taa2 p00/toa20/toa2off/intp00 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 51 (6/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin tia21 69 90 18 b6 input capture trigger input of taa2 p01/toa21/intp01 tia30 note 2 ? 89 17 c6 external event count input/external trigger input/capture trigger input of taa3 p02 note 2 /toa30 note 2 /toa3off note 2 /intp02 note 2 tia31 note 2 ? 88 16 c7 input capture trigger input of taa3 p03 note 2 /toa31 note 2 /intp03 note 2 tia40 44 53 81 l12 input external event count input/external trigger input/capture trigger input of taa4 p46/toa40/intp17/wr0 note 1 tia41 45 54 82 k14 input capture trigger input of taa4 p47/toa41/intp18/rd note 1 tib00 75 96 24 b4 p13/tob0b2/a3 note 1 tib01 78 99 27 b3 p10/tob0t1/tob01/a0 note 1 tib02 77 98 26 c3 p11/tob0b1/tob02/a1 note 1 tib03 76 97 25 a4 p12/tob0t2/tob03/a2 note 1 tib10 26 31 59 n4 p23/tob1b2 tib11 23 28 56 p3 p20/tob1t1/tob11 tib12 24 29 57 n3 p21/tob1b1/tob12 tib13 25 30 58 p4 input capture trigger input of tab0, tab1 p22/tob1t2/tob13 tit00 note 2 ? 84 12 c8 p04 note 2 /tecr0 note 2 /tot00 note 2 /intp04 note 2 tit01 note 2 ? 82 10 c10 input capture trigger input of tit0 p06 note 2 /tenc01 note 2 /tot01 note 2 /intp06 note 2 tit10 41 50 78 m13 p43/tecr1/tot10/intp14 tit11 43 52 80 l13 input capture trigger input of tit1 p45/tenc11/tot11/intp16/wr1 note 1 toa20 70 91 19 a6 p00/tia20/toa2off/intp00 toa21 69 90 18 b6 output timer output of taa2 p01/tia21/intp01 toa2off 70 91 19 a6 input high-impedance output control signal input p00/toa20/tia20/intp00 toa30 note 2 ? 89 17 c6 p02 note 2 /tia30 note 2 /toa3off note 2 /intp02 note 2 toa31 note 2 ? 88 16 c7 output timer output of taa3 p03 note 2 /tia31 note 2 /intp03 note 2 toa3off note 2 ? 89 17 c6 input high-impedance output control signal input p02 note 2 /toa30 note 2 /tia30 note 2 /intp02 note 2 toa40 44 53 81 l12 p46/tia40/intp17/wr0 note 1 toa41 45 54 82 k14 output timer output of taa4 p47/tia41/intp18/rd note 1 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 52 (7/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin tob00 71 92 20 c5 p17/intp09/a7 note 1 tob01 78 99 27 b3 p10/tob0t1/tib01/a0 note 1 tob02 77 98 26 c3 p11/tob0b1/tib02/a1 note 1 tob03 76 97 25 a4 output timer output of tab0 p12/tob0t2/tib03/a2 note 1 tob0b1 77 98 26 c3 p11/tib02/tob02/a1 note 1 tob0b2 75 96 24 b4 p13/tib00/a3 note 1 tob0b3 73 94 22 a5 output pulse signal output for 6-phase pwm low arm of tab0 p15/trgb0/a5 note 1 tob0off 72 93 21 b5 input 6-phase pwm high-impedance output control signal input of tab0 p16/intp08/adtrg0/intadt0/a6 note 1 tob0t1 78 99 27 b3 p10/tib01/tob01/a0 note 1 tob0t2 76 97 25 a4 p12/tib03/tob03/a2 note 1 tob0t3 74 95 23 c4 output pulse signal output for 6-phase pwm high arm of tab0 p14/evtb0/a4 note 1 tob10 29 34 62 m6 p26/tob1off/intp10/adtrg1/intadt1 tob11 23 28 56 p3 p20/tob1t1/tib11 tob12 24 29 57 n3 p21/tob1b1/tib12 tob13 25 30 58 p4 output timer output of tab1 p22/tob1t2/tib13 tob1b1 24 29 57 n3 p21/tib12/tob12 tob1b2 26 31 59 n4 p23/tib10 tob1b3 28 33 61 m5 output pulse signal output for 6-phase pwm low arm of tab1 p25/trgb1 tob1off 29 34 62 m6 input 6-phase pwm high-impedance output control signal input of tab1 p26/tob10/intp10/adtrg1/intadt1 tob1t1 23 28 56 p3 p20/tib11/tob11 tob1t2 25 30 58 p4 p22/tib13/tob13 tob1t3 27 32 60 m4 output pulse signal output for 6-phase pwm high arm of tab1 p24/evtb1 tot00 note 2 ? 84 12 c8 p04 note 2 /tecr0 note 2 /tit00 note 2 /intp04 note 2 tot01 note 2 ? 82 10 c10 p06 note 2 /tenc01 note 2 /tit01 note 2 /intp06 note 2 tot10 41 50 78 m13 p43/tecr1/tit10/intp14 tot11 43 52 80 l13 output timer output of tmt0, tmt1 p45/tenc11/tit11/intp16/wr1 note 1 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 53 (8/8) pin no. if3 ig3 pin name gc gc gf f1 i/o function alternate-function pin trgb0 73 94 22 a5 p15/tob0b3/a5 note 1 trgb1 28 33 61 m5 input external trigger input of tab0, tab1 p25/tob1b3 txda0 39 48 76 n12 p41/sob0/dck note 2 txda1 47 56 84 k12 p31/sda txda2 49 58 86 j13 output serial transmit data output of uarta0 to uarta2 p33/sob1 txdb 52 61 89 h13 output serial transmit data output of uartb0 p36/sob2 v dd0 30 35 63 n5, p5 ? v dd1 68 87 15 a7, b7 ? positive power supply for internal unit ? v ss0 32 37 65 n7, p7 ? v ss1 66 85 13 a9, b9 ? ground potential for internal unit ? wait note ? 51 ? l14 input external wait request input p44/tenc10/evtt1/intp15 wr0 note ? 53 ? l12 p46/toa40/tia40/intp17 wr1 note ? 52 ? l13 output write strobe output of external data bus p45/tenc11/tit11/tot11/intp16 x1 33 38 66 p8 input ? x2 34 39 67 n8 ? resonator connection pin for system clock ? note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 54 2.2 pin status the operation statuses of pi ns in the various operation modes are described below. table 2-2. pin operation status in operation modes operating status pin reset halt mode/ during dma transfer idle mode/ stop mode idle state ad0 to ad15 note 1 (pdl0 to pdl15) hi-z note 2 operating hi-z held a0 to a7 note 1 (p10 to p17) hi-z note 2 operating hi-z held cs0 note 1 , cs1 note 1 (p34, p32) hi-z note 2 operating h held wr0 note 1 , wr1 note 1 (p46, p45) hi-z note 2 operating h h rd note 1 (p47) hi-z note 2 operating h h astb note 1 (p37) hi-z note 2 operating h h wait note 1 (p44) hi-z note 2 operating ? ? clkout note 1 (p07) hi-z note 2 operating held operating notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. since the bus control pin is also us ed as a port pin, it is initialized to the input mode (port mode) after reset. remark hi-z: high impedance held: the state during t he immediately preceding external bus cycle is held. h: high-level output ?: input without samp ling (not acknowledged)
chapter 2 pin functions user?s manual u18279ej3v0ud 55 2.3 pin i/o circuits and recomme nded connection of unused pins it is recommended that 1 to 10 k resistors be used when connecting to av ss2 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only) or ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only) via resistors. (1/4) pin no. if3 ig3 pin alternate-function pin name gc gc gf f1 i/o circuit type recommended connection p00 toa20/tia20/toa2off/intp00 70 91 19 a6 p01 toa21/tia21/intp01 69 90 18 b6 p02 note 1 toa30 note 1 /tia30 note 1 /toa3off note 1 / intp02 note 1 ? 89 17 c6 p03 note 1 toa31 note 1 /tia31 note 1 /intp03 note 1 ? 88 16 c7 p04 note 1 tecr0 note 1 /tit00 note 1 /tot00 note 1 /intp04 note 1 ? 84 12 c8 p05 note 1 tenc00 note 1 /evtt0 note 1 /intp05 note 1 ? 83 11 c9 p06 note 1 tenc01 note 1 /tit01 note 1 /tot01 note 1 /intp06 note 1 ? 82 10 c10 p07 note 1 intp07 note 1 /clkout note 2 ? 63 91 g12 p10 tob0t1/tib01/tob01/a0 note 2 78 99 27 b3 p11 tob0b1/tib02/tob02/a1 note 2 77 98 26 c3 p12 tob0t2/tib03/tob03/a2 note 2 76 97 25 a4 p13 tob0b2/tib00/a3 note 2 75 96 24 b4 p14 tob0t3/evtb0/a4 note 2 74 95 23 c4 p15 tob0b3/trgb0/a5 note 2 73 94 22 a5 p16 tob0off/intp08/adtrg0/intadt0/a6 note 2 72 93 21 b5 p17 tob00/intp09/a7 note 2 71 92 20 c5 p20 tob1t1/tib11/tob11 23 28 56 p3 p21 tob1b1/tib12/tob12 24 29 57 n3 p22 tob1t2/tib13/tob13 25 30 58 p4 p23 tob1b2/tib10 26 31 59 n4 p24 tob1t3/evtb1 27 32 60 m4 p25 tob1b3/trgb1 28 33 61 m5 p26 tob10/tob1off/intp10/adtrg1/intadt1 29 34 62 m6 p27 dms note 1 36 45 73 m11 5-ah input: independently connect to ev dd0 , ev dd1 , ev dd2 note 1 or ev ss0 , ev ss1 , ev ss2 note 1 via a resistor. output: leave open. notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 56 (2/4) pin no. if3 ig3 pin alternate-function pin name gc gc gf f1 i/o circuit type recommended connection p30 rxda1/scl 46 55 83 k13 p31 txda1/sda 47 56 84 k12 p32 sib1/rxda2/cs1 note 1 48 57 85 j14 5-ah p33 sob1/txda2 49 58 86 j13 5-ag p34 sckb1/intp11/cs0 note 1 50 59 87 j12 p35 sib2/rxdb 51 60 88 h14 5-ah p36 sob2/txdb 52 61 89 h13 5-ag p37 sckb2/intp12/astb note 1 53 62 90 h12 p40 sib0/rxda0 38 47 75 p12 5-ah p41 sob0/txda0/dck note 2 39 48 76 n12 5-ag p42 sckb0/intp13/ddi note 2 40 49 77 m14 p43 tecr1/tit10/tot10/intp14 41 50 78 m13 p44 tenc10/evtt1/intp15/wait note 1 42 51 79 l14 p45 tenc11/tit11/tot11/intp16/wr1 note 1 43 52 80 l13 p46 toa40/tia40/intp17/wr0 note 1 44 53 81 l12 p47 toa41/tia41/intp18/rd note 1 45 54 82 k14 5-ah input: independently connect to ev dd0 , ev dd1 , ev dd2 note 2 or ev ss0 , ev ss1 , ev ss2 note 2 via a resistor. output: leave open. p70 ani20 20 25 53 l1 p71 ani21 19 24 52 l2 p72 ani22 18 23 51 l3 p73 ani23 17 22 50 k1 p74 note 2 ani24 note 2 ? 21 49 k2 p75 note 2 ani25 note 2 ? 20 48 k3 p76 note 2 ani26 note 2 ? 19 47 k4 p77 note 2 ani27 note 2 ? 18 46 j4 11-g independently connect to av ss2 via a resistor. pdl0 ad0 note 1 65 81 9 a10 pdl1 ad1 note 1 64 80 8 b10 pdl2 ad2 note 1 63 79 7 a11 pdl3 ad3 note 1 62 78 6 b11 5-ag input: independently connect to ev dd0 , ev dd1 , ev dd2 note 2 or ev ss0 , ev ss1 , ev ss2 note 2 via a resistor. output: leave open. notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 57 (3/4) pin no. if3 ig3 pin alternate-function pin name gc gc gf f1 i/o circuit type recommended connection pdl4 ad4 note 1 61 77 5 c11 pdl5 ad5 note 1 /flmd1 60 76 4 a12 pdl6 ad6 note 1 59 75 3 b12 pdl7 ad7 note 1 58 74 2 c14 pdl8 ad8 note 1 57 73 1 c13 pdl9 ad9 note 1 56 72 100 d14 pdl10 note 2 ad10 note 1 ? 71 99 d13 pdl11 note 2 ad11 note 1 ? 70 98 d12 pdl12 note 2 ad12 note 1 ? 69 97 e14 pdl13 note 2 ad13 note 1 ? 68 96 e13 pdl14 note 2 ad14 note 1 ? 67 95 e12 pdl15 note 2 ad15 note 1 ? 66 94 f12 5-ag input: independently connect to ev dd0 , ev dd1 , ev dd2 note 2 or ev ss0 , ev ss1 , ev ss2 note 2 via a resistor. output: leave open. ani00 ani05 1 2 30 d1 ani01 ? 2 3 31 d2 ani02 ? 3 4 32 e3 ani03 cref0l 4 5 33 f3 ani04 cref0f 5 6 34 f4 ani10 ani15 16 17 45 j1 ani11 ani16 15 16 44 j2 ani12 ani17 14 15 43 h3 ani13 cref1l 13 14 42 g3 ani14 cref1f 12 13 41 g4 7-c connect to av ss0 or av ss1 . notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 58 (4/4) pin no. if3 ig3 pin alternate-function pin name gc gc gf f1 i/o circuit type recommended connection ddo note 1 ? ? 44 72 m10 3-c leave open (output when drst is high-level). drst note 1 ? ? 43 71 m9 2-m leave open (on-chip pull-down resistor). flmd0 ? 37 46 74 n9 2 ? ic0 note 2 ? ? ? ? e5 connect to ev ss0 , ev ss1 , or ev ss2 . ic1 note 2 ? ? ? ? note 3 leave open ic2 note 2 ? ? ? ? note 4 ? independently connect to av ss2 via a resistor. reset ? 35 40 68 p9 2 pull this pin up when the power- on-clear circuit (poc) is used. notes 1. v850e/ig3 only 2. pd70f3454f1-da9-a only 3. a2, a13, b13, b14, c12, d4 to d 11, e11, f11, g11, h11, j11, k11, l5 to l11, m7, m8, m12, n1, n13, n14, p2, p13 4. h4, j3 remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 2 pin functions user?s manual u18279ej3v0ud 59 2.4 pin i/o circuits type 2 type 2-m type 3-c schmitt-triggered input with hysteresis characteristics type 5-ag type 5-ah in in ev dd0 , ev dd1 , ev dd2 note ev dd0 , ev dd1 , ev dd2 note ev dd0 , ev dd1 , ev dd2 note ev dd0 , ev dd1 , ev dd2 note ev dd0 , ev dd1 , ev dd2 note p-ch n-ch data out ev ss0 , ev ss1 , ev ss2 note ev ss0 , ev ss1 , ev ss2 note ev ss0 , ev ss1 , ev ss2 note ev ss0 , ev ss1 , ev ss2 note type 7-c p-ch n-ch p-ch n-ch in av ss0 , av ss1 av ss0 , av ss1 v ref (threshold voltage) comparator + cref0l, cref0f, cref1l, cref1f (pin level) comparator + - - op type 11-g data output disable p-ch in/out n-ch input enable p-ch pull-up enable pull-up enable data output disable input enable p-ch p-ch in/out n -ch data output disable av dd2 p-ch in/out n-ch p-ch n-ch v ref (threshold voltage) comparator input enable + _ av ss2 av ss2 note v850e/ig3 only
user?s manual u18279ej3v0ud 60 chapter 3 cpu function the cpu of the v850e/if3 and v850e/ig3 is based on risc architectu re and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 features { minimum instruction execution time: 15.6 ns (@ 64 mhz internal operation) { thirty-two 32-bit general-purpose registers { internal 32-bit architecture { five-stage pipeline control { multiply/divide instructions { saturated operation instructions { one-clock 32-bit shift instruction { load/store instruction with long/short instruction format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
chapter 3 cpu function user?s manual u18279ej3v0ud 61 3.2 cpu register set the registers of the v850e/if3 and v850 e/ig3 can be classified into two ca tegories: a general-purpose program register set and a dedicated system register set. all the registers have a 32-bit width. for details, refer to v850e1 architecture user?s manual . figure 3-1. cpu register set (1) program register set (2) system register set r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) 31 0 pc (program counter) 31 0 eipc (status saving register during interrupt) eipsw (status saving register during interrupt) fepc (status saving register during nmi) fepsw (status saving register during nmi) ecr (interrupt source register) psw (program status word) ctpc (status saving register during callt execution) ctpsw (status saving register during callt execution) dbpc (status saving register during exception/debug trap) dbpsw (status saving register during exception/debug trap) ctbp (callt base pointer) 31 0
chapter 3 cpu function user?s manual u18279ej3v0ud 62 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instru ctions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the assembler a nd c compiler. therefore, before using these registers, their contents must be saved so that th ey are not lost. the contents must be restored to the registers after the registers have been used. r2 may be used by the real-tim e os. if the real-time os does not use r2, it can be used as a variable register. table 3-1. general-purpose registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for genera ting 32-bit immediate data r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 after reset: 00000000h
chapter 3 cpu function user?s manual u18279ej3v0ud 63 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification system register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) 3 nmi status saving register (fepsw) 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to enable multip le interrupts, it is necessary to save this register by program. 2. these registers can be read/written only in the period between dbtrap instruction or illegal opcode execution and dbret instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 by the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, and ctpc, use an even value (bit 0 = 0). remark : access allowed : access prohibited
chapter 3 cpu function user?s manual u18279ej3v0ud 64 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), the contents are saved to the nm i status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed wh en a software exception or maskable interrupt occurs is saved to eipc, except for some instructions (see 20.9 periods in which cpu does not acknowledge interrupts ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving r egisters, the contents of thes e registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function user?s manual u18279ej3v0ud 65 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), t he contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi status saving registers, the contents of these regi sters must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. when the reti instruction has been ex ecuted, the values of fepc and fepsw are restored to the pc and psw, respectively. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the interrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code coded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
chapter 3 cpu function user?s manual u18279ej3v0ud 66 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program st atus (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruction, the new contents become valid immediately following completion of ldsr instruction ex ecution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servici ng is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled (ei) 1: interrupt disabled (di) 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do no t become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page.
chapter 3 cpu function user?s manual u18279ej3v0ud 67 (2/2) note during saturated operation, the saturated operat ion results are determined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when the ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function user?s manual u18279ej3v0ud 68 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, th e contents of the program co unter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. these registers can be read or written only in t he period between dbtrap instruction or illegal opcode execution and dbret instruction execution. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. when the dbret instruction has been executed, the values of dbpc and dbpsw are restored to the pc and psw, respectively. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify t able addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu function user?s manual u18279ej3v0ud 69 3.3 operating modes 3.3.1 operating modes the v850e/if3 and v850e/ig3 have the following operating modes. mode specification is carried out using the flmd0 and flmd1 pins. (1) normal operation mode in this mode, execution branches to the reset entry ad dress in the internal rom and instruction processing is started when system reset is released. (2) flash memory programming mode if this mode is specified, a program can be written to the internal flash memory by the flash memory programmer. 3.3.2 operating mode specification the operating mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. in the normal operating mode, input a low level to the flmd0 pin after reset. when the flash memory programmer is connected, a high level is input to the flmd0 pin by the flash memory programmer in the flash memory programming mode; however, in the self-programming mode, input a high level via an external circuit. other than in the self-programming mode, fix the specificat ions of these pins in the application system, and do not change then during operation. flmd1 flmd0 operating mode remarks l normal operation mode internal rom area is allocated from address 000000h. l h flash memory programming mode ? h h setting prohibited remark l: low-level input h: high-level input
chapter 3 cpu function user?s manual u18279ej3v0ud 70 3.4 address space 3.4.1 cpu address space the cpu of the v850e/if3 and v850e/ig3 has 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). also , in instruction address addressing, a maximum of 64 mb of linear address space (program space) is supported. figure 3-2 shows the cpu address space. figure 3-2. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space
chapter 3 cpu function user?s manual u18279ej3v0ud 71 3.4.2 image a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. in actuality, the same 256 mb physical address space is accessed regardless of the va lues of bits 31 to 28 of the cpu address. figure 3-3 shows the image of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-3. images on address space ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram on-chip peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space
chapter 3 cpu function user?s manual u18279ej3v0ud 72 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a re sult of a branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the upper-limit address of the program space, address 03ffffffh, and the lower-limit address 00000000h become contiguous addresses. wraparound refe rs to a situation like this whereby the lower-limit address and upper-limit address become contiguous. caution the 4 kb area of 03 fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. this area is access-prohibited. the refore, do not execute any branch address calculation in which the result will r eside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the upper-limit address of the program space, address ffff ffffh, and the lower-limit address 00000000h are contiguous addresses, and the data sp ace is wrapped around at the boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
chapter 3 cpu function user?s manual u18279ej3v0ud 73 3.4.4 memory map the v850e/if3 and v850e/ig3 reserve areas as shown in figure 3-4. figure 3-4. memory map on-chip peripheral i/o area pd70f3451 (v850e/if3) pd70f3453 (v850e/ig3) internal ram area access prohibited access prohibited internal rom area 256 mb 256 kb 1 mb 128 kb 4 kb 12 kb 3 mb 8 kb on-chip peripheral i/o area pd70f3452 (v850e/if3) pd70f3454 (v850e/ig3) internal ram area internal rom area access prohibited access prohibited access prohibited external memory area note external memory area note x f f f f f f f h x f f f f 0 0 0 h x f f f e f f f h x f f f e 0 0 0 h x f f f d f f f h x f f f c 0 0 0 h x f f f b f f f h x 0 1 0 0 0 0 0 h x 0 0 4 0 0 0 0 h x 0 0 0 0 0 0 0 h x 0 0 f f f f f h x 0 4 0 0 0 0 0 h x 0 3 f f f f f h x 0 0 1 f f f f h x 0 0 2 0 0 0 0 h x 0 0 3 f f f f h note pd70f3454gc-8ea-a and 70f3454f1-da 9-a: external memory area others: access prohibited area
chapter 3 cpu function user?s manual u18279ej3v0ud 74 3.4.5 area (1) internal rom area 1 mb of internal rom area, addre sses 00000h to fff ffh, is reserved. (a) pd70f3451 (v850e/if3), pd70f3453 (v850e/ig3) 128 kb are provided at addre sses 000000h to 01ffffh as physical internal rom. figure 3-5. internal rom area (128 kb) 0 0 f f f f f h 0 0 2 0 0 0 0 h 0 0 1 f f f f h 0 0 0 0 0 0 0 h access prohibited area internal rom (b) pd70f3452 (v850e/if3), pd70f3454 (v850e/ig3) 256 kb are provided at addre sses 000000h to 03ffffh as physical internal rom. figure 3-6. internal rom area (256 kb) 0 0 f f f f f h 0 0 4 0 0 0 0 h 0 0 3 f f f f h 0 0 0 0 0 0 0 h access prohibited area internal rom
chapter 3 cpu function user?s manual u18279ej3v0ud 75 (2) internal ram area the 12 kb area of addresses fffc000h to fffefffh is reserved for the internal ram area. (a) pd70f3451 (v850e/if3), pd70f3453 (v850e/ig3) the 8 kb area of addresses fffc000h to fffdfffh is provided as physical internal ram. caution the following are as are access-prohibited. addresses fffe000h to fffefffh figure 3-7. internal ram area (8 kb) access prohibited internal ram area (8 kb) f f f e f f f h f f f e 0 0 0 h f f f d f f f h f f f c 0 0 0 h (b) pd70f3452 (v850e/if3), pd70f3454 (v850e/ig3) the 12 kb area of addresses fffc000h to fffefffh is provided as physical internal ram. figure 3-8. internal ram area (12 kb) internal ram area (12 kb) f f f e f f f h f f f c 0 0 0 h
chapter 3 cpu function user?s manual u18279ej3v0ud 76 (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, is provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen at addresses 3fff000h to 3ffffffh note . note addresses 3fff000h to 3ffffffh are access-prohib ited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. figure 3-9. on-chip peripheral i/o area f f f f f f f h f f f f 0 0 0 h on-chip peripheral i/o area (4 kb) on-chip peripheral i/o registers associ ated with the operating mode specification and th e state monitoring for the on-chip peripheral i/o are all memo ry-mapped to the on-chip peripheral i/o area. program fetches cannot be executed from this area. cautions 1. in the v850e/if3 and v850e/ig3, if a register is word accessed, halfword access is performed twice in the order of lower addr ess, then higher address of the word area, disregarding the lower 2 bits of the address. 2. for registers in which byte access is possi ble, if halfword access is executed, the higher 8 bits become undefined during the read opera tion, and the lower 8 bits of data are written to the register during the write operation. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer. (4) external memory area ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) 3 mb (0100000h to 03fffffh) are available for the ex ternal memory area. for details, see chapter 18 bus control function .
chapter 3 cpu function user?s manual u18279ej3v0ud 77 3.4.6 recommended use of address space the architecture of the v850e /if3 and v850e/ig3 requires that a register that serves as a pointer be secured for address generation in operand data accessing of data space. operand data access from in struction can be directly executed at the address in this pointer register area 32 kb. however, because the general-purpose registers that can be used as a pointer register are limited, by minimizing the deterioration of addres s calculation performance when changing the pointer value, the number of usable general-pur pose registers for handling variables is maximized, and the program size can be saved. (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. therefore, a contiguous 64 mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space with the v850e/if3 and v850e/ig3, a 256 mb physical addr ess space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bi t address is assigned as an address sign-extended to 32 bits. (a) application examples using wraparound when r = r0 (zero register) is s pecified by the ld/st disp16 [r] in struction, an addressing range of 00000000h 32 kb can be referenced by the sign-extended disp16. the zero register (r0) is a register set to 0 by the hardware, and eliminates the nee d for additional registers for the pointer. example pd70f3454 (v850e/ig3) internal rom area on-chip peripheral i/o area internal ram area 32 kb 12 kb 4 kb 0 0 0 3 f f f f h 0 0 0 0 7 f f f h (r = ) 0 0 0 0 0 0 0 0 h f f f f f 0 0 0 h f f f f e f f f h f f f f c 0 0 0 h f f f f b f f f h f f f f 8 0 0 0 h
chapter 3 cpu function user?s manual u18279ej3v0ud 78 figure 3-10. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory area note 3 internal ram on-chip peripheral i/o note 1 access prohibited note 2 access prohibited note 2 access prohibited note 2 program space 64 mb internal rom external memory area note 3 internal rom external memory area note 3 f f f f f f f f h f f f f f 0 0 0 h f f f f e f f f h f f f f c 0 0 0 h f f f e b f f f h x f f f f f f f h x f f f f 0 0 0 h x f f f e f f f h x 0 1 0 0 0 0 0 h x 0 0 f f f f f h x 0 0 4 0 0 0 0 h x 0 0 0 0 0 0 0 h x 0 0 3 f f f f h x f f f c 0 0 0 h x f f f b f f f h x 0 4 0 0 0 0 0 h x 0 3 f f f f f h 0 4 0 0 0 0 0 0 h 0 3 f f f f f f h 0 3 f f f 0 0 0 h 0 3 f f e f f f h 0 3 f f c 0 0 0 h 0 3 f f b f f f h 0 0 1 0 0 0 0 0 h 0 0 0 f f f f f h 0 0 4 0 0 0 0 0 h 0 0 3 f f f f f h 0 0 0 4 0 0 0 0 h 0 0 0 0 0 0 0 0 h 0 0 0 3 f f f f h notes 1. this area is access-prohibited. to access t he on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 2. the operation is not guaranteed if an a ccess-prohibited area is accessed. 3. pd70f3454gc-8ea-a and 70f3454f1- da9-a: external memory area others: access prohibited area note 2 remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map for the pd70f3454 (v850e/ig3).
chapter 3 cpu function user?s manual u18279ej3v0ud 79 3.4.7 on-chip peripheral i/o registers (1/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff004h port dl register pdl undefined fffff004h port dll register pdll undefined fffff005h port dlh register pdlh undefined fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff066h bus size configur ation register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 80 (2/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff10ah interrupt mask register 5 imr5 ffffh fffff10ah interrupt mask register 5l imr5l ffh fffff10bh interrupt mask register 5h imr5h ffh fffff110h interrupt control register lvilic 47h fffff112h interrupt control register lvihic 47h fffff114h interrupt control register pic00 47h fffff116h interrupt control register pic01 47h fffff118h interrupt control register pic02 note 47h fffff11ah interrupt control register pic03 note 47h fffff11ch interrupt control register pic04 note 47h fffff11eh interrupt control register pic05 note 47h fffff120h interrupt control register pic06 note 47h fffff122h interrupt control register pic07 note 47h fffff124h interrupt control register pic08 47h fffff126h interrupt control register pic09 47h fffff128h interrupt control register pic10 47h fffff12ah interrupt control register pic11 47h fffff12ch interrupt control register pic12 47h fffff12eh interrupt control register pic13 47h fffff130h interrupt control register pic14 47h fffff132h interrupt control register pic15 47h fffff134h interrupt control register pic16 47h fffff136h interrupt control register pic17 47h fffff138h interrupt control register pic18 47h fffff13ah interrupt control register cmpic0l r/w 47h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 81 (3/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff13ch interrupt control register cmpic0f 47h fffff13eh interrupt control register cmpic1l 47h fffff140h interrupt control register cmpic1f 47h fffff142h interrupt control register tb0ovic 47h fffff144h interrupt control register tb0ccic0 47h fffff146h interrupt control register tb0ccic1 47h fffff148h interrupt control register tb0ccic2 47h fffff14ah interrupt control register tb0ccic3 47h fffff14ch interrupt control register tb1ovic 47h fffff14eh interrupt control register tb1ccic0 47h fffff150h interrupt control register tb1ccic1 47h fffff152h interrupt control register tb1ccic2 47h fffff154h interrupt control register tb1ccic3 47h fffff156h interrupt control register tt0ovic 47h fffff158h interrupt control register tt0ccic0 47h fffff15ah interrupt control register tt0ccic1 47h fffff15ch interrupt control register tt0iecic note 47h fffff15eh interrupt control register tt1ovic 47h fffff160h interrupt control register tt1ccic0 47h fffff162h interrupt control register tt1ccic1 47h fffff164h interrupt control register tt1iecic 47h fffff166h interrupt control register ta0ovic 47h fffff168h interrupt control register ta0ccic0 47h fffff16ah interrupt control register ta0ccic1 47h fffff16ch interrupt control register ta1ovic 47h fffff16eh interrupt control register ta1ccic0 47h fffff170h interrupt control register ta1ccic1 47h fffff172h interrupt control register ta2ovic 47h fffff174h interrupt control register ta2ccic0 47h fffff176h interrupt control register ta2ccic1 47h fffff178h interrupt control register ta3ovic 47h fffff17ah interrupt control register ta3ccic0 47h fffff17ch interrupt control register ta3ccic1 47h fffff17eh interrupt control register ta4ovic 47h fffff180h interrupt control register ta4ccic0 47h fffff182h interrupt control register ta4ccic1 47h fffff184h interrupt control register dmaic0 47h fffff186h interrupt control register dmaic1 47h fffff188h interrupt control register dmaic2 47h fffff18ah interrupt control register dmaic3 r/w 47h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 82 (4/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff18ch interrupt control register ureic 47h fffff18eh interrupt control register uric 47h fffff190h interrupt control register utic 47h fffff192h interrupt control register uific 47h fffff194h interrupt control register utoic 47h fffff196h interrupt control register ua0reic 47h fffff198h interrupt control register ua0ric 47h fffff19ah interrupt control register ua0tic 47h fffff19ch interrupt control register cb0reic 47h fffff19eh interrupt control register cb0ric 47h fffff1a0h interrupt control register cb0tic 47h fffff1a2h interrupt control register ua1reic 47h fffff1a4h interrupt control register ua1ric 47h fffff1a6h interrupt control register ua1tic 47h fffff1a8h interrupt control register cb1reic 47h fffff1aah interrupt control register cb1ric 47h fffff1ach interrupt control register cb1tic 47h fffff1aeh interrupt control register ua2reic 47h fffff1b0h interrupt control register ua2ric 47h fffff1b2h interrupt control register ua2tic 47h fffff1b4h interrupt control register cb2reic 47h fffff1b6h interrupt control register cb2ric 47h fffff1b8h interrupt control register cb2tic 47h fffff1bah interrupt control register iicic 47h fffff1bch interrupt control register ad0ic 47h fffff1beh interrupt control register ad1ic 47h fffff1c0h interrupt control register ad2ic 47h fffff1c2h interrupt control register tm0eqic0 47h fffff1c4h interrupt control register tm1eqic0 47h fffff1c6h interrupt control register tm2eqic0 47h fffff1c8h interrupt control register tm3eqic0 47h fffff1cah interrupt control register adt0ic 47h fffff1cch interrupt control register adt1ic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h fffff200h a/d0 conversion result register 0 ad0cr0 0000h fffff201h a/d0 conversion result register 0h ad0cr0h 00h fffff202h a/d0 conversion result register 1 ad0cr1 0000h fffff203h a/d0 conversion result register 1h ad0cr1h r 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 83 (5/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff204h a/d0 conversion result register 2 ad0cr2 0000h fffff205h a/d0 conversion result register 2h ad0cr2h 00h fffff206h a/d0 conversion result register 3 ad0cr3 0000h fffff207h a/d0 conversion result register 3h ad0cr3h 00h fffff208h a/d0 conversion result register 4 ad0cr4 0000h fffff209h a/d0 conversion result register 4h ad0cr4h 00h fffff20ah a/d0 conversion result register 5 ad0cr5 0000h fffff20bh a/d0 conversion result register 5h ad0cr5h 00h fffff20ch a/d0 conversion result register 6 ad0cr6 0000h fffff20dh a/d0 conversion result register 6h ad0cr6h 00h fffff20eh a/d0 conversion result register 7 ad0cr7 0000h fffff20fh a/d0 conversion result register 7h ad0cr7h 00h fffff210h a/d0 conversion result register 8 ad0cr8 0000h fffff211h a/d0 conversion result register 8h ad0cr8h 00h fffff212h a/d0 conversion result register 9 ad0cr9 0000h fffff213h a/d0 conversion result register 9h ad0cr9h 00h fffff214h a/d0 conversion result register 10 ad0cr10 0000h fffff215h a/d0 conversion result register 10h ad0cr10h 00h fffff216h a/d0 conversion result register 11 ad0cr11 0000h fffff217h a/d0 conversion result register 11h ad0cr11h 00h fffff218h a/d0 conversion result register 12 ad0cr12 0000h fffff219h a/d0 conversion result register 12h ad0cr12h 00h fffff21ah a/d0 conversion result register 13 ad0cr13 0000h fffff21bh a/d0 conversion result register 13h ad0cr13h 00h fffff21ch a/d0 conversion result register 14 ad0cr14 0000h fffff21dh a/d0 conversion result register 14h ad0cr14h 00h fffff21eh a/d0 conversion result register 15 ad0cr15 0000h fffff21fh a/d0 conversion result register 15h ad0cr15h r 00h fffff220h a/d converter 0 scan mode register ad0scm 0000h fffff220h a/d converter 0 scan mode register l ad0scml 00h fffff221h a/d converter 0 scan mode register h ad0scmh 00h fffff222h a/d converter 0 conversion time control register ad0ctc 00h fffff224h a/d converter 0 conversion channel specification register ad0chen 0000h fffff224h a/d converter 0 conversion channel specification register l ad0chenl 00h fffff225h a/d converter 0 conversion channel specification register h ad0chenh 00h fffff230h a/d converter 0 control register ad0ctl0 00h fffff231h a/d converter 0 trigger select register ad0tsel 10h fffff232h a/d converter 0 channel specification register 1 ad0ch1 r/w 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 84 (6/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff233h a/d converter 0 channel specification register 2 ad0ch2 r/w 00h fffff240h a/d0 conversion result expansion register 0 ad0ecr0 0000h fffff241h a/d0 conversion result expansion register 0h ad0ecr0h 00h fffff242h a/d0 conversion result expansion register 1 ad0ecr1 0000h fffff243h a/d0 conversion result expansion register 1h ad0ecr1h 00h fffff244h a/d0 conversion result expansion register 2 ad0ecr2 0000h fffff245h a/d0 conversion result expansion register 2h ad0ecr2h 00h fffff246h a/d0 conversion result expansion register 3 ad0ecr3 0000h fffff247h a/d0 conversion result expansion register 3h ad0ecr3h 00h fffff248h a/d0 conversion result expansion register 4 ad0ecr4 0000h fffff249h a/d0 conversion result expansion register 4h ad0ecr4h 00h fffff254h a/d converter 0 flag register ad0flg 00h fffff255h a/d converter 0 flag buffer register ad0flgb r 00h fffff260h operational amplifier 0 control register 0 op0ctl0 00h fffff261h comparator 0 control register 0 cmp0ctl0 r/w 00h fffff262h comparator 0 control register 1 cmp0ctl1 r 00h fffff263h comparator 0 control register 2 cmp0ctl2 00h fffff264h comparator 0 control register 3 cmp0ctl3 00h fffff270h a/d converter 0 clock select register ad0ocks 00h fffff274h a/d converter 1 clock select register ad1ocks 00h fffff278h comparator output digital noise elimination register 0l cmpnfc0l 00h fffff27ah comparator output digital noise elimination register 0f cmpnfc0f 00h fffff27ch comparator output digital noise elimination register 1l cmpnfc1l 00h fffff27eh comparator output digital noise elimination register 1f cmpnfc1f r/w 00h fffff280h a/d1 conversion result register 0 ad1cr0 0000h fffff281h a/d1 conversion result register 0h ad1cr0h 00h fffff282h a/d1 conversion result register 1 ad1cr1 0000h fffff283h a/d1 conversion result register 1h ad1cr1h 00h fffff284h a/d1 conversion result register 2 ad1cr2 0000h fffff285h a/d1 conversion result register 2h ad1cr2h 00h fffff286h a/d1 conversion result register 3 ad1cr3 0000h fffff287h a/d1 conversion result register 3h ad1cr3h 00h fffff288h a/d1 conversion result register 4 ad1cr4 0000h fffff289h a/d1 conversion result register 4h ad1cr4h 00h fffff28ah a/d1 conversion result register 5 ad1cr5 0000h fffff28bh a/d1 conversion result register 5h ad1cr5h 00h fffff28ch a/d1 conversion result register 6 ad1cr6 0000h fffff28dh a/d1 conversion result register 6h ad1cr6h 00h fffff28eh a/d1 conversion result register 7 ad1cr7 0000h fffff28fh a/d1 conversion result register 7h ad1cr7h 00h fffff290h a/d1 conversion result register 8 ad1cr8 0000h fffff291h a/d1 conversion result register 8h ad1cr8h r 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 85 (7/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff292h a/d1 conversion result register 9 ad1cr9 0000h fffff293h a/d1 conversion result register 9h ad1cr9h 00h fffff294h a/d1 conversion result register 10 ad1cr10 0000h fffff295h a/d1 conversion result register 10h ad1cr10h 00h fffff296h a/d1 conversion result register 11 ad1cr11 0000h fffff297h a/d1 conversion result register 11h ad1cr11h 00h fffff298h a/d1 conversion result register 12 ad1cr12 0000h fffff299h a/d1 conversion result register 12h ad1cr12h 00h fffff29ah a/d1 conversion result register 13 ad1cr13 0000h fffff29bh a/d1 conversion result register 13h ad1cr13h 00h fffff29ch a/d1 conversion result register 14 ad1cr14 0000h fffff29dh a/d1 conversion result register 14h ad1cr14h 00h fffff29eh a/d1 conversion result register 15 ad1cr15 0000h fffff29fh a/d1 conversion result register 15h ad1cr15h r 00h fffff2a0h a/d converter 1 scan mode register ad1scm 0000h fffff2a0h a/d converter 1 scan mode register l ad1scml 00h fffff2a1h a/d converter 1 scan mode register h ad1scmh 00h fffff2a2h a/d converter 1 conversion time control register ad1ctc 00h fffff2a4h a/d converter 1 conv ersion channel specification register ad1chen 0000h fffff2a4h a/d converter 1 conv ersion channel specification register l ad1chenl 00h fffff2a5h a/d converter 1 conv ersion channel specification register h ad1chenh 00h fffff2b0h a/d converter 1 control register ad1ctl0 00h fffff2b1h a/d converter 1 trigger select register ad1tsel 10h fffff2b2h a/d converter 1 channel specification register 1 ad1ch1 00h fffff2b3h a/d converter 1 channel specification register 2 ad1ch2 r/w 00h fffff2c0h a/d1 conversion result expansion register 0 ad1ecr0 0000h fffff2c1h a/d1 conversion result expansion register 0h ad1ecr0h 00h fffff2c2h a/d1 conversion result expansion register 1 ad1ecr1 0000h fffff2c3h a/d1 conversion result expansion register 1h ad1ecr1h 00h fffff2c4h a/d1 conversion result expansion register 2 ad1ecr2 0000h fffff2c5h a/d1 conversion result expansion register 2h ad1ecr2h 00h fffff2c6h a/d1 conversion result expansion register 3 ad1ecr3 0000h fffff2c7h a/d1 conversion result expansion register 3h ad1ecr3h 00h fffff2c8h a/d1 conversion result expansion register 4 ad1ecr4 0000h fffff2c9h a/d1 conversion result expansion register 4h ad1ecr4h 00h fffff2d4h a/d converter 1 flag register ad1flg 00h fffff2d5h a/d converter 1 flag buffer register ad1flgb r 00h fffff2e0h operational amplifier 1 control register 0 op1ctl0 00h fffff2e1h comparator 1 control register 0 cmp1ctl0 r/w 00h fffff2e2h comparator 1 control register 1 cmp1ctl1 r 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 86 (8/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff2e3h comparator 1 control register 2 cmp1ctl2 00h fffff2e4h comparator 1 control register 3 cmp1ctl3 00h fffff2f0h a/d trigger falling edge specification register adtf 00h fffff2f2h a/d trigger rising edge specification register adtr 00h fffff2f4h comparator output interrupt falling edge specification register cmpof 00h fffff2f6h comparator output interrupt rising edge specification register cmpor 00h fffff2f8h a/dldtrg1 input select register adlts1 00h fffff2fah a/dldtrg2 input select register adlts2 00h fffff310h digital noise elimination 0 control register 14 intnfc14 00h fffff312h digital noise elimination 0 control register 15 intnfc15 00h fffff314h digital noise elimination 0 control register 16 intnfc16 00h fffff400h port 0 register p0 undefined fffff402h port 1 register p1 undefined fffff404h port 2 register p2 undefined fffff406h port 3 register p3 undefined fffff408h port 4 register p4 undefined fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff424h port 2 mode register pm2 ffh fffff426h port 3 mode register pm3 ffh fffff428h port 4 mode register pm4 ffh fffff440h port 0 mode control register pmc0 00h fffff442h port 1 mode control register pmc1 00h fffff444h port 2 mode control register pmc2 00h fffff446h port 3 mode control register pmc3 00h fffff448h port 4 mode control register pmc4 00h fffff460h port 0 function control register pfc0 00h fffff462h port 1 function control register pfc1 00h fffff464h port 2 function control register pfc2 00h fffff466h port 3 function control register pfc3 00h fffff468h port 4 function control register pfc4 00h fffff480h bus cycle type configuration register 0 bct0 cccch fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff48eh bus clock division control register dvc 81h fffff540h tmm0 control register 0 tm0ctl0 00h fffff544h tmm0 compare register 0 tm0cmp0 0000h fffff550h tmm1 control register 0 tm1ctl0 r/w 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 87 (9/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff554h tmm1 compare register 0 tm1cmp0 0000h fffff560h tmm2 control register 0 tm2ctl0 00h fffff564h tmm2 compare register 0 tm2cmp0 0000h fffff570h tmm3 control register 0 tm3ctl0 00h fffff574h tmm3 compare register 0 tm3cmp0 0000h fffff580h tmt0 control register 0 tt0ctl0 00h fffff581h tmt0 control register 1 tt0ctl1 00h fffff582h tmt0 control register 2 tt0ctl2 note 00h fffff583h tmt0 i/o control register 0 tt0ioc0 note 00h fffff584h tmt0 i/o control register 1 tt0ioc1 note 00h fffff585h tmt0 i/o control register 2 tt0ioc2 note 00h fffff586h tmt0 i/o control register 3 tt0ioc3 note 00h fffff587h tmt0 option register 0 tt0opt0 00h fffff588h tmt0 option register 1 tt0opt1 note 00h fffff58ah tmt0 capture/compare register 0 tt0ccr0 0000h fffff58ch tmt0 capture/compare register 1 tt0ccr1 r/w 0000h fffff58eh tmt0 counter read buffer register tt0cnt r 0000h fffff590h tmt0 counter write register tt0tcw note 0000h fffff5a0h digital noise eliminati on 2 control register 0 ttnfc0 note 00h fffff5a2h digital noise eliminati on 2 control register 1 ttnfc1 00h fffff5a4h tmt0 capture input select register ttisl0 note undefined fffff5a6h tmt1 capture input select register ttisl1 undefined fffff5c0h tmt1 control register 0 tt1ctl0 00h fffff5c1h tmt1 control register 1 tt1ctl1 00h fffff5c2h tmt1 control register 2 tt1ctl2 00h fffff5c3h tmt1 i/o control register 0 tt1ioc0 00h fffff5c4h tmt1 i/o control register 1 tt1ioc1 00h fffff5c5h tmt1 i/o control register 2 tt1ioc2 00h fffff5c6h tmt1 i/o control register 3 tt1ioc3 00h fffff5c7h tmt1 option register 0 tt1opt0 00h fffff5c8h tmt1 option register 1 tt1opt1 00h fffff5cah tmt1 capture/compare register 0 tt1ccr0 0000h fffff5cch tmt1 capture/compare register 1 tt1ccr1 r/w 0000h fffff5ceh tmt1 counter read buffer register tt1cnt r 0000h fffff5d0h tmt1 counter write register tt1tcw 0000h fffff5e0h tab0 control register 0 tab0ctl0 00h fffff5e1h tab0 control register 1 tab0ctl1 00h fffff5e2h tab0 i/o control register 0 tab0ioc0 00h fffff5e3h tab0 i/o control register 1 tab0ioc1 00h fffff5e4h tab0 i/o control register 2 tab0ioc2 r/w 00h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 88 (10/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff5e5h tab0 option register 0 tab0opt0 00h fffff5e6h tab0 capture/compare register 0 tab0ccr0 0000h fffff5e8h tab0 capture/compare register 1 tab0ccr1 0000h fffff5eah tab0 capture/compare register 2 tab0ccr2 0000h fffff5ech tab0 capture/compare register 3 tab0ccr3 r/w 0000h fffff5eeh tab0 counter read buffer register tab0cnt r 0000h fffff600h tab0 option register 1 tab0opt1 00h fffff601h tab0 option register 2 tab0opt2 00h fffff602h tab0 i/o control register 3 tab0ioc3 a8h fffff603h tab0 option register 3 tab0opt3 00h fffff604h tab0 deadtime compare register tab0dtc 0000h fffff610h high-impedance output control register 00 hza0ctl0 00h fffff611h high-impedance output control register 01 hza0ctl1 00h fffff618h high-impedance output control register 10 hza1ctl0 00h fffff619h high-impedance output control register 11 hza1ctl1 note 00h fffff620h tab1 control register 0 tab1ctl0 00h fffff621h tab1 control register 1 tab1ctl1 00h fffff622h tab1 i/o control register 0 tab1ioc0 00h fffff623h tab1 i/o control register 1 tab1ioc1 00h fffff624h tab1 i/o control register 2 tab1ioc2 00h fffff625h tab1 option register 0 tab1opt0 00h fffff626h tab1 capture/compare register 0 tab1ccr0 0000h fffff628h tab1 capture/compare register 1 tab1ccr1 0000h fffff62ah tab1 capture/compare register 2 tab1ccr2 0000h fffff62ch tab1 capture/compare register 3 tab1ccr3 r/w 0000h fffff62eh tab1 counter read buffer register tab1cnt r 0000h fffff640h tab1 option register 1 tab1opt1 00h fffff641h tab1 option register 2 tab1opt2 00h fffff642h tab1 i/o control register 3 tab1ioc3 a8h fffff643h tab1 option register 3 tab1opt3 00h fffff644h tab1 deadtime compare register tab1dtc 0000h fffff650h high-impedance output control register 20 hza2ctl0 00h fffff651h high-impedance output control register 21 hza2ctl1 00h fffff658h high-impedance output control register 30 hza3ctl0 00h fffff659h high-impedance output control register 31 hza3ctl1 00h fffff660h taa0 control register 0 taa0ctl0 00h fffff661h taa0 control register 1 taa0ctl1 00h fffff665h taa0 option register 0 taa0opt0 00h fffff666h taa0 capture/compare register 0 taa0ccr0 0000h fffff668h taa0 capture/compare register 1 taa0ccr1 r/w 0000h fffff66ah taa0 counter read buffer register taa0cnt r 0000h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 89 (11/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff680h taa1 control register 0 taa1ctl0 00h fffff681h taa1 control register 1 taa1ctl1 00h fffff685h taa1 option register 0 taa1opt0 00h fffff686h taa1 capture/compare register 0 taa1ccr0 0000h fffff688h taa1 capture/compare register 1 taa1ccr1 r/w 0000h fffff68ah taa1 counter read buffer register taa1cnt r 0000h fffff6a0h taa2 control register 0 taa2ctl0 00h fffff6a1h taa2 control register 1 taa2ctl1 00h fffff6a2h taa2 i/o control register 0 taa2ioc0 00h fffff6a3h taa2 i/o control register 1 taa2ioc1 00h fffff6a4h taa2 i/o control register 2 taa2ioc2 00h fffff6a5h taa2 option register 0 taa2opt0 00h fffff6a6h taa2 capture/compare register 0 taa2ccr0 0000h fffff6a8h taa2 capture/compare register 1 taa2ccr1 r/w 0000h fffff6aah taa2 counter read buffer register taa2cnt r 0000h fffff6c0h oscillation stabilization time select register osts 04h fffff6d0h watchdog timer mode register wdtm 67h fffff6d1h watchdog timer enable register wdte 1ah fffff700h port 0 function control expansion register pfce0 00h fffff702h port 1 function control expansion register pfce1 00h fffff704h port 2 function control expansion register pfce2 00h fffff706h port 3 function control expansion register pfce3 00h fffff708h port 4 function control expansion register pfce4 00h fffff802h system status register sys 00h fffff810h dma trigger factor register 0 dtfr0 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl 01h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h/10h/01h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh
chapter 3 cpu function user?s manual u18279ej3v0ud 90 (12/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 r/w 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffa40h uartb control register 0 ubctl0 10h fffffa42h uartb control register 2 ubctl2 ffffh fffffa44h uartb status register ubstr r/w 00h fffffa46h uartb receive data register ap ubrxap 00ffh fffffa46h uartb receive data register ubrx r ffh fffffa48h uartb transmit data register ubtx w ffh fffffa4ah uartbfifo control register 0 ubfic0 00h fffffa4bh uartbfifo control register 1 ubfic1 00h fffffa4ch uartbfifo control register 2 ubfic2 0000h fffffa4ch uartbfifo control register 2l ubfic2l 00h fffffa4dh uartbfifo control register 2h ubfic2h r/w 00h fffffa4eh uartbfifo status register 0 ubfis0 00h fffffa4fh uartbfifo status register 1 ubfis1 r 10h fffffb00h taa3 control register 0 taa3ctl0 00h fffffb01h taa3 control register 1 taa3ctl1 00h fffffb02h taa3 i/o control register 0 taa3ioc0 note 00h fffffb03h taa3 i/o control register 1 taa3ioc1 note 00h fffffb04h taa3 i/o control register 2 taa3ioc2 note 00h fffffb05h taa3 option register 0 taa3opt0 00h fffffb06h taa3 capture/compare register 0 taa3ccr0 0000h fffffb08h taa3 capture/compare register 1 taa3ccr1 r/w 0000h fffffb0ah taa3 counter read buffer register taa3cnt r 0000h fffffb20h taa4 control register 0 taa4ctl0 00h fffffb21h taa4 control register 1 taa4ctl1 00h fffffb22h taa4 i/o control register 0 taa4ioc0 00h fffffb23h taa4 i/o control register 1 taa4ioc1 r/w 00h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 91 (13/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffffb24h taa4 i/o control register 2 taa4ioc2 00h fffffb25h taa4 option register 0 taa4opt0 00h fffffb26h taa4 capture/compare register 0 taa4ccr0 0000h fffffb28h taa4 capture/compare register 1 taa4ccr1 r/w 0000h fffffb2ah taa4 counter read buffer register taa4cnt r 0000h fffffb40h digital noise elimination 1 control register 2 tanfc2 00h fffffb42h digital noise eliminati on 1 control register 3 tanfc3 note 00h fffffb44h digital noise elimination 1 control register 4 tanfc4 00h fffffb80h a/d converter 2 mode register 0 ad2m0 00h fffffb81h a/d converter 2 mode register 1 ad2m1 00h fffffb82h a/d converter 2 channel sp ecification register ad2s r/w 00h fffffb90h a/d2 conversion result register 0 ad2cr0 0000h fffffb91h a/d2 conversion result register 0h ad2cr0h 00h fffffb92h a/d2 conversion result register 1 ad2cr1 0000h fffffb93h a/d2 conversion result register 1h ad2cr1h 00h fffffb94h a/d2 conversion result register 2 ad2cr2 0000h fffffb95h a/d2 conversion result register 2h ad2cr2h 00h fffffb96h a/d2 conversion result register 3 ad2cr3 0000h fffffb97h a/d2 conversion result register 3h ad2cr3h 00h fffffb98h a/d2 conversion result register 4 ad2cr4 note 0000h fffffb99h a/d2 conversion result register 4h ad2cr4h note 00h fffffb9ah a/d2 conversion result register 5 ad2cr5 note 0000h fffffb9bh a/d2 conversion result register 5h ad2cr5h note 00h fffffb9ch a/d2 conversion result register 6 ad2cr6 note 0000h fffffb9dh a/d2 conversion result register 6h ad2cr6h note 00h fffffb9eh a/d2 conversion result register 7 ad2cr7 note 0000h fffffb9fh a/d2 conversion result register 7h ad2cr7h note r 00h fffffbb0h port 7 register p7 r undefined fffffbb8h port 7 mode control register pmc7 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc02h external interrupt falling edge specification register 1 intf1 00h fffffc04h external interrupt falling edge specification register 2 intf2 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc22h external interrupt rising edge specification register 1 intr1 00h fffffc24h external interrupt rising edge specification register 2 intr2 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc42h pull-up resistor option register 1 pu1 00h fffffc44h pull-up resistor option register 2 pu2 00h fffffc46h pull-up resistor option register 3 pu3 00h fffffc48h pull-up resistor option register 4 pu4 r/w 00h note v850e/ig3 only
chapter 3 cpu function user?s manual u18279ej3v0ud 92 (14/14) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffffc66h port 3 function register pf3 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic ops clock select register iicocks 00h ffffff44h pull-up resistor option register dl pudl 0000h ffffff44h pull-up resistor option register dll pudll 00h ffffff45h pull-up resistor option register dlh pudlh r/w 00h
chapter 3 cpu function user?s manual u18279ej3v0ud 93 3.4.8 special registers special registers are registers that are protected from being written with illegal data due to a program loop. the v850e/if3 and v850e/ig3 have the fo llowing five special registers. ? power save control register (psc) ? processor clock control register (pcc) ? reset source flag register (resf) ? clock monitor mode register (clm) ? low-voltage detection register (lvim) in addition, a command register (prcmd) is provided to pr otect against a write access to the special registers so that the application system does not inadvertently stop due to a program loop . a write access to the special registers is made in a specific sequence, and an illegal store opera tion is reported to the system status register (sys).
chapter 3 cpu function user?s manual u18279ej3v0ud 94 (1) setting data to special registers set data to the special registers in the following sequence. <1> prepare data to be set to the special register in a general-purpose register. <2> write the data prepared in <1> to the command register. <3> write the setting data to the special regi ster (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<4> to <8> insert nop instructions (5 instructions).) note [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle and stop modes). <1> mov 0x02, r10 <2> st.b r10, prcmd[r0] ; write prcmd register. <3> st.b r10, psc[r0] ; set psc register. <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle mode or stop mode (by setting the psc.stb bit to 1). cautions 1. when a store instru ction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <2> and <3> above are performed by successive store instructions. if another instruction is placed between <2> and <3>, and if an interrupt is acknowledged by that inst ruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e command register, use the same general-purpose register used to set the special register (<3> in example) by using the store instruction to write data to the command register (<2> in example). the same applies when a general- purpose register is used for addressing. an example of setting the special register (< 3> in example) by using the bit manipulation instruction is shown below. clr1 4, resf[r0] 3. before executing this processing, terminate all dma tr ansfer operations.
chapter 3 cpu function user?s manual u18279ej3v0ud 95 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program loop. the first write access to a special register is valid after data has be en written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. an illegal write operation to a special register can be checked by using the sys.prerr bit. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). reset makes this register undefined. 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
chapter 3 cpu function user?s manual u18279ej3v0ud 96 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. if this register is not written in the correct sequence in cluding an access to the prcmd register, data is not written to the intended register, a protection error occurs , and the prerr flag is set. this register is cleared by writing ?0? to it by an instruction from cpu. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur. protection error occurred. prerr 0 1 protection error detection sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) ? when data is written to a special register without writing anything to the prcmd register (when <3> is executed without executing <2> in 3.4.8 (1) setting data to special registers ) ? when data is written to an on-chip peripheral i/o r egister other than a spec ial register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <3> in 3.4.8 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is r ead (excluding execution of a bit manipulation instruction) between a write access to the p rcmd register and a write access to a special register (such as an access to the internal ra m), the prerr flag is not set and data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the sys.prerr flag (ii) when the system is reset cautions 1. if 0 is written to the sys.prerr bit which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register, which is not a special re gister, immediately after a write access to the prcmd regist er, the prerr bit is set to 1.
chapter 3 cpu function user?s manual u18279ej3v0ud 97 3.4.9 system wait control register (vswc) the vswc register is a register that controls the bus access wait for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers of the v850e1 cp u core is basically made in 3 clocks; however, in the v850e/if3 and v850e/ig3, a wait set by the vswc register is required in addition to those 3 clocks. set 13h (set wait for 4 clocks) to vswc. this register can be read or written in 8-bit units (address: fffff06eh, initial value: 77h). cpu clock frequency (f cpu ) vswc set value 500 khz f cpu 64 mhz 13h caution when using the v850e/if3 and v850e/ig3 , the vswc register must be set first. set other registers if necessary after setting the vswc register. remark when a register includes status flags that indicate the statuses of the on-chip peripheral functions (such as uanstr) or a register that indicates the count value of a timer (such as taancnt) is accessed, a register access retry operation takes place if the ti ming at which the flag and count value changes and the timing of the register access ov erlap. consequently, access to the on-chip peripheral i/o register may take a long time.
user?s manual u18279ej3v0ud 98 chapter 4 port functions 4.1 features 4.1.1 v850e/if3 input-only ports: 4 i/o ports: 44 input data read/output data write is enabled in 1-bit units. on-chip pull-up resistor can be connected in 1-bit units (ports 0 to 4 and dl only). however, an on-chip pull-up resistor can only be connected when the pins are in input mode in the port mode, or when the pins function as input pins in the alternate-f unction mode. moreover, an on-chip pull-up resistor can be connected to the tob0t1 to tob0t3, tob0b1 to to b0b3, and toa21 pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the tob0off, toa2off, or tob1off pin or software processing. 4.1.2 v850e/ig3 input-only ports: 8 i/o ports: 56 input data read/output data write is enabled in 1-bit units. on-chip pull-up resistor can be connected in 1-bit units (ports 0 to 4 and dl only). however, an on-chip pull-up resistor can only be connecte d when the pins are in in put mode in the port mode, or when the pins function as input pi ns in the alternate-function mode. mo reover, an on-chip pull-up resistor can be connected to the tob0t1 to to b0t3, tob0b1 to tob0b3, toa21, tob1t1 to tob1 t3, tob1b1 to tob1b3, and toa31 pins, these are output pins in the alternate-function m ode, when these pins go into a high- impedance state due to the tob0off, tob1off, toa2off, or toa3o ff pin or software processing.
chapter 4 port functions user?s manual u18279ej3v0ud 99 4.2 port configuration 4.2.1 v850e/if3 the v850e/if3 incorporates a total of 48 input/output ports (including 4 input-only ports) labeled ports 0 to 4, 7, and dl. the port configuration is shown in figure 4-1. there are two power supply system s for the i/o buffer of a pin: av dd2 and ev dd0 , ev dd1 . the relationship between each of these power supplies and t he pin is shown in table 4-1. figure 4-1. port configuration (v850e/if3) port 0 p00 p01 port 1 p10 p17 port 2 p20 p27 port 3 p30 p37 port 4 p40 p47 port 7 p70 p73 port dl pdl0 pdl9 table 4-1. power supplies for i/o buffer of each pin (v850e/if3) power supply corresponding pins av dd2 p70 to p73 ev dd0 , ev dd1 p00, p01, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl9, reset
chapter 4 port functions user?s manual u18279ej3v0ud 100 4.2.2 v850e/ig3 the v850e/ig3 incorporates a total of 64 input/output ports (inclu ding 8 input-only ports) la beled ports 0 to 4, 7, and dl. the port configuratio n is shown in figure 4-2. there are two power su pply systems for the i/o buffer of a pin: av dd2 and ev dd0 , ev dd1 , ev dd2 . the relationship between each of these power supplies an d the pin is shown in table 4-2. figure 4-2. port configuration (v850e/ig3) port 0 p00 port 1 p10 p17 port 2 p07 p20 p27 port 3 p30 p37 port 4 p40 p47 port 7 p70 p77 port dl pdl0 pdl15 table 4-2. power supplies for i/o buffer of each pin (v850e/ig3) power supply corresponding pins av dd2 p70 to p77 ev dd0 , ev dd1 , ev dd2 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl15, reset, dck, ddi, ddo, dms, drst
chapter 4 port functions user?s manual u18279ej3v0ud 101 4.3 port configuration table 4-3. port configuration (v850e/if3) item configuration control registers port n register (pn: n = 0 to 4, 7, dl) port n mode register (pmn: n = 0 to 4, dl) port n mode control register (pmcn: n = 0 to 4, 7, dl) port n function control register (pfcn: n = 0 to 4) port n function control expansion register (pfcen: n = 0 to 4) pull-up resistor option register (pun: n = 0 to 4, dl) port 3 function register (pf3) ports input-only: 4, i/o: 44 pull-up resistor software control: 44 table 4-4. port configuration (v850e/ig3) item configuration control registers port n register (pn: n = 0 to 4, 7, dl) port n mode register (pmn: n = 0 to 4, dl) port n mode control register (pmcn: n = 0 to 4, 7, dl) port n function control register (pfcn: n = 0 to 4) port n function control expansion register (pfcen: n = 0 to 4) pull-up resistor option register (pun: n = 0 to 4, dl) port 3 function register (pf3) ports input-only: 8, i/o: 56 pull-up resistor software control: 56
chapter 4 port functions user?s manual u18279ej3v0ud 102 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 output 0. output 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: undefined r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-5. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note 1 . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read note 2 . input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note 1 . the pin status is read note 3 . notes 1. the value written to the output latch is retained until a new value is written to the output latch. 2. also, the value of the pn register is read when t he pmn register is in t he output mode while the alternate function is set. 3. if the pmn register is in the input mode while the alternat e function is set, the statuses of the pins at that time are read regardless of whether the alter nate function is an input or output function.
chapter 4 port functions user?s manual u18279ej3v0ud 103 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. port mode alternate function pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function
chapter 4 port functions user?s manual u18279ej3v0ud 104 (5) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) pull-up resistor option register (pun) pun is a register that specifies the c onnection of an on-chip pull-up resistor. each bit of the pull-up resistor option register correspon ds to one pin of port n and can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 control of on-chip pull-up resistor connection
chapter 4 port functions user?s manual u18279ej3v0ud 105 (7) port settings set the ports as follows. figure 4-3. register settings and pin functions pmcn register output mode input mode pmn register "0" "1" "0" "1" "0" "1" (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm caution to switch to external interrupt input (int pn) from the port mode (by changing the pmca.pmcam bit from 0 to 1), an external inte rrupt may be input if a wrong valid edge is detected. therefore, be sure to set ?no e dge detection? by intrk, intfk, adtr, or adtf register, select external interrupt input (intpn), and then specify the valid edge (v850e/if3: n = 00, 01, 08 to 18, adt0, adt1, a = 0 to 4, m = 0 to 7, k = 0 to 2, v850e/ig3: n = 00 to 18, adt0, adt1, a = 0 to 4, m = 0 to 7, k = 0 to 2)). when switching to the port mode from ext ernal interrupt input (intpn) (by changing the pmcam bit = from 1 to 0), an edge may be de tected. therefore, be sure to set ?no edge detection? by intrk, intfk, adtr, or ad tf register, and then select the port mode. remark switch to the alternate function usin g the following procedure (for n, see tables 4-3 and 4-4 ). <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrk, intfk, adtr, and adtf registers (when external interrupt pin is set). if the pmcn register is set before setting the pfcn and pfcen registers, an unexpected peripheral function may be selected while the pf cn and pfcen registers are being set.
chapter 4 port functions user?s manual u18279ej3v0ud 106 4.3.1 port 0 port 0 can be set to the input or output mode in 1-bit units. the number of i/o pins differs from one product to another. generic name number of i/o ports v850e/if3 2-bit i/o port v850e/ig3 8-bit i/o port port 0 has an alternate function as the following pins. table 4-6. alternate-function pins of port 0 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p00 70 91 19 a6 toa20/tia20/toa2off/intp00 i/o p01 69 90 18 b6 toa21/tia21/intp01 i/o p02 note 2 ? 89 17 c6 toa30 note 2 /tia30 note 2 /toa3off note 2 /intp02 note 2 i/o p03 note 2 ? 88 16 c7 toa31 note 2 /tia31 note 2 /intp03 note 2 i/o p04 note 2 ? 84 12 c8 tecr0 note 2 /tit00 note 2 /tot00 note 2 /intp04 note 2 i/o p05 note 2 ? 83 11 c9 tenc00 note 2 /evtt0 note 2 /intp05 note 2 input p06 note 2 ? 82 10 c10 tenc01 note 2 /tit01 note 2 /tot01 note 2 /intp06 note 2 i/o p07 note 2 ? 63 91 c12 intp07 note 2 /clkout note 3 i/o provided remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10) notes 1. software pull-up function 2. v850e/ig3 only 3. pd70f3454gc-8ea-a and 70f3454f1-da9-a only cautions 1. to control the high-impedance output of a timer for motor control, be sure to set the pmc0.pmc0n bit to 1 and then specify th e edge to be detected and enable the operation of the high-impeda nce output controller, because the output of the motor control timer may go into a high-impedance state if a wrong valid edge is detected (v850e/if3: n = 0, v850e/ig3: n = 0, 2). 2. when p01 and p03 (v850e/ig3 only) are used as toa21 and toa31 (v850e/ig3 only), they go into a high-impedance state by inputting the foll owing active signal. ? output of high impedance setting signa l from high impedance output controller ? output of clock stop detecti on signal from clock monitor
chapter 4 port functions user?s manual u18279ej3v0ud 107 cautions 3. to switch to external interrupt input (intp0n) from the port mode (by changing the pmc0.pmc0n bit from 0 to 1), an external in terrupt may be input if a wrong valid edge is detected. therefore, be sure to disab le edge detection (i ntf0.intf0n bit = 0 and intr0.intr0n bit = 0), select external interr upt input (intp0n), and then specify the valid edge (v850e/if3: n = 0, 1, v850e/ig3: n = 0 to 7). when switching to the port mode from ex ternal interrupt input (intp0n) (by changing the pmc0n bit from 1 to 0), an edge may be detected. therefore, be sure to disable edge detection (intf0n bit = 0, intr0n bit = 0), and then select the port mode. 4. to control high-impedance output of the external interrupt function and motor output control function, set the pmc0 n bit to 1 (v850e/if3: n = 0, 1, v850e/ig3: n = 0 to 7).
chapter 4 port functions user?s manual u18279ej3v0ud 108 (1) registers (a) port 0 register (p0) p07 note p0 p06 note p05 note p04 note p03 note p02 note p01 p00 after reset: undefined r/w address: fffff400h output 0. output 1. p0n 0 1 control of output data (in output mode) note valid only for the v850e/ig3. with the v850e/if3, the read val ue of this register is undefined. remark v850e/if3: n = 0, 1 v850e/ig3: n = 0 to 7 (b) port 0 mode register (pm0) pm07 note output mode input mode pm0n 0 1 control of i/o mode ( in port mode) pm0 pm06 note pm05 note pm04 note pm03 note pm02 note pm01 pm00 after reset: ffh r/w address: fffff420h note valid only for the v850e/ig3. with the v850e/if3, be sure to set this bit to 1. remark v850e/if3: n = 0, 1 v850e/ig3: n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 109 (c) port 0 mode control register (pmc0) pmc07 note 1 pmc0 pmc06 note 1 pmc05 note 1 pmc04 note 1 pmc03 note 1 pmc02 note 1 pmc01 pmc00 i/o port tenc00 input note 2 /evtt0 input note 2 /intp05 input note 2 pmc05 note 1 0 1 specification of operating mode of p05 pin specification of operating mode of p04 pin specification of operating mode of p03 pin specification of operating mode of p02 pin specification of operating mode of p01 pin specification of operating mode of p00 pin i/o port tecr0 input note 2 /tit00 input note 2 /tot00 output note 2 /intp04 input note 2 pmc04 note 1 0 1 i/o port toa31 output note 2 /tia31 input note 2 /intp03 input note 2 pmc03 note 1 0 1 i/o port toa30 output note 2 /tia30 input note 2 /toa3off input note 2 /intp02 input note 2 pmc02 note 1 0 1 i/o port toa21 output/tia21 input/intp01 input pmc01 0 1 i/o port toa20 output/tia20 input/toa2off input/intp00 input pmc00 0 1 after reset: 00h r/w address: fffff440h i/o port intp07 input note 2 /clkout output note 3 pmc07 note 1 0 1 specification of operating mode of p07 pin specification of operating mode of p06 pin i/o port tenc01 input note 2 /tit01 input note 2 /tot01 output note 2 /intp06 input note 1 pmc06 note 1 0 1 notes 1. valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. 2. v850e/ig3 only 3. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 110 (d) port 0 function control register (pfc0) pfc07 note pfc0 pfc06 note pfc05 note pfc04 note pfc03 note pfc02 note pfc01 pfc00 after reset: 00h r/w address: fffff460h note valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. remark for the specifications of alternate functions, see 4.3.1 (1) (f) settings of al ternate functions of port 0 . (e) port 0 function contro l expansion register (pfce0) 0 pfce0 pfce06 note pfce05 note pfce04 note pfce03 note pfce02 note pfce01 pfce00 after reset: 00h r/w address: fffff700h note valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. remark for the specifications of alternate functions, see 4.3.1 (1) (f) settings of al ternate functions of port 0 .
chapter 4 port functions user?s manual u18279ej3v0ud 111 (f) setting of alternate function of port 0 pfc07 note 1 specification of alternate function of p07 note 1 pin 0 intp07 input note 1 1 clkout output note 2 pfce06 note 1 pfc06 note 1 specification of alternate function of p06 note 1 pin 0 0 tenc01 input note 1 /tit01 input note 1 (two functions are alternately used) 0 1 tot01 output note 1 1 0 intp06 input note 1 1 1 setting prohibited pfce05 note 1 pfc05 note 1 specification of alternate function of p05 note 1 pin 0 0 tenc00 input note 1 0 1 evtt0 input note 1 1 0 intp05 input note 1 1 1 setting prohibited pfce04 note 1 pfc04 note 1 specification of alternate function of p04 note 1 pin 0 0 tecr0 input note 1 /tit00 input note 1 (two functions are alternately used) 0 1 tot00 output note 1 1 0 intp04 input note 1 1 1 setting prohibited pfce03 note 1 pfc03 note 1 specification of alternate function of p03 note 1 pin 0 0 toa31 output note 1 0 1 tia31 input note 1 1 0 intp03 input note 1 1 1 setting prohibited pfce02 note 1 pfc02 note 1 specification of alternate function of p02 note 1 pin 0 0 toa30 output note 1 0 1 tia30 input note 1 1 0 toa3off input note 1 /intp02 input note 1 (two functions are alternately used) 1 1 setting prohibited notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 112 pfce01 pfc01 specification of alternate function of p01 pin 0 0 toa21 output 0 1 tia21 input 1 0 intp01 input 1 1 setting prohibited pfce00 pfc00 specification of alternate function of p00 pin 0 0 toa20 output 0 1 tia20 input 1 0 toa2off input/intp00 input 1 1 setting prohibited (g) pull-up resistor option register 0 (pu0) pu07 note 1 pu0 pu06 note 1 pu05 note 1 pu04 note 1 pu03 note 1 pu02 note 1 pu01 pu00 after reset: 00h r/w address: fffffc40h do not connect connect note 2 pu0n 0 1 control of on-chip pull-up resistor connection notes 1. valid only in the v850e/ig3. with the v850e/if3, be su re to set this bit to 0. 2. an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode. moreover, an on-chip pull-up resistor can be connected to the toa21 and toa31 (v850e/ig3 only) pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the toa2off or toa3off (v850e/ig3 only) pin, or software proc essing. an on-chip pull-up resistor cannot be connected when the pins are in output mode. remark v850e/if3: n = 0, 1 v850e/ig3: n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 113 4.3.2 port 1 port 1 can be set to the input or output mode in 1-bit units. port 1 has an alternate function as the following pins. table 4-7. alternate-function pins of port 1 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p10 78 99 27 b3 tob0t1/tib01/tob01/a0 note 2 i/o p11 77 98 26 c3 tob0b1/tib02/tob02/a1 note 2 i/o p12 76 97 25 a4 tob0t2/tib03/tob03/a2 note 2 i/o p13 75 96 24 b4 tob0b2/tib00/a3 note 2 i/o p14 74 95 23 c4 tob0t3/evtb0/a4 note 2 i/o p15 73 94 22 a5 tob0b3/trgb0/a5 note 2 i/o p16 72 93 21 b5 tob0off/intp08/adtrg0/intadt0/a6 note 2 i/o p17 71 92 20 c5 tob00/intp09/a7 note 2 i/o provided notes 1. software pull-up function 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only caution when p10 to p15 are used as tob0t1 to tob0t3 and tob0b1 to to b0b3, they go into a high- impedance state by inputting the following active signal. ? output of high impedance setting signa l from high impedance output controller ? output of clock stop detecti on signal from clock monitor remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 114 (1) registers (a) port 1 register (p1) p17 p1 p16 p15 p14 p13 p12 p11 p10 after reset: undefined r/w address: fffff402h output 0. output 1. p1n 0 1 control of output data (in output mode) remark n = 0 to 7 (b) port 1 mode register (pm1) pm17 output mode input mode pm1n 0 1 control of i/o mode ( in port mode) pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 after reset: ffh r/w address: fffff422h remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 115 (c) port 1 mode control register (pmc1) pmc17 pmc1 pmc16 pmc15 pmc14 pmc13 pmc12 pmc11 pmc10 i/o port tob0b3 output/trgb0 input/a5 output note pmc15 0 1 specification of operating mode of p15 pin specification of operating mode of p14 pin specification of operating mode of p13 pin specification of operating mode of p12 pin specification of operating mode of p11 pin specification of operating mode of p10 pin i/o port tob0t3 output/evtb0 input/a4 output note pmc14 0 1 i/o port tob0b2 output/tib00 input/a3 output note pmc13 0 1 i/o port tob0t2 output/tib03 input/tob03 output/a2 output note pmc12 0 1 i/o port tob0b1 output/tib02 input/tob02 output/a1 output note pmc11 0 1 i/o port tob0t1 output/tib01 input/tob01output/a0 output note pmc10 0 1 after reset: 00h r/w address: fffff442h i/o port tob00 output/intp09 input/a7 output note pmc17 0 1 specification of operating mode of p17 pin specification of operating mode of p16 pin i/o port tob0off input/intp08 input/adtrg0 input/intadt0 input/a6 output note pmc16 0 1 note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 116 (d) port 1 function control register (pfc1) pfc17 pfc1 pfc16 pfc15 pfc14 pfc13 pfc12 pfc11 pfc10 after reset: 00h r/w address: fffff462h remark for the specifications of alternate functions, see 4.3.2 (1) (f) settings of al ternate functions of port 1 . (e) port 1 function contro l expansion register (pfce1) pfce17 pfce1 pfce16 pfce15 pfce14 pfce13 pfce12 pfce11 pfce10 after reset: 00h r/w address: fffff702h remark for the specifications of alternate functions, see 4.3.2 (1) (f) settings of al ternate functions of port 1 .
chapter 4 port functions user?s manual u18279ej3v0ud 117 (f) settings of alternate functions of port 1 pfce17 pfc17 specification of alternate function of p17 pin 0 0 tob00 output 0 1 intp09 input 1 0 a7 output note 1 1 setting prohibited pfce16 pfc16 specification of alternate function of p16 pin 0 0 tob0off input/intp08 input (two functions are alternately used) 0 1 adtrg0 input/intadt0 input (two functions are alternately used) 1 0 a6 output note 1 1 setting prohibited pfce15 pfc15 specification of alternate function of p15 pin 0 0 tob0b3 output 0 1 trgb0 input 1 0 a5 output note 1 1 setting prohibited pfce14 pfc14 specification of alternate function of p14 pin 0 0 tob0t3 output 0 1 evtb0 input 1 0 a4 output note 1 1 setting prohibited pfce13 pfc13 specification of alternate function of p13 pin 0 0 tob0b2 output 0 1 tib00 input 1 0 a3 output note 1 1 setting prohibited pfce12 pfc12 specification of alternate function of p12 pin 0 0 tob0t2 output 0 1 tib03 input 1 0 tob03 output 1 1 a2 output note note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 118 pfce11 pfc11 specification of alternate function of p11 pin 0 0 tob0b1 output 0 1 tib02 input 1 0 tob02 output 1 1 a1 output note pfce10 pfc10 specification of alternate function of p10 pin 0 0 tob0t1 output 0 1 tib01 input 1 0 tob01 output 1 1 a0 output note note pd70f3454gc-8ea-a and 70f3454f1-da9-a only (g) pull-up resistor option register 1 (pu1) pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 after reset: 00h r/w address: fffffc42h do not connect connect note pu1n 0 1 control of on-chip pull-up resistor connection note an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alter nate-function mode. moreover, an on-chip pull-up resistor can be connected to the tob0t1 to tob0 t3 and tob0b1 to tob0b3 pins, these are output pins in the alternate-function mode, when thes e pins go into a high-impedance state due to the tob0off pin, or software processing. an on-chip pull-up resistor cannot be connected when the pins are in output mode. remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 119 4.3.3 port 2 port 2 can be set to the input or output mode in 1-bit units. port 2 has an alternate function as the following pins. table 4-8. alternate-function pins of port 2 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p20 23 28 56 p3 tob1t1/tib11/tob11 i/o p21 24 29 57 n3 tob1b1/tib12/tob12 i/o p22 25 30 58 p4 tob1t2/tib13/tob13 i/o p23 26 31 59 n4 tob1b2/tib10 i/o p24 27 32 60 m4 tob1t3/evtb1 i/o p25 28 33 61 m5 tob1b3/trgb1 i/o p26 29 34 62 m6 tob10/tob1off/intp10/adtrg1/intadt1 i/o p27 36 45 73 m11 dms notes 2, 3 input provided notes 1. software pull-up function 2. v850e/ig3 only 3. the p27 pin also functions as an on-chip debug pin. the on-chip debug function or port function (including the alternate functions) can be selected by using the level of the drst pin, as shown in the table below. port 2 functions low-level input to drst pin high-level input to drst pin p27 dms caution when p20 to p25 are used as tob1t1 to tob1t3 and tob1b1 to tob1b3, they go into a high- impedance state by inputting the following active signal. ? output of high impedance setting signa l from high impedance output controller ? output of clock stop detecti on signal from clock monitor remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 120 (1) registers (a) port 2 register (p2) p27 p2 p26 p25 p24 p23 p22 p21 p20 after reset: undefined r/w address: fffff404h output 0. output 1. p2n 0 1 control of output data (in output mode) remark n = 0 to 7 (b) port 2 mode register (pm2) pm27 output mode input mode pm2n 0 1 control of i/o mode ( in port mode) pm2 pm26 pm25 pm24 pm23 pm22 pm21 pm20 after reset: ffh r/w address: fffff424h remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 121 (c) port 2 mode control register (pmc2) 0 pmc2 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 i/o port tob1b3 output/ trgb1 input pmc25 0 1 specification of operating mode of p25 pin specification of operating mode of p24 pin specification of operating mode of p23 pin specification of operating mode of p22 pin specification of operating mode of p21 pin specification of operating mode of p20 pin i/o port tob1t3 output/ evtb1 input pmc24 0 1 i/o port tob1b2 output/ tib10 input pmc23 0 1 i/o port tob1t2 output/ tib13 input/ tob13 output pmc22 0 1 i/o port tob1b1 output/ tib12 input/ tob12 output pmc21 0 1 i/o port tob1t1 output/ tib11 input/ tob11 output pmc20 0 1 after reset: 00h r/w address: fffff444h specification of operating mode of p26 pin i/o port tob10 output/tob1off input/intp10 input/adtrg1 input/intadt1 input pmc26 0 1
chapter 4 port functions user?s manual u18279ej3v0ud 122 (d) port 2 function control register (pfc2) 0 pfc2 pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 after reset: 00h r/w address: fffff464h remark for the specifications of alternate functions, see 4.3.3 (1) (f) settings of al ternate functions of port 2 . (e) port 2 function contro l expansion register (pfce2) 0 pfce2 pfce26 0 0 0 pfce22 pfce21 pfce20 after reset: 00h r/w address: fffff704h remark for the specifications of alternate functions, see 4.3.3 (1) (f) settings of al ternate functions of port 2 .
chapter 4 port functions user?s manual u18279ej3v0ud 123 (f) settings of alternate functions of port 2 pfce26 pfc26 specification of alternate function of p26 pin 0 0 tob10 output 0 1 tob1off input/intp10 input (two functions are alternately used) 1 0 adtrg1 input/intadt1 input (two functions are alternately used) 1 1 setting prohibited pfc25 specification of alternate function of p25 pin 0 tob1b3 output 1 trgb1 input pfc24 specification of alternate function of p24 pin 0 tob1t3 output 1 evtb1 input pfc23 specification of alternate function of p23 pin 0 tob1b2 output 1 tib10 input pfce22 pfc22 specification of alternate function of p22 pin 0 0 tob1t2 output 0 1 tib13 input 1 0 tob13 output 1 1 setting prohibited pfce21 pfc21 specification of alternate function of p21 pin 0 0 tob1b1 output 0 1 tib12 input 1 0 tob12 output 1 1 setting prohibited pfce20 pfc20 specification of alternate function of p20 pin 0 0 tob1t1 output 0 1 tib11 input 1 0 tob11 output 1 1 setting prohibited
chapter 4 port functions user?s manual u18279ej3v0ud 124 (g) pull-up resistor option register 2 (pu2) pu27 pu2 pu26 pu25 pu24 pu23 pu22 pu21 pu20 after reset: 00h r/w address: fffffc44h do not connect connect note pu2n 0 1 control of on-chip pull-up resistor connection note an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alter nate-function mode. moreover, an on-chip pull-up resistor can be connected to the tob1t1 to tob1 t3 and tob1b1 to tob1b3 pins, these are output pins in the alternate-function mode, when thes e pins go into a high-impedance state due to the tob1off pin, or software processing. an on-chip pull-up resistor cannot be connected when the pins are in output mode. remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 125 4.3.4 port 3 port 3 can be set to the input or output mode in 1-bit units. port 3 has an alternate function as the following pins. table 4-9. alternate-function pins of port 3 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p30 46 55 83 k13 rxda1/scl i/o p31 47 56 84 k12 txda1/sda i/o p32 48 57 85 j14 sib1/rxda2/cs1 note 2 i/o p33 49 58 86 j13 sob1/txda2 output p34 50 59 87 j12 sckb1/intp11/cs0 note 2 i/o p35 51 60 88 h14 sib2/rxdb input p36 52 61 89 h13 sob2/txdb output p37 53 62 90 h12 sckb2/intp12/astb note 2 i/o provided notes 1. software pull-up function 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 126 (1) registers (a) port 3 register (p3) p37 p3 p36 p35 p34 p33 p32 p31 p30 after reset: undefined r/w address: fffff406h output 0. output 1. p3n 0 1 control of output data (in output mode) remark n = 0 to 7 (b) port 3 mode register (pm3) pm37 output mode input mode pm3n 0 1 control of i/o mode ( in port mode) pm3 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffh r/w address: fffff426h remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 127 (c) port 3 mode control register (pmc3) pmc37 pmc3 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 i/o port sib2 input/rxdb input pmc35 0 1 specification of operating mode of p35 pin specification of operating mode of p34 pin specification of operating mode of p33 pin specification of operating mode of p32 pin specification of operating mode of p31 pin specification of operating mode of p30 pin i/o port sckb1 i/o/intp11 input/cs0 output note pmc34 0 1 i/o port sob1 output/txda2 output pmc33 0 1 i/o port sib1 input/rxda2 input/cs1 output note pmc32 0 1 i/o port txda1 output/sda i/o pmc31 0 1 i/o port rxda1 input/scl i/o pmc30 0 1 after reset: 00h r/w address: fffff446h i/o port sckb2 i/o/ntp12 input/astb output note pmc37 0 1 specification of operating mode of p37 pin specification of operating mode of p36 pin i/o port sob2 output/txdb output pmc36 0 1 note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 128 (d) port 3 function control register (pfc3) pfc37 pfc3 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 after reset: 00h r/w address: fffff466h remark for the specifications of alternate functions, see 4.3.4 (1) (f) settings of al ternate functions of port 3 . (e) port 3 function contro l expansion register (pfce3) pfce37 pfce3 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 after reset: 00h r/w address: fffff706h remark for the specifications of alternate functions, see 4.3.4 (1) (f) settings of al ternate functions of port 3 .
chapter 4 port functions user?s manual u18279ej3v0ud 129 (f) settings of alternate functions of port 3 pfce37 pfc37 specification of alternate function of p37 pin 0 0 sckb2 input/output 0 1 intp12 input 1 0 astb output note 1 1 setting prohibited pfce36 pfc36 specification of alternate function of p36 pin 0 0 sob2 output 0 1 txdb output 1 0 setting prohibited 1 1 setting prohibited pfce35 pfc35 specification of alternate function of p35 pin 0 0 sib2 input 0 1 rxdb input 1 0 setting prohibited 1 1 setting prohibited pfce34 pfc34 specification of alternate function of p34 pin 0 0 sckb1 input/output 0 1 intp11 input 1 0 cs0 output note 1 1 setting prohibited pfc33 specification of alternate function of p33 pin 0 sob1 output 1 txda2 output pfce32 pfc32 specification of alternate function of p32 pin 0 0 sib1 input 0 1 rxda2 input 1 0 cs1 output note 1 1 setting prohibited note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 130 pfce31 pfc31 specification of alternate function of p31 pin 0 0 txda1 output 0 1 sda input/output 1 0 setting prohibited 1 1 setting prohibited pfce30 pfc30 specification of alternate function of p30 pin 0 0 rxda1 input 0 1 scl input/output 1 0 setting prohibited 1 1 setting prohibited (g) pull-up resistor option register 3 (pu3) pu37 pu3 pu36 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h do not connect connect note pu3n 0 1 control of on-chip pull-up resistor connection note an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the al ternate-function mode (including the sckb1 and sckb2 pins in the slave mode). an on-chip pull-up resistor cannot be connected when the pins are in output mode. remark n = 0 to 7 (h) port 3 function register (pf3) 0 pf3 0 0 0 0 0 pf31 pf30 after reset: 00h r/w address: fffffc66h normal output (cmos output) n-ch open-drain output note pf3n 0 1 control of normal output/n-ch open-drain output note when using i 2 c, set as n-ch open-drain output. remark n = 0, 1
chapter 4 port functions user?s manual u18279ej3v0ud 131 4.3.5 port 4 port 4 can be set to the input or output mode in 1-bit units. port 4 has an alternate function as the following pins. table 4-10. alternate-function pins of port 4 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p40 38 47 75 p12 sib0/rxda0 input p41 39 48 76 n12 sob0/txda0/dck notes 2, 3 i/o p42 40 49 77 m14 sckb0/intp13/ddi notes 2, 3 i/o p43 41 50 78 m13 tecr1/tit10/tot10/intp14 i/o p44 42 51 79 l14 tenc10/evtt1/intp15/wait note 4 input p45 43 52 80 l13 tenc11/tit11/tot11/intp16/wr1 note 4 i/o p46 44 53 81 l12 toa40/tia40/intp17/wr0 note 4 i/o p47 45 54 82 k14 toa41/tia41/intp18/rd note 4 i/o provided notes 1. software pull-up function 2. v850e/ig3 only 3. the p41 and p42 pins also function as on-chip de bug pins. the on-chip debug function or port function (including the alternate functions) can be selected by using the level of the drst pin, as shown in the table below. port 4 functions low-level input to drst pin high-level input to drst pin p41/sob0/txda0 dck p42/sckb0/intp13 ddi 4. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 132 (1) registers (a) port 4 register (p4) p47 p4 p46 p45 p44 p43 p42 p41 p40 after reset: undefined r/w address: fffff408h output 0. output 1. p4n 0 1 control of output data (in output mode) remark n = 0 to 7 (b) port 4 mode register (pm4) pm47 output mode input mode pm4n 0 1 control of i/o mode ( in port mode) pm4 pm46 pm45 pm44 pm43 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 133 (c) port 4 mode control register (pmc4) pmc47 pmc4 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 i/o port sckb0 input/output/intp13 input/ddi input note 2 pmc42 0 1 specification of operating mode of p42 pin specification of operating mode of p41 pin specification of operating mode of p40 pin i/o port sob0 output/txda0 output/dck input note 2 pmc41 0 1 i/o port sib0 input/rxda0 input pmc40 0 1 after reset: 00h r/w address: fffff448h i/o port toa41 output/tia41 input/intp18 input/rd output note 1 pmc47 0 1 specification of operating mode of p47 pin specification of operating mode of p46 pin i/o port toa40 output/tia40 input/intp17 input/wr0 output note 1 pmc46 0 1 i/o port tenc11 input/tit11 input/tot11 output/intp16 input/wr1 output note 1 pmc45 0 1 specification of operating mode of p45 pin specification of operating mode of p44 pin specification of operating mode of p43 pin i/o port tenc10 input/evtt1 input/intp15 input/wait input note 1 pmc44 0 1 i/o port tecr1 input/tit10 input/tot10 output/intp14 input pmc43 0 1 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 134 (d) port 4 function control register (pfc4) pfc47 pfc4 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 after reset: 00h r/w address: fffff468h remark for the specifications of alternate functions, see 4.3.5 (1) (f) settings of al ternate functions of port 4 . (e) port 4 function contro l expansion register (pfce4) pfce47 pfce4 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 0 after reset: 00h r/w address: fffff708h remark for the specifications of alternate functions, see 4.3.5 (1) (f) settings of al ternate functions of port 4 .
chapter 4 port functions user?s manual u18279ej3v0ud 135 (f) settings of alternate functions of port 4 pfce47 pfc47 specification of alternate function of p47 pin 0 0 toa41 output 0 1 tia41 input 1 0 intp18 input 1 1 rd output note pfce46 pfc46 specification of alternate function of p46 pin 0 0 toa40 output 0 1 tia40 input 1 0 intp17 input 1 1 wr0 output note pfce45 pfc45 specification of alternate function of p45 pin 0 0 tenc11 input/tit11 input (two functions are alternately used) 0 1 tot11 output 1 0 intp16 input 1 1 wr1 output note pfce44 pfc44 specification of alternate function of p44 pin 0 0 tenc10 input 0 1 evtt1 input 1 0 intp15 input 1 1 wait input note pfce43 pfc43 specification of alternate function of p43 pin 0 0 tecr1 input/tit10 input (two functions are alternately used) 0 1 tot10 output 1 0 intp14 input 1 1 setting prohibited pfce42 pfc42 specification of alternate function of p42 pin 0 0 sckb0 i/o 0 1 intp13 input 1 0 setting prohibited 1 1 setting prohibited note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 136 pfce41 pfc41 specification of alternate function of p41 pin 0 0 sob0 output 0 1 txda0 output 1 0 setting prohibited 1 1 setting prohibited pfc40 specification of alternate function of p40 pin 0 sib0 input 1 rxda0 input (g) pull-up resistor option register 4 (pu4) pu47 pu4 pu46 pu45 pu44 pu43 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h do not connect connect note pu4n 0 1 control of on-chip pull-up resistor connection note an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternat e-function mode (including the sckb0 pin in the slave mode). an on-chip pull-up resistor cannot be connected when the pins are in output mode. remark n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 137 4.3.6 port 7 port 7 is an input port with all its pins fixed to the input mode. the number of input port pins differs depending on the product. generic name number of i/o ports v850e/if3 4-bit input-only port v850e/ig3 8-bit input-only port port 7 has an alternate function as the following pins. table 4-11. alternate-function pins of port 7 pin no. if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 p70 20 25 53 l1 ani20 input p71 19 24 52 l2 ani21 input p72 18 23 51 l3 ani22 input p73 17 22 50 k1 ani23 input p74 note 2 ? 21 49 k2 ani24 note 2 input p75 note 2 ? 20 48 k3 ani25 note 2 input p76 note 2 ? 19 47 k4 ani26 note 2 input p77 note 2 ? 18 46 j4 ani27 note 2 input none notes 1. software pull-up function 2. v850e/ig3 only remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 138 (1) registers (a) port 7 register (p7) p77 note p7 p76 note p75 note p74 note p73 p72 p71 p70 after reset: undefined r address: fffffbb0h input low level. input high level. p7n 0 1 control of input data note valid only in the v850e/ig3. with the v850e/if3, the read val ue of this register is undefined. caution when using a port input pin and analog input pin (ani2n) together, be sure to set (1) the bit (pmc7n) of the pmc7 register to be used as the ani2n pin. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 (b) port 7 mode control register (pmc7) pmc77 note pmc7 pmc76 note pmc75 note pmc74 note pmc73 pmc72 pmc71 pmc70 input por t (reading p7n enabled. input buffer is on when this bit is read) ani2n inpu t (reading p7n disabled. input buffer is off when this bit is read) pmc7n 0 1 specification of operating mode of p7n pin after reset: 00h r/w address: fffffbb8h note valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. cautions 1. do not change to the port mode using a/d converter 2 during a/d conversion. 2. the pmc7 register enables or disables reading of the p7 regi ster. when the pmc7n bit = 1, the input buffer does not turn on even when the p7 register is read. in this case, the read value of the p7n bit is fixed to the low level (v850e/if3: n = 0 to 3, v850e/ig3: n = 0 to 7). this is to prevent through-current that may flow when the ani2n input (intermediate level) is read. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 4 port functions user?s manual u18279ej3v0ud 139 4.3.7 port dl port dl can be set to the input or output mode in 1-bit units. port dl has an alternate function as the following pins. table 4-12. alternate-function pins of port dl pin no, if3 ig3 pin name gc gc gf f1 alternate-function pin name i/o pull-up note 1 pdl0 65 81 9 a10 ad0 note 3 i/o pdl1 64 80 8 b10 ad1 note 3 i/o pdl2 63 79 7 a11 ad2 note 3 i/o pdl3 62 78 6 b11 ad3 note 3 i/o pdl4 61 77 5 c11 ad4 note 3 i/o pdl5 60 76 4 a12 ad5 note 3 /flmd1 note 4 i/o pdl6 59 75 3 b12 ad6 note 3 i/o pdl7 58 74 2 c14 ad7 note 3 i/o pdl8 57 73 1 c13 ad8 note 3 i/o pdl9 56 72 100 d14 ad9 note 3 i/o pdl10 note 2 ? 71 99 d13 ad10 note 3 i/o pdl11 note 2 ? 70 98 d12 ad11 note 3 i/o pdl12 note 2 ? 69 97 e14 ad12 note 3 i/o pdl13 note 2 ? 68 96 e13 ad13 note 3 i/o pdl14 note 2 ? 67 95 e12 ad14 note 3 i/o pdl15 note 2 ? 66 94 f12 ad15 note 3 i/o provided notes 1. software pull-up function 2. v850e/ig3 only 3. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 4. this pin is used in the flash programming mode and does not have to be manipulated by a port control register. for details, see chapter 27 flash memory . remark if3: v850e/if3 ig3: v850e/ig3 gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 4 port functions user?s manual u18279ej3v0ud 140 (1) registers (a) port dl register (pdl) pdl (pdlh note 1 ) (pdll) after reset: undefined r/w address: pdl fffff004h pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdl15 note 2 pdl14 note 2 pdl13 note 2 pdl12 note 2 pdl11 note 2 pdl10 note 2 pdl9 pdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 output 0. output 1. pdln 0 1 control of output data (in output mode) notes 1. to read/write bits 8 to 15 of the pdl register in 8-bi t or 1-bit units, specify them as bits 0 to 7 of the pdlh register. 2. valid only in the v850e/ig3. with the v850e/if3, the read val ue of this register is undefined. remarks 1. the pdl register can be read or written in 16-bit units. when the higher 8 bits of the pdl register are used as the pdlh register, and the lower 8 bits, as the pdll register, these registers can be read or written in 8-bit or 1-bit units. 2. v850e/if3: n = 0 to 9 v850e/ig3: n = 0 to 15
chapter 4 port functions user?s manual u18279ej3v0ud 141 (b) port dl mode register (pmdl) output mode input mode pmdln 0 1 control of i/o mode ( in port mode) pmdl (pmdlh note 1 ) (pmdll) after reset: ffffh r/w address: pmdl fffff024h pmdll fffff024h, pmdlh fffff025h pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdl15 note 2 pmdl14 note 2 pmdl13 note 2 pmdl12 note 2 pdal11 note 2 pdal10 note 2 pmdl9 pmdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 notes 1. to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. 2. valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 1. remarks 1. the pmdl register can be read or written in 16-bit units. when the higher 8 bits of the pmdl register are used as the pmdlh register, and the lower 8 bits, as the pmdll register, these registers c an be read or written in 8-bit or 1-bit units. 2. v850e/if3: n = 0 to 9 v850e/ig3: n = 0 to 15
chapter 4 port functions user?s manual u18279ej3v0ud 142 (c) port dl mode control register (pmcdl) i/o port adn input/output pmcdln 0 1 specification of operating mode of pmcdln pin pmcdl (pmcdlh note 1 ) (pmcdll) after reset: 0000h r/w address: pmcdl fffff044h pmcdll fffff044h, pmcdlh fffff045h pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdl15 note 2 pmcdl14 note 2 pmcdl13 note 2 pmcdl12 note 2 pmcdl11 note 2 pmcdl10 note 2 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 notes 1. to read/write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. 2. valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. remarks 1. the pmcdl register can be read or written in 16-bit units. when the higher 8 bits of the pmcdl register are used as the pmcdlh register, and the lower 8 bits, as the pmcdll register, these registers c an be read or written in 8-bit or 1-bit units. 2. v850e/if3: n = 0 to 9 v850e/ig3: n = 0 to 15
chapter 4 port functions user?s manual u18279ej3v0ud 143 (d) pull-up resistor option register dl (pudl) pudl15 note 2 pudl (pudlh note 1 ) (pudll) pudl14 note 2 pudl13 note 2 pudl12 note 2 pudl11 note 2 pudl10 note 2 pudl9 pudl8 do not connect connect note 3 pudln 0 1 control of on-chip pull-up resistor connection pudl7 pudl6 pudl5 pudl4 pudl3 pudl2 pudl1 pudl0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pudl ffffff44h pudll ffffff44h, pudlh ffffff45h notes 1. to read/write bits 8 to 15 of the pudl register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the pudlh register. 2. valid only in the v850e/ig3. with the v850e/if3, be sure to set these bits to 0. 3. an on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode. an on-chip pull-up resistor cannot be con nected when the pins are in output mode. remarks 1. the pudl register can be read or written in 16-bit units. when the higher 8 bits of the pudl register are used as the pudlh register, and the lower 8 bits, as the pudll register, these registers c an be read or written in 8-bit or 1-bit units. 2. v850e/if3: n = 0 to 9 v850e/ig3: n = 0 to 15
chapter 4 port functions user?s manual u18279ej3v0ud 144 4.4 output data and port read value for each setting table 4-14 shows the values used to select the alternate function of the respective pins, output data and port read values for each setting. in addition to the settings shown in table 4-14, the setting of each peripheral function control register is required.
chapter 4 port functions user?s manual u18279ej3v0ud 145 table 4-13. output data and port read value for each setting (1/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch toa20, toa21, toa30 note , toa31 note 1 0 0 1 alternate output (timer output) pin level 0 port latch tia20, tia21, tia30 note , tia31 note 1 0 1 1 ? pin level alternate input (timer input) 0 port latch p00, p01, p02 note , p03 note toa2off, intp00, intp01, toa3off note , intp02 note , intp03 note 1 1 0 1 ? pin level alternate input (timer input, external interrupt input (necessary to specify valid edge)) output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tecr0 note , tit00 note , tenc01 note , tit01 note 1 0 0 1 ? pin level alternate input (timer input) 0 port latch tot00 note , tot01 note 1 0 1 1 alternate output (timer output) pin level 0 port latch p04 note , p06 note intp04 note , intp06 note 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) note v850e/ig3 only remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 146 table 4-13. output data and port read value for each setting (2/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tenc00 note 1 1 0 0 1 ? pin level alternate input (timer input) 0 port latch evtt0 note 1 1 0 1 1 ? pin level alternate input (timer input) 0 port latch p05 note 1 intp05 note 1 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) output port 0 port latch port latch input port 0 none 1 ? pin level 0 port latch intp07 note 1 1 none 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p07 note 1 clkout note 2 1 none 1 1 alternate output (bus output) pin level notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 147 table 4-13. output data and port read value for each setting (3/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob0t1, tob0b1, tob0t2 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch tib01 to tib03 1 0 1 1 ? pin level alternate input (timer input) 0 port latch tob01 to tob03 1 1 0 1 alternate output 2 (timer output) pin level 0 port latch p10 to p12 a0 note , a1 note , a2 note 1 1 1 1 alternate output 3 (bus output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob0b2, tob0t3, tob0b3 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch tib00, evtb0, trgb0 1 0 1 1 ? pin level alternate input (timer input) 0 port latch p13 to p15 a3 note , a4 note , a5 note 1 1 0 1 alternate output 2 (bus output) pin level note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 148 table 4-13. output data and port read value for each setting (4/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob0off/intp08 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch adtrg0/intadt0 1 0 1 1 ? pin level alternate input (a/d input, external interrupt input (necessary to specify valid edge)) 0 port latch p16 a6 note 1 1 0 1 alternate output 2 (bus output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob00 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch intp09 1 0 1 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p17 a7 note 1 1 0 1 alternate output 2 (bus output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob1t1, tob1b1, tob1t2 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch tib11 to tib13 1 0 1 1 ? pin level alternate input (timer input) 0 port latch p20 to p22 tob11 to tob13 1 1 0 1 alternate output 2 (timer output) pin level note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 149 table 4-13. output data and port read value for each setting (5/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 none 1 ? pin level 0 port latch tob1b2, tob1t3, tob1b3 1 none 0 1 alternate output (timer output) pin level 0 port latch p23 to p25 tib10, evtb1, trgb1 1 none 1 1 ? pin level alternate input (timer input) output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tob10 1 0 0 1 alternate output (timer output) pin level 0 port latch tob1off/intp10 1 0 1 1 ? pin level alternate input (timer input, external interrupt input (necessary to specify valid edge)) 0 port latch p26 adtrg1/intadt1 1 1 0 1 ? pin level alternate input (a/d input, external interrupt input (necessary to specify valid edge)) output port 0 port latch port latch p27 note input port none none none 1 ? pin level note the p27 pin is also used for on-chip debugging (v850e/ig3 only). switching between on-chip debu g function and port function ( including the alternate function) can be set by using the drst pin level. the following shows the setting method. port 2 functions low-level input to drst pin high-level input to drst pin p27 dms remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 150 table 4-13. output data and port read value for each setting (6/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch rxda1 1 0 0 1 ? pin level alternate input (serial input) 0 port latch p30 scl 1 0 1 1 alternate i/o (serial i/o) pin level output in master mode input in slave mode output port 0 port latch port latch input port 0 1 ? pin level 0 port latch txda1 1 0 0 1 alternate output (serial output) pin level 0 port latch p31 sda 1 0 1 1 alternate i/o (serial i/o) pin level output in master mode input in slave mode output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sib1 1 0 0 1 ? pin level alternate input (serial input) 0 port latch rxda2 1 0 1 1 ? pin level alternate input (serial input) 0 port latch p32 cs1 note 1 1 0 1 alternate output (bus output) pin level note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 151 table 4-13. output data and port read value for each setting (7/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 none 1 ? pin level 0 port latch sob1 1 none 0 1 alternate output 1 (serial output) pin level 0 port latch p33 txda2 1 none 1 1 alternate output 2 (serial output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sckb1 1 0 0 1 alternate i/o (serial i/o) pin level output in master mode input in slave mode 0 port latch intp11 1 0 1 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p34 cs0 note 1 1 0 1 alternate output (bus output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sib2 1 0 0 1 ? pin level alternate input (serial input) 0 port latch p35 rxdb 1 0 1 1 ? pin level alternate input (serial input) note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 152 table 4-13. output data and port read value for each setting (8/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sob2 1 0 0 1 alternate output 1 (serial output) pin level 0 port latch p36 txdb 1 0 1 1 alternate output 2 (serial output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sckb2 1 0 0 1 alternate i/o (serial i/o) pin level output in master mode input in slave mode 0 port latch intp12 1 0 1 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p37 astb note 1 1 0 1 alternate output (bus output) pin level output port 0 port latch port latch input port 0 none 1 ? pin level 0 port latch sib0 1 none 0 1 ? pin level alternate input (serial input) 0 port latch p40 rxda0 1 none 1 1 ? pin level alternate input (serial input) note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 153 table 4-13. output data and port read value for each setting (9/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sob0 1 0 0 1 alternate output 1 (serial output) pin level 0 port latch p41 note txda0 1 0 1 1 alternate output 2 (serial output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch sckb0 1 0 0 1 alternate i/o (serial i/o) pin level output in master mode input in slave mode 0 port latch p42 note intp13 1 0 1 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) note the p41 and p42 pins are also used for on-chip debugging (v850e /ig3 only). switching between on-chip debug function and port function (including the alternate function) can be set by using the drst pin level. the following shows the setting method. port 4 functions low-level input to drst pin high-level input to drst pin p41/sob0/txda0 dck p42/sckb0/intp13 ddi remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 154 table 4-13. output data and port read value for each setting (10/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tecr1/tit10 1 0 0 1 ? pin level alternate input (timer input) 0 port latch tot10 1 0 1 1 alternate output (timer output) pin level 0 port latch p43 intp14 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tenc10 1 0 0 1 ? pin level alternate input (timer input) 0 port latch evtt1 1 0 1 1 alternate output (timer output) pin level 0 port latch intp15 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p44 wait note 1 1 1 1 ? pin level alternate input (bus input) note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 155 table 4-13. output data and port read value for each setting (11/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark output port 0 port latch port latch input port 0 1 ? pin level 0 port latch tenc11/tit11 1 0 0 1 ? pin level alternate input (timer input) 0 port latch tot11 1 0 1 1 alternate output 1 (timer output) pin level 0 port latch intp16 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p45 wr1 note 1 1 1 1 alternate output 2 (bus output) pin level output port 0 port latch port latch input port 0 1 ? pin level 0 port latch toa40, toa41 1 0 0 1 alternate output 1 (timer output) pin level 0 port latch tia40, tia41 1 0 1 1 ? pin level alternate input (timer input) 0 port latch intp17, intp18 1 1 0 1 ? pin level alternate input (external interrupt input (necessary to specify valid edge)) 0 port latch p46, p47 wr0 note , rd note 1 1 1 1 alternate output 2 (bus output) pin level note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark : don?t care
user?s manual u18279ej3v0ud chapter 4 port functions 156 table 4-13. output data and port read value for each setting (12/12) port name function pmcmn pfcemn pfcmn pmmn output data pmn read value remark input port 0 ? pin level p70 to p73, p74 to p77 note 1 ani20 to ani23, ani24 to ani27 note 1 1 none none none ? low level input-only port output port 0 port latch port latch input port 0 none none 1 ? pin level 0 port latch pdl0 to pdl9, pdl10 to pdl15 note 1 ad0 to ad15 note 2 1 none none 1 alternate i/o (bus i/o) pin level notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 3. the pdl5 pin is also used in flash programming mode. this pin does not have to be manipulated by a port control register. fo r details, see chapter 27 flash memory . remark : don?t care
chapter 4 port functions user?s manual u18279ej3v0ud 157 4.5 port register settings when alternate function is used the following shows the port register settings when each por t is used for an alternate function. when using a port pin as an alternate-function pin, re fer to the description of each pin.
user?s manual u18279ej3v0ud chapter 4 port functions 158 table 4-14. using port pin as alternate-function pin (1/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) toa20 output p00 = setting not required pm00 = setting not required pmc00 = 1 pfce00 = 0 pfc00 = 0 tia20 input p00 = setting not required pm00 = settin g not required pmc00 = 1 pfce00 = 0 pfc00 = 1 toa2off input p00 = setting not required pm00 = sett ing not required pmc00 = 1 pfce00 = 1 pfc00 = 0 p00 intp00 input p00 = setting not required pm00 = setting not requir ed pmc00 = 1 pfce00 = 1 pfc00 = 0 intf00 (intf0), intr00 (intr 0) toa21 output p01 = setting not required pm01 = setting not required pmc01 = 1 pfce01 = 0 pfc01 = 0 tia21 input p01 = setting not required pm01 = settin g not required pmc01 = 1 pfce01 = 0 pfc01 = 1 p01 intp01 input p01 = setting not required pm01 = setting not requir ed pmc01 = 1 pfce01 = 1 pfc01 = 0 intf01 (intf0), intr01 (intr 0) toa30 note output p02 = setting not required pm02 = setting not required pmc02 = 1 pfce02 = 0 pfc02 = 0 tia30 note input p02 = setting not required pm02 = setting not required pmc02 = 1 pfce02 = 0 pfc02 = 1 toa3off note input p02 = setting not required pm02 = setting not required pmc02 = 1 pfce02 = 1 pfc02 = 0 p02 note intp02 note input p02 = setting not required pm02 = setting not required pm c02 = 1 pfce02 = 1 pfc02 = 0 intf02 (intf0), intr02 (intr0) toa31 note output p03 = setting not required pm03 = setting not required pmc03 = 1 pfce03 = 0 pfc03 = 0 tia31 note input p03 = setting not required pm03 = setting not required pmc03 = 1 pfce03 = 0 pfc03 = 1 p03 note intp03 note input p03 = setting not required pm03 = setting not required pm c03 = 1 pfce03 = 1 pfc03 = 0 intf03 (intf0), intr03 (intr0) tecr0 note input p04 = setting not required pm04 = setting not required pmc04 = 1 pfce04 = 0 pfc04 = 0 tit00 note input p04 = setting not required pm04 = setting not required pmc04 = 1 pfce04 = 0 pfc04 = 0 tot00 note output p04 = setting not required pm04 = setting not required pmc04 = 1 pfce04 = 0 pfc04 = 1 p04 note intp04 note input p04 = setting not required pm04 = setting not required pm c04 = 1 pfce04 = 1 pfc04 = 0 intf04 (intf0), intr04 (intr0) tenc00 note input p05 = setting not required pm05 = setting not required pmc05 = 1 pfce05 = 0 pfc05 = 0 evtt0 note input p05 = setting not required pm05 = setting not required pmc05 = 1 pfce05 = 0 pfc05 = 1 p05 note intp05 note input p05 = setting not required pm05 = setting not required pm c05 = 1 pfce05 = 1 pfc05 = 0 intf05 (intf0), intr05 (intr0) note v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 159 table 4-14. using port pin as alternate-function pin (2/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) tenc01 note 1 input p06 = setting not required pm06 = setting not required pmc06 = 1 pfce06 = 0 pfc06 = 0 tit01 note 1 input p06 = setting not required pm06 = setting not required pmc06 = 1 pfce06 = 0 pfc06 = 0 tot01 note 1 output p06 = setting not required pm06 = setting not required pmc06 = 1 pfce06 = 0 pfc06 = 1 p06 note 1 intp06 note 1 input p06 = setting not required pm06 = setting not required pmc 06 = 1 pfce06 = 1 pfc06 = 0 in tf06 (intf0), intr06 (intr0) intp07 note 1 input p07 = setting not required pm07 = setting not required pmc07 = 1 ? pfc07 = 0 intf07 (intf0), intr07 (intr0) p07 note 1 clkout note 2 output p07 = setting not required pm07 = setting not required pmc07 = 1 ? pfc07 = 1 tob0t1 output p10 = setting not required pm10 = sett ing not required pmc10 = 1 pfce10 = 0 pfc10 = 0 tib01 input p10 = setting not required pm10 = settin g not required pmc10 = 1 pfce10 = 0 pfc10 = 1 tob01 output p10 = setting not required pm10 = setting not required pmc10 = 1 pfce10 = 1 pfc10 = 0 p10 a0 note 2 output p10 = setting not required pm10 = setting not required pmc10 = 1 pfce10 = 1 pfc10 = 1 tob0b1 output p11 = setting not required pm11 = setting not required pmc11 = 1 pfce11 = 0 pfc11 = 0 tib02 input p11 = setting not required pm11 = settin g not required pmc11 = 1 pfce11 = 0 pfc11 = 1 tob02 output p11 = setting not required pm11 = sett ing not required pmc11 = 1 pfce11 = 1 pfc11 = 0 p11 a1 note 2 output p11 = setting not required pm11 = setting not required pmc11 = 1 pfce11 = 1 pfc11 = 1 tob0t2 output p12 = setting not required pm12 = sett ing not required pmc12 = 1 pfce12 = 0 pfc12 = 0 tib03 input p12 = setting not required pm12 = settin g not required pmc12 = 1 pfce12 = 0 pfc12 = 1 tob03 output p12 = setting not required pm12 = setting not required pmc12 = 1 pfce12 = 1 pfc12 = 0 p12 a2 note 2 output p12 = setting not required pm12 = setting not required pmc12 = 1 pfce12 = 1 pfc12 = 1 tob0b2 output p13 = setting not required pm13 = setting not required pmc13 = 1 pfce13 = 0 pfc13 = 0 tib00 input p13 = setting not required pm13 = settin g not required pmc13 = 1 pfce13 = 0 pfc13 = 1 p13 a3 note 2 output p13 = setting not required pm13 = setting not required pmc13 = 1 pfce13 = 1 pfc13 = 0 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
user?s manual u18279ej3v0ud chapter 4 port functions 160 table 4-14. using port pin as alternate-function pin (3/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) tob0t3 output p14 = setting not required pm14 = setting not required pmc14 = 1 pfce14 = 0 pfc14 = 0 evtb0 input p14 = setting not required pm14 = settin g not required pmc14 = 1 pfce14 = 0 pfc14 = 1 p14 a4 note output p14 = setting not required pm14 = setting not required pmc14 = 1 pfce14 = 1 pfc14 = 0 tob0b3 output p15 = setting not required pm15 = setting not required pmc15 = 1 pfce15 = 0 pfc15 = 0 trgb0 input p15 = setting not required pm15 = settin g not required pmc15 = 1 pfce15 = 0 pfc15 = 1 p15 a5 note output p15 = setting not required pm15 = setting not required pmc15 = 1 pfce15 = 1 pfc15 = 0 tob0off input p16 = setting not required pm16 = sett ing not required pmc16 = 1 pfce16 = 0 pfc16 = 0 intp08 input p16 = setting not required pm16 = setting not requir ed pmc16 = 1 pfce16 = 0 pfc16 = 0 intf08 (intf1), intr08 (intr 1) adtrg0 input p16 = setting not required pm16 = sett ing not required pmc16 = 1 pfce16 = 0 pfc16 = 1 intadt0 input p16 = setting not required pm16 = setting not requir ed pmc16 = 1 pfce16 = 0 pfc16 = 1 adtf0 (adtf), adtr0 (adtr) p16 a6 note output p16 = setting not required pm16 = setting not required pmc16 = 1 pfce16 = 1 pfc16 = 0 tob00 output p17 = setting not required pm17 = setting not required pmc17 = 1 pfce17 = 0 pfc17 = 0 intp09 input p17 = setting not required pm17 = setting not requir ed pmc17 = 1 pfce17 = 0 pfc17 = 1 intf09 (intf1), intr09 (intr 1) p17 a7 note output p17 = setting not required pm17 = setting not required pmc17 = 1 pfce17 = 1 pfc17 = 0 tob1t1 output p20 = setting not required pm20 = setting not required pmc20 = 1 pfce20 = 0 pfc20 = 0 tib11 input p20 = setting not required pm20 = settin g not required pmc20 = 1 pfce20 = 0 pfc20 = 1 p20 tob11 output p20 = setting not required pm20 = setting not required pmc20 = 1 pfce20 = 1 pfc20 = 0 tob1b1 output p21 = setting not required pm21 = setting not required pmc21 = 1 pfce21 = 0 pfc21 = 0 tib12 input p21 = setting not required pm21 = settin g not required pmc21 = 1 pfce21 = 0 pfc21 = 1 p21 tob12 output p21 = setting not required pm21 = setting not required pmc21 = 1 pfce21 = 1 pfc21 = 0 tob1t2 output p22 = setting not required pm22 = setting not required pmc22 = 1 pfce22 = 0 pfc22 = 0 tib13 input p22 = setting not required pm22 = settin g not required pmc22 = 1 pfce22 = 0 pfc22 = 1 p22 tob13 output p22 = setting not required pm22 = setting not required pmc22 = 1 pfce22 = 1 pfc22 = 0 note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 161 table 4-14. using port pin as alternate-function pin (4/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) tob1b2 output p23 = setting not required pm23 = setting not required pmc23 = 1 ? pfc23 = 0 p23 tib10 input p23 = setting not required pm23 = setting not required pmc23 = 1 ? pfc23 = 1 tob1t3 output p24 = setting not required pm24 = setting not required pmc24 = 1 ? pfc24 = 0 p24 evtb1 input p24 = setting not required pm24 = setting not required pmc24 = 1 ? pfc24 = 1 tob1b3 output p25 = setting not required pm25 = setting not required pmc25 = 1 ? pfc25 = 0 p25 trgb1 input p25 = setting not required pm25 = setting not required pmc25 = 1 ? pfc25 = 1 tob10 output p26 = setting not required pm26 = setting not required pmc26 = 1 pfce26 = 0 pfc26 = 0 tob1off input p26 = setting not required pm26 = sett ing not required pmc26 = 1 pfce26 = 0 pfc26 = 1 intp10 input p26 = setting not required pm26 = setting not requi red pmc26 = 1 pfce26 = 0 pfc26 = 1 intf10 (intf1), intr10 (int r1) adtrg1 input p26 = setting not required pm26 = sett ing not required pmc26 = 1 pfce26 = 1 pfc26 = 0 p26 intadt1 input p26 = setting not required pm26 = setting not requi red pmc26 = 1 pfce26 = 1 pfc26 = 0 adtf1 (adtf), adtr1 (adtr) p27 dms notes 1 , 2 input p27 = setting not required pm27 = setting not required ? ? ? rxda1 input p30 = setting not required pm30 = sett ing not required pmc30 = 1 pfce30 = 0 pfc30 = 0 p30 scl i/o p30 = setting not required pm30 = setting not required pmc30 = 1 pfce30 = 0 pfc30 = 1 pf30 (pf3) = 1 txda1 output p31 = setting not required pm31 = setting not required pmc31 = 1 pfce31 = 0 pfc31 = 0 p31 sda i/o p31 = setting not required pm31 = setting not required pmc31 = 1 pfce31 = 0 pfc31 = 1 pf31 (pf3) = 1 notes 1. v850e/ig3 only 2. the p27 pin is also used for on-chip debugging. switching between on-chip debug function and port function can be set by usin g the drst pin level. the following shows the setting method. port 2 functions low-level input to drst pin high-level input to drst pin p27 dms
user?s manual u18279ej3v0ud chapter 4 port functions 162 table 4-14. using port pin as alternate-function pin (5/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) sib1 input p32 = setting not required pm32 = sett ing not required pmc32 = 1 pfce32 = 0 pfc32 = 0 rxda2 input p32 = setting not required pm32 = sett ing not required pmc32 = 1 pfce32 = 0 pfc32 = 1 p32 cs1 note output p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 1 pfc32 = 0 sob1 output p33 = setting not required pm33 = setting not required pmc33 = 1 ? pfc33 = 0 p33 txda2 output p33 = setting not required pm33 = setting not required pmc33 = 1 ? pfc33 = 1 sckb1 i/o p34 = setting not required pm34 = settin g not required pmc34 = 1 pfce34 = 0 pfc34 = 0 intp11 input p34 = setting not required pm34 = setting not requir ed pmc34 = 1 pfce34 = 0 pfc34 = 1 intf11 (intf1), intr11 (intr 1) p34 cs0 note output p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 1 pfc34 = 0 sib2 input p35 = setting not required pm35 = sett ing not required pmc35 = 1 pfce35 = 0 pfc35 = 0 p35 rxdb input p35 = setting not required pm35 = sett ing not required pmc35 = 1 pfce35 = 0 pfc35 = 1 sob2 output p36 = setting not required pm36 = sett ing not required pmc36 = 1 pfce36 = 0 pfc36 = 0 p36 txdb output p36 = setting not required pm36 = sett ing not required pmc36 = 1 pfce36 = 0 pfc36 = 1 sckb2 i/o p30 = setting not required pm37 = settin g not required pmc37 = 1 pfce37 = 0 pfc37 = 0 intp12 input p30 = setting not required pm37 = setting not requir ed pmc37 = 1 pfce37 = 0 pfc37 = 1 intf12 (intf1), intr12 (intr 1) p37 astb note output p30 = setting not required pm37 = setting not required pmc37 = 1 pfce37 = 1 pfc37 = 0 sib0 input p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 0 p40 rxda0 input p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 1 note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 4 port functions user?s manual u18279ej3v0ud 163 table 4-14. using port pin as alternate-function pin (6/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) sob0 output p41 = setting not required pm41 = setting not required pmc41 = 1 pfce41 = 0 pfc41 = 0 txda0 output p41 = setting not required pm41 = se tting not required pmc41 = 1 pfce41 = 0 pfc41 = 1 p41 dck notes 1 , 2 input p41 = setting not required pm41 = setting not required pmc41 = setting not required pfce41 = setting not required pfc41 = setting not required sckb0 i/o p42 = setting not required pm42 = setting not required pmc42 = 1 pfce42 = 0 pfc42 = 0 intp13 input p42 = setting not required pm42 = setting not requi red pmc42 = 1 pfce42 = 0 pfc42 = 1 intf13 (intf1), intr13 (intr 1) p42 ddi notes 1 , 2 input p42 = setting not required pm42 = setting not required pmc42 = setting not required pfce42 = setting not required pfc42 = setting not required tecr1 input p43 = setting not required pm43 = sett ing not required pmc43 = 1 pfce43 = 0 pfc43 = 0 tit10 input p43 = setting not required pm43 = sett ing not required pmc43 = 1 pfce43 = 0 pfc43 = 0 tot10 output p43 = setting not required pm43 = se tting not required pmc43 = 1 pfce43 = 0 pfc43 = 1 p43 intp14 input p43 = setting not required pm43 = setting not requi red pmc43 = 1 pfce43 = 1 pfc43 = 0 intf14 (intf2), intr14 (intr 2) tenc10 input p44 = setting not required pm44 = sett ing not required pmc44 = 1 pfce44 = 0 pfc44 = 0 evtt1 input p44 = setting not required pm44 = sett ing not required pmc44 = 1 pfce44 = 0 pfc44 = 1 intp15 input p44 = setting not required pm44 = setting not requi red pmc44 = 1 pfce44 = 1 pfc44 = 0 intf15 (intf2), intr15 (intr 2) p44 wait note 3 input p44 = setting not required pm44 = settin g not required pmc44 = 1 pfce44 = 1 pfc44 = 1 notes 1. v850e/ig3 only 2. the p41 and p42 pins are also used for on-chip debugging. s witching between on-chip debug function and port function (includin g alternate function) can be set by using the drst pin level. the following shows the setting method. port 4 functions low-level input to drst pin high-level input to drst pin p41/sob0/txda0 dck p42/sckb0/intp13 ddi 3. pd70f3454gc-8ea-a, 70f3454f1-da9-a only
user?s manual u18279ej3v0ud chapter 4 port functions 164 table 4-14. using port pin as alternate-function pin (7/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) tenc11 input p45 = setting not required pm45 = sett ing not required pmc45 = 1 pfce45 = 0 pfc45 = 0 tit11 input p45 = setting not required pm45 = sett ing not required pmc45 = 1 pfce45 = 0 pfc45 = 0 tot11 output p45 = setting not required pm45 = se tting not required pmc45 = 1 pfce45 = 0 pfc45 = 1 intp16 input p45 = setting not required pm45 = setting not requir ed pmc45 = 1 pfce45 = 1 pfc45 = 0 intf16 (intf2), intr16 (intr 2) p45 wr1 note 1 output p45 = setting not required pm45 = setting not required pmc45 = 1 pfce45 = 1 pfc45 = 1 toa40 output p46 = setting not required pm46 = setting not required pmc46 = 1 pfce46 = 0 pfc46 = 0 tia40 input p46 = setting not required pm46 = sett ing not required pmc46 = 1 pfce46 = 0 pfc46 = 1 intp17 input p46 = setting not required pm46 = setting not requir ed pmc46 = 1 pfce46 = 1 pfc46 = 0 intf17 (intf1), intr17 (intr 1) p46 wr0 note 1 output p46 = setting not required pm46 = setting not required pmc46 = 1 pfce46 = 1 pfc46 = 1 toa41 output p47 = setting not required pm47 = setting not required pmc47 = 1 pfce47 = 0 pfc47 = 0 tia41 input p47 = setting not required pm47 = sett ing not required pmc47 = 1 pfce47 = 0 pfc47 = 1 intp18 input p47 = setting not required pm47 = setting not requir ed pmc47 = 1 pfce47 = 1 pfc47 = 0 intf18 (intf1), intr18 (intr 1) p47 rd note 1 output p47 = setting not required pm47 = setting not required pmc47 = 1 pfce47 = 1 pfc47 = 1 p70 ani20 input p70 = setting not required ? pmc70 = 1 ? ? p71 ani21 input p71 = setting not required ? pmc71 = 1 ? ? p72 ani22 input p72 = setting not required ? pmc72 = 1 ? ? p73 ani23 input p73 = setting not required ? pmc73 = 1 ? ? p74 note 2 ani24 note 2 input p74 = setting not required ? pmc74 = 1 ? ? p75 note 2 ani25 note 2 input p75 = setting not required ? pmc75 = 1 ? ? p76 note 2 ani26 note 2 input p76 = setting not required ? pmc76 = 1 ? ? p77 note 2 ani27 note 2 input p77 = setting not required ? pmc77 = 1 ? ? notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 165 table 4-14. using port pin as alternate-function pin (8/8) alternate pin pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bit (register) pdl0 ad0 note 1 i/o pdl0 = setting not required pmdl0 = setting not required pmcdl0 = 1 ? ? pdl1 ad1 note 1 i/o pdl1 = setting not required pmdl1 = setting not required pmcdl1 = 1 ? ? pdl2 ad2 note 1 i/o pdl2 = setting not required pmdl2 = setting not required pmcdl2 = 1 ? ? pdl3 ad3 note 1 i/o pdl3 = setting not required pmdl3 = setting not required pmcdl3 = 1 ? ? pdl4 ad4 note 1 i/o pdl4 = setting not required pmdl4 = setting not required pmcdl4 = 1 ? ? ad5 note 1 i/o pdl5 = setting not required pmdl5 = setting not required pmcdl5 = 1 ? ? pdl5 flmd1 note 2 input pdl5 = setting not required pmdl5 = setting not required pmcdl5 = setting not required ? ? pdl6 ad6 note 1 i/o pdl6 = setting not required pmdl6 = setting not required pmcdl6 = 1 ? ? pdl7 ad7 note 1 i/o pdl7 = setting not required pmdl7 = setting not required pmcdl7 = 1 ? ? pdl8 ad8 note 1 i/o pdl8 = setting not required pmdl8 = setting not required pmcdl8 = 1 ? ? pdl9 ad9 note 1 i/o pdl9 = setting not required pmdl9 = setting not required pmcdl9 = 1 ? ? pdl10 note 3 ad10 note 1 i/o pdl10 = setting not required pmdl10 = setting not required pmcdl10 = 1 ? ? pdl11 note 3 ad11 note 1 i/o pdl11 = setting not required pmdl11 = setting not required pmcdl11 = 1 ? ? pdl12 note 3 ad12 note 1 i/o pdl12 = setting not required pmdl12 = setting not required pmcdl12 = 1 ? ? pdl13 note 3 ad13 note 1 i/o pdl13 = setting not required pmdl13 = setting not required pmcdl13 = 1 ? ? pdl14 note 3 ad14 note 1 i/o pdl14 = setting not required pmdl14 = setting not required pmcdl14 = 1 ? ? pdl15 note 3 ad15 note 1 i/o pdl15 = setting not required pmdl15 = setting not required pmcdl15 = 1 ? ? notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. the pdl5 pin is also used for a pin (flmd1) to be set in the flash programming mode. this pin does not need to be manipulated using the port control register. for details, see chapter 27 flash memory . 3. v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 166 4.6 noise eliminator a timing controller used to secure the noise elimination time is provided for the following pins. input signals that change within the noise elimination time are not internally acknowledged. table 4-15. noise eliminator (1/2) target pin filter type noise elimination width sampling clock reset drst note 1 flmd0 analog filter several 10 ns ? tia20 digital filter 2, 3 clocks f xx , f xx /4 selectable toa2off p00/toa20/tia20/toa2off/intp00 intp00 analog filter several 10 ns ? tia21 digital filter 2, 3 clocks f xx , f xx /4 selectable p01/toa21/tia21/intp01 intp01 analog filter several 10 ns ? tia30 note 1 digital filter 2, 3 clocks f xx , f xx /4 selectable toa3off note 1 p02 note 1 /toa30 note 1 /tia30 note 1 /toa3off note 1 / intp02 note 1 intp02 note 1 analog filter several 10 ns ? tia31 note 1 digital filter 2, 3 clocks f xx , f xx /4 selectable p03 note 1 /toa31 note 1 /tia31 note 1 /intp03 note 1 intp03 note 1 analog filter several 10 ns ? tecr0 note 1 / tit00 note 1 digital filter 2, 3 clocks f xx , f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p04 note 1 /tecr0 note 1 /tit00 note 1 /tot00 note 1 / intp04 note 1 intp04 note 1 analog filter several 10 ns ? tenc00 note 1 evtt0 note 1 digital filter 2, 3 clocks f xx , f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p05 note 1 /tenc00 note 1 /evtt0 note 1 /intp05 note 1 intp05 note 1 analog filter several 10 ns ? tenc01 note 1 / tit01 note 1 digital filter 2, 3 clocks f xx , f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p06 note 1 /tenc01 note 1 /tit01 note 1 /tot01 note 1 / intp06 note 1 intp06 note 1 p07 note 1 /intp07 note 1 /clkout note 2 intp07 note 1 analog filter several 10 ns ? p10/tob0t1/tib01/tob01/a0 note 2 tib01 p11/tob0b1/tib02/tob02/a1 note 2 tib02 p12/tob0t2/tib03/tob03/a2 note 2 tib03 p13/tob0b2/tib00/a3 note 2 tib00 p14/tob0t3/evtb0/a4 note 2 evtb0 p15/tob0b3/trgb0/a5 note 2 trgb0 digital filter 2, 3 clocks f xx /4 notes 1. v850e/ig3 only 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only cautions 1. the maskable interrupt pins can be used to release the standby mode. for details, see chapter 21 standby function. 2. the digital filter uses cl ock sampling and therefore cannot acknowledge an input signal when the peripheral clock (f xx ) is stopped (stop or idle mode). 3. the noise eliminator is valid only in the alternate-function mode.
chapter 4 port functions user?s manual u18279ej3v0ud 167 table 4-15. noise eliminator (2/2) target pin filter type noise elimination width sampling clock tob0off intp08 adtrg0 p16/tob0off/intp08/adtrg0/intadt0/ a6 note 1 intadt0 p17/tob00/intp09/a7 note 1 intp09 analog filter several 10 ns ? p20/tob1t1/tib11/tob11 tib11 p21/tob1b1/tib12/tob12 tib12 p22/tob1t2/tib13/tob13 tib13 p23/tob1b2/tib10 tib10 p24/tob1t3/evtb1 evtb1 p25/tob1b3/trgb1 trgb1 digital filter 2, 3 clocks f xx /4 tob1off intp10 adtrg1 p26/tob10/tob1off/intp10/adtrg1/ intadt1 intadt1 p34/sckb1/intp11/cs0 note 1 intp11 p37/sckb2/intp12/astb note 1 intp12 p42/sckb0/intp13/ddi note 2 intp13 analog filter several 10 ns ? tecr1/ tit10 f xx , f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p43/tecr1/tit10/tot10/intp14 intp14 f xx /4, f xx /16, f xx /64, f xx /128, f xx /256, f xx /512 selectable tenc10 evtt1 f xx , f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p44/tenc10/evtt1/intp15/wait note 1 intp15 f xx /4, f xx /16, f xx /64, f xx /128, f xx /256, f xx /512 selectable tenc11/ tit11 f xx /, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 selectable p45/tenc11/tit11/tot11/intp16/wr1 note 1 intp16 f xx /4, f xx /16, f xx /64, f xx /128, f xx /256, f xx /512 selectable tia40 digital filter 2, 3 clocks f xx , f xx /4 selectable p46/toa40/tia40/intp17/wr0 note 1 intp17 analog filter several 10 ns ? tia41 digital filter 2, 3 clocks f xx , f xx /4 selectable p47/toa41/tia41/intp18/rd note 1 intp18 analog filter several 10 ns ? notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. v850e/ig3 only cautions 1. the maskable interrupt pins can be used to release the standby mode. for details, see chapter 21 standby function. 2. the digital filter uses cl ock sampling and therefore cannot acknowledge an input signal when the peripheral clock (f xx ) is stopped (stop or idle mode). 3. the noise eliminator is valid only in the alternate-function mode.
chapter 4 port functions user?s manual u18279ej3v0ud 168 an example of timing of noise elimination by digital filter for intp14 to intp16, timer aa input pin, and timer t input pin is shown below. figure 4-4. example of noise elimination timing noise elimination clock input signal internal signal intp14 to intp16 rising edge detection intp14 to intp16 falling edge detection 3 clocks sampling 3 times 3 clocks 1 clock 1 clock 2 clocks 2 clocks sampling 3 times caution if there are two or fewer noise elimination clocks while the intp14 to intp16 input signals are high level (or low level), the input signal is eliminated as noise. if it is sampled three times or more, the edge is det ected as a valid input.
chapter 4 port functions user?s manual u18279ej3v0ud 169 (1) digital noise elimination 0 control register n (intnfcn) the intnfcn register is used to select the sampling cl ock that is used to eliminate digital noise on the intpn pin. if the same level is not detected on this pin th ree times in sequence using the clock selected by the intnfcn register, the signal is eliminated as noise. this register can be read or written in 8-bit units. reset sets this register to 00h. cautions 1. if the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal is detected as a valid edge or eliminated as noi se. so that the signal is actually detected as a valid edge, the same signal level must be input for a duration of 3 clocks or more. 2. if noise is generated in synchronization with the sampling clock, eliminate the noise by attaching a filter to the input pin. 3. noise is not eliminated if the pi n is used as a normal input port pin. intnfenn note enables digital noise elimination intnfenn 0 1 setting of digital noise elimination intnfcn (n = 14 to 16) 0000 intnfcn2 intnfcn1 intnfcn0 654321 after reset: 00h r/w address: intnfc14 fffff310h, intnfc15 fffff312h, intnfc16 fffff314h 0 f xx /4 f xx /16 f xx /64 f xx /128 f xx /256 f xx /512 setting prohibited intnfcn2 0 0 0 0 1 1 other than above sampling clock selection intnfcn1 0 0 1 1 0 0 intnfcn0 0 1 0 1 0 1 7 note when using the intpn pin, be sure to set the intnfe nn bit to 1 (digital noise elimination enabled). at the same time, a sampli ng clock must be selected. when using an alternate function of the intpn pin, set the intnfenn bit to 0.
chapter 4 port functions user?s manual u18279ej3v0ud 170 (2) digital noise elimination 1 control register n (tanfcn) the tanfcn register is used to select the sampling clock that is used to eliminate digital noise on the tian0 or tian1 pin. if the same level is not detected on these pi ns three times in sequence using the clock selected by the tanfcn register, the signal is eliminated as noise. this register can be read or written in 8-bit units. reset sets this register to 00h. cautions 1. if the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal is detected as a valid edge or eliminated as noi se. so that the signal is actually detected as a valid edge, the same signal level must be input for a duration of 3 clocks or more. 2. if noise is generated in synchronization with the sampling clock, eliminate the noise by attaching a filter to the input pin. 3. noise is not eliminated if the pi n is used as a normal input port pin. 4. the noise elimination function starts opera ting when the taanctl0.taance bit is set to 1 (enabling count operations). tanfenn disables digital noise elimination enables digital noise elimination tanfenn 0 1 setting of digital noise elimination 0 0 0 0 0 0 tanfcn0 654321 f xx f xx /4 tanfcn0 0 1 sampling clock selection after reset: 00h r/w address: tanfc2 fffffb40h, tanfc3 fffffb42h note , tanfc4 fffffb44h 0 7 tanfcn v850e/if3 n = 2, 4 v850e/ig3 n = 2 to 4 note v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 171 (3) digital noise elimination 2 control register n (ttnfcn) the ttnfcn register is used to select the sampling clock that is used to eliminate digital noise on the titn0, titn1, evttn, tencn0, tencn1, or tecr n pin. if the same level is not detected on these pins three times in sequence using the clock selected by the ttn fcn register, the signal is eliminated as noise. this register can be read or written in 8-bit units. reset sets this register to 00h. cautions 1. if the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal is detected as a valid edge or eliminated as noi se. so that the signal is actually detected as a valid edge, the same signal level must be input for a duration of 3 clocks or more. 2. if noise is generated in synchronization with the sampling clock, eliminate the noise by attaching a filter to the input pin. 3. noise is not eliminated if the pi n is used as a normal input port pin. 4. the noise elimination function starts ope rating when the ttnctl0.ttnce bit is set to 1 (enabling count operations). ttnfenn disables digital noise elimination enables digital noise elimination ttnfenn 0 1 setting of digital noise elimination 0 0 0 0 ttnfcn2 ttnfcn1 ttnfcn0 654321 after reset: 00h r/w address: ttnfc0 fffff5a0h note , ttnfc1 fffff5a2h 0 7 f xx f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 setting prohibited ttnfcn2 0 0 0 0 1 1 other than above sampling clock selection ttnfcn1 0 0 1 1 0 0 ttnfcn0 0 1 0 1 0 1 ttnfcn v850e/if3 n = 1 v850e/ig3 n = 0, 1 note v850e/ig3 only
chapter 4 port functions user?s manual u18279ej3v0ud 172 4.7 cautions 4.7.1 cautions on setting port pins (1) set the registers of a port in the following sequence. <1> set pfcn and pfcen registers. <2> set pmcn register. <3> set intfn and intrn registers. if the pmcn register is set before setting the pfcn and pfcen registers, an unexpected peripheral function may be selected while the pfcn an d pfcen registers are being set. (2) an on-chip pull-up resistor can only be connected when the pins are in input mode in the port mode, or when the pins function as input pins in the alternate-function mode. moreover, for the v850e/if3, an on-chip pull-up resi stor can be connected to the tob0t1 to tob0t3, tob0b1 to tob0b3, and toa21 pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the tob0off, to a2off, and tob1off pins or software processing. for the v850e/ig3, an on-chip pull-up resistor can be connected to the tob0t1 to tob0t3, tob0b1 to tob0b3, toa21, tob1t1 to tob1t3, tob1b1 to tob1b3, and toa31 pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the tob0off, toa2off, tob1off, and toa3off pins or software processing. set the on-chip pull-up resistor in the following sequence. <1> set pmcn register. <2> set pmn register. <3> set pu register. (3) set the n-ch open-drain in the following sequence. ? used in port mode <1> set pmcn register. <2> set pfn register. ? used as output pin in alternate-function mode of i 2 c <1> set pfcn and pfcen registers. <2> set pfn register. <3> set pmcn register.
chapter 4 port functions user?s manual u18279ej3v0ud 173 4.7.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when p20 pin is an output port, p21 to p27 pins are input ports (all pin statuses are high level), and the value of the port latch is 00h, if the output of p 20 pin is changed from low level to high level via a bit manipulation instruction, t he value of the port latch is ffh. explanation: the target bits of writing to and re ading from the pn register of a port whose pmnm bit is 1 are in the output latch stat us and pin status, respectively. a bit manipulation instruction is executed in t he following order in the v850e/if3 and v850e/ig3. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the output latch (0) of p20 pin, which is an output port, is read, while the pin statuses of p21 to p27 pins, which are input ports, are read. if the pin statuses of p21 to p27 pins are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-5. bit manipulati on instruction (p20 pin) low-level output bit manipulation instruction (set1 0, p2[r0]) is executed for p20 bit. pin status: high level p20 p21 to p27 port 2 latch 00000000 high-level output pin status: high level p20 p21 to p27 port 2 latch 11111111 bit manipulation instruction for p20 bit <1> p2 register is read in 8-bit units. ? in the case of p20, an output port, the value of the port latch (0) is read. ? in the case of p21 to p27, input ports, the pin status (1) is read. <2> set (1) the p20 bit. <3> write the results of <2> to the output latch of p2 register in 8-bit units.
user?s manual u18279ej3v0ud 174 chapter 5 clock generator 5.1 overview the features of clock generator are as follows. { oscillator ? in pll mode: f x = 4 to 8 mhz (f xx = 32 to 64 mhz) ? in clock-through mode: f x = 4 to 8 mhz (f xx = 4 to 8 mhz) { multiply ( 8 fixed) function by pll (phase locked loop) ? clock-through mode/pll mode selectable { internal system clock generation ? 4 steps (f xx , f xx /2, f xx /4, f xx /8) { peripheral clock generation { oscillation stabilization time selection caution the oscillation guarant eed range is 4 to 8 mhz. remark f x : oscillation frequency f xx : system clock frequency
chapter 5 clock generator user?s manual u18279ej3v0ud 175 5.2 configuration figure 5-1. clock generator selpll bit stop mode oscillation stabilization time wait prescaler 1 port 0 clock monitor oscillation stabilization time wait control (ost) prescaler 2 idle control halt control halt mode cpu clock peripheral clock watchdog timer clock high impedance output clock (timer for motor control) internal system clock oscillator oscillator stop control x1 x2 clkout note idle mode ck1, ck0 bits selector dvc1, dvc0 bits selector selector pll f xx /8 f xx /4 f xx /2 f xx f clk f clk /2 f clk /4 f cpu f clk f xx to f xx /4096 f xx f x external bus clock f bus note pd70f3454gc-8ea-a and 70f3454f1-da9-a only caution because f cpu and f clk do not go through pll immediately after reset, and f xx /8 is selected by prescaler 2, if f x = 8 mhz, f cpu and f clk are 1 mhz. remark f x : oscillation frequency f xx: system clock frequency f cpu: cpu cock frequency f clk: internal system clock frequency f bus: external bus clock frequency
chapter 5 clock generator user?s manual u18279ej3v0ud 176 table 5-1. operation clock of each function block function block operation clock cpu f cpu (selected from f xx to f xx /8 by pcc register) dma, interrupt controller f clk (selected from f xx to f xx /8 by pcc register) taa0, taa1 f xx taa taa2 to taa4 f xx /2 tab f xx tmt f xx /2 tmm f xx /2 watchdog timer f xx /1024 uarta f uclk (selected from f xx /2 to f xx /4096 by uanctl1 register) uartb f xx csib f cclk (selected from f xx /4 to f xx /256 by cbnctl1 register) i 2 c f xx /2 bus control function f bus (selected from f clk /1, f clk /2, f clk /4 by dvc register) a/d converters 0, 1 f ad01 (selected from f xx /2 to f xx /4 by adnocks register) a/d converter 2 f ad2 = f xx /2 remarks 1. f cpu: cpu cock frequency f xx : peripheral clock frequency f clk: internal system clock frequency f uclk : base clock frequency of uarta0 to uarta2 f cclk : base clock frequency of csib0 to csib2 f ad01 : base clock frequency of a/d converters 0 and 1 f ad2 : operating clock frequen cy of a/d converter 2 f bus: external bus clock frequency 2. n = 0, 1
chapter 5 clock generator user?s manual u18279ej3v0ud 177 (1) oscillator the main resonator oscillates the following frequencies (f x ): ? in pll mode ( 8 fixed): f x = 4 to 8 mhz (f xx = 32 to 64 mhz) ? in clock-through mode: f x = 4 to 8 mhz (f xx = 4 to 8 mhz) (2) idle control all functions other than the oscillator, pll, clock monitor operation, csib in slave mode, low-voltage detector (lvi), and power-on-clear circuit (poc) are stopped. (3) halt control only the cpu clock (f cpu ) is stopped. (4) pll this circuit multiplies the clock generated by the oscillator (f x ) by 8. it operates in two modes: clock-through mode in which f x is output as is by setting the selpll bit of the pll control register (pllctl), and pll mode in which a multiplied clock is output. (5) prescaler 1 this prescaler generates the clock (f xx to f xx /4096) to be supplied to on-chip peripheral functions. (6) prescaler 2 this circuit divides the system clock (f xx ). the clock (f xx to f xx /8) to be supplied to the cpu clock (f cpu ) and internal system clock (f clk ) is generated. (7) oscillation stabilization time wait control (ost) this unit measures the time from when the clock gener ated by the oscillator was i nput until oscillation is stabilized. it also counts the pll lockup time. the count clock can be selected from 2 14 /f x to 2 18 /f x . (8) clock monitor the clock monitor samples the clock generated by the oscillator (f x ), by using the internal oscillation clock. when it detects stop of oscillation, ou tput of the timer for motor control goes into a high-impedance state (for details, see chapter 10 motor control function ).
chapter 5 clock generator user?s manual u18279ej3v0ud 178 5.3 control registers the clock generator is controlled by the following six registers. ? pll control register (pllctl) ? processor clock control register (pcc) ? power save control register (psc) ? power save mode register (psmr) ? oscillation stabilization time select register (osts) ? clock monitor mode register (clm) (1) pll control register (pllctl) the pllctl register selects cpu operation clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 0 0 selpll 1 clock-through mode pll mode selpll 0 1 cpu operation clock selection after reset: 01h r/w address: fffff82ch < > cautions 1. be sure to set bits 7 to 2 to ?0? and set bit 0 to ?1?. 2. setting the selpll bit to 1 is enabled only wh en the pll clock freque ncy is stabilized. if the selpll bit is rewritten when the pll clock frequency is not stabilized (during unlock), 0 is written to the bit. theref ore, be sure to confirm that the pll mode has been set. use the following program for reference. _loop: set1 1, pllctl tst1 1, pllctl bz _loop (next instruction)
chapter 5 clock generator user?s manual u18279ej3v0ud 179 (2) processor clock control register (pcc) the pcc register is a special register. data can be wri tten to this register only in a combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. 0 pcc 0 0 0 0 0 ck1 ck0 after reset: 03h r/w address: fffff828h f xx f xx /2 f xx /4 f xx /8 ck1 0 0 1 1 clock selection (f clk /f cpu ) ck0 0 1 0 1 cautions 1. be sure to set bits 2 to 7 to ?0?. 2. set the pcc register to 00h after the pll mode is selected (p llctl.selpll bit = 1).
chapter 5 clock generator user?s manual u18279ej3v0ud 180 (3) power save control register (psc) the psc register is an 8-bit regist er that controls the standby func tion and specifies the standby mode by setting the stb bit. the psc register is a special register (see 3.4.8 special registers ). data can be written to this register only in a combination of specific sequences. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc 0 0 intm 0 0 stb 0 standby mode release by intxx request enabled standby mode release by intxx request disabled intm 0 1 standby mode control note 2 by maskable interrupt request (intxx note 1 ) normal mode standby mode stb 0 1 sets operation mode after reset: 00h r/w address: fffff1feh < > < > notes 1. for details, see table 20-1 interrupt source list . 2. setting is valid only in the idle mode and stop mode. cautions 1. be sure to set bits 0, 2, 3, and 5 to 7 to ?0?. 2. before setting a standby mode by setting the stb bit to 1, be sure to set the pcc register to 03h and then set the stb bit to 1. othe rwise, the standby mode may not be set or released. after releasing the standby mode, ch ange the value of the pcc register to the desired value. 3. to set the idle mode or stop mode, set the pcc register to 03h, and the psmr.psm0 bit in that order and then set the stb bit to 1.
chapter 5 clock generator user?s manual u18279ej3v0ud 181 (4) power save mode register (psmr) the psmr register is an 8-bit register that contro ls the operation in the software standby mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle mode stop mode psm0 0 1 specifies operation in software standby mode psmr 0 0 0 0 0 0 psm0 after reset: 00h r/w address: fffff820h < > cautions 1. be sure to set bits 1 to 7 to ?0?. 2. the psm0 bit is valid only when the psc.stb bit is 1.
chapter 5 clock generator user?s manual u18279ej3v0ud 182 (5) oscillation stabilization time select register (osts) the osts register selects the oscill ation stabilization time until the oscilla tion stabilizes after the stop mode is released by interrupt request. this register can be read or written in 8-bit units. reset sets this register to 04h. 0 osts 0 0 0 osts3 osts2 osts1 osts0 after reset: 04h r/w address: fffff6c0h 2 14 /f x (2.05 ms) 2 15 /f x (4.10 ms) 2 16 /f x (8.19 ms) 2 17 /f x (16.4 ms) 2 18 /f x (32.8 ms) setting prohibited other than above osts3 0 0 0 0 1 selection of oscillation stabilization time (f x = 8 mhz) osts2 1 1 1 1 0 osts1 0 0 1 1 0 osts0 0 1 0 1 0 cautions 1. the wait time does not include the time until the clock oscillation st arts (?a? in the figure below) following release of the stop mode. a stop mode release voltage waveform x2 pin cv dd 2. the default value of the osts register afte r reset is 04h. if an 8 mhz resonator is used, therefore, the oscillation stabilization time is about 2 ms. half the oscillation stabilization time is consumed by waiting for the lockup of pll. therefore, the actual stabilization time of the resonator is about 1 ms. when re leasing reset, therefore, make sure that the oscillation stabilization time is secured duri ng the active period of the reset signal. to release the stop mode by an interrupt input other than a reset signal (reset pin input, reset signal (lvires) generati on by low-voltage detector (lvi), reset signal (pocres) generation by power-on-clear circuit (poc )), the oscillation stabilization time is determined by the set value of the osts regi ster. therefore, set a time twice as long as that required for the resonator to stabilize to the osts register (because half the oscillation stabilization time is the stabilization time of pll). 3. be sure to set bits 4 to 7 to ?0?. remark f x : oscillation frequency
chapter 5 clock generator user?s manual u18279ej3v0ud 183 (6) clock monitor mode register (clm) the clm register sets clock monitor operation mode. the clm register is a special register. it can be written only in a combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 clock monitor operation disabled clock monitor operation enabled clme 0 1 clock monitor operation control clm 0 0 0 0 0 0 clme after reset: 00h r/w address: fffff870h cautions 1. the clme bit is cleared to 0 only after reset. 2. when the clme bit = 1, th e clock monitor function is fo rcibly stopped if the following conditions are satisfied. ? during oscillation stabilization time count after release of stop mode 3. when the clme bit = 1, output of the ti mer for motor control goes into a high-impedance state if oscillation (f x ) stop is detected. see figure 10-4 for the target timer output.
chapter 5 clock generator user?s manual u18279ej3v0ud 184 5.4 pll function 5.4.1 overview the cpu and the operating clock of the peripheral macro can be switched between output of the oscillation frequency multiplied by 8, and clock-through mode. when pll function is used: input clock (f x ) = 4 to 8 mhz, output clock (f xx ) = 32 to 64 mhz clock-through mode: input clock (f x ) = 4 to 8 mhz, output clock (f xx ) = 4 to 8 mhz 5.4.2 pll mode in the pll mode, the oscillation frequency (f x ) is multiplied by 8 with the pll to generate a system clock (f xx ). in the pll mode, the clock is input from the oscillator to the pll. a clock at a stable frequency must be supplied to the internal circuit after the lapse of the lockup time (f requency stabilization time) during which the phase is locked at a specific frequency and oscillation is st abilized. in the v850e/if3 and v850e/ig3, the lockup time after release of reset is secured automatically. caution when a resonator of f x = 8 mhz is used and if the oscillati on stabilization time of that resonator must be 3 ms (max.), the reset input (re set active) width must be 2 ms (min.). 5.4.3 clock-through mode in the clock-through mode, a system clock (f xx ) of the same frequency as the oscillation frequency (f x ) is generated.
chapter 5 clock generator user?s manual u18279ej3v0ud 185 5.5 operation 5.5.1 operation of each clock the following table shows the oper ation status of each clock. table 5-2. operation status of each clock power save mode oscillator (f x ) pll internal system clock (f clk ) peripheral clock (f xx to f xx /4096) external bus clock (f bus ) note 1 cpu clock (f cpu ) watchdog timer clock note 2 normal operation halt mode idle mode in stop mode and during oscillation stabilization time count after release of stop mode note 3 note 3 during reset pin input note 4 and subsequent oscillation stabilization time count note 5 note 6 notes 1. pd70f3454gc-8ea-a and 70f3454f1-da9-a only 2. the peripheral clock (f xx /1024) is used as the watchdog timer clock. 3. operation continues during on-chip debugging. 4. reset pin input, reset signal (wdtres) generatio n by watchdog timer, reset signal (lvires) generation by low-voltage detect or (lvi), or reset signal (po cres) generation by power-on-clear circuit (poc) 5. the output from the prescaler (prs) in not performed. 6. the clock is not output from the clkout pin. remark : operating : stopped 5.5.2 clock output function the clock output function is used to output the external bus clock (f bus ) from the clkout pin and supported only in the pd70f3454gc-8ea-a and 70f3454f1-da9-a. when the internal system clock (f clk ) in table 5-2 is in the operable status ( ), the pin can output the clock. when it is in the stopped status ( ), the pin cannot output the clock.
chapter 5 clock generator user?s manual u18279ej3v0ud 186 5.5.3 operation timing (1) power on (power-on reset) v dd0 , v dd1 <1> <2> <3> reset (input) fixed oscillation stabilization time of clock from oscillator 1.024 ms (at 8 mhz) pll lockup time 1.024 ms (at 8 mhz) ost counter 00h (initialization) 00h pll output clock internal reset signal x1 f cpu pll output stabilized oscillation stabilization time <4> f xx /8 of clock-through mode after reset <1> the oscillator is activa ted during the reset period that follows power application. make sure that the low-level width of the reset si gnal is ?oscillation stabilization time of the used resonator ? fixed oscillation stabilization time? or more, taking the oscillation stabilization time into consideration. pll stops during the reset period and fixed oscillation stabilization time. <2> when the fixed oscillation stabilization time that elapses after the reset signal is released expires, pll stop is released, and counting the lockup time starts. <3> pll is locked when counting of the lockup time is over. the ost counter is initialized to 00h. <4> when the lockup time expires, the cpu releases the reset signal and operates in the clock-through mode (f x ). the cpu operation clock (f cpu ) is f xx /8. the pll mode can be set by software. cautions 1. the clock generate d by the oscillator starts osc illating during the reset period. after the reset signal is released, a specifi c wait time (fixed oscillation stabilization time) elapses. 2. to avoid malfunction due to noise, do not change the division ratio of the cpu operation clock (f cpu ) by using the pcc register befo re setting the pll mode. before changing the division ratio, be sure to select the pll mode.
chapter 5 clock generator user?s manual u18279ej3v0ud 187 (2) reset input with power on v dd0 , v dd1 <1> <3> <2> h reset note fixed oscillation stabilization time of clock from oscillator 1.024 ms (at 8 mhz) ost counter 00h (initialization) 00h pll output stabilized pll output clock internal reset signal x1 f cpu pll lockup time 1.024 ms (at 8 mhz) <4> f xx /8 of clock-through mode after reset <1> the oscillator continues op erating during the reset period. pll stops during the reset period and fixed oscillation stabilization time. <2> when the fixed oscillation stabilization time that elaps es after the reset signal is released expires, pll stop is released, and counting the lockup time starts. <3> pll is locked when counting of the lockup time is over. the ost counter is initialized to 00h. <4> when the lockup time expires, the cpu releases the reset signal and operates in the clock-through mode (f x ). the cpu operation clock (f cpu ) is f xx /8. the pll mode can be set by software. note reset pin input, reset signal (wdtres) generation by the watchdog timer, reset signal (lvires) generation by the low-volt age detector (lvi), or reset signal (pocres) generation by the power-on- clear circuit (poc) cautions 1. the clock generated by the o scillator continues operating during a reset. after the reset signal is re leased, a specific wait time (fixed oscillation stabilization time) elapses. 2. to avoid malfunction due to noise, do not change the division ratio of the cpu operation clock (f cpu ) by using the pcc register befo re setting the pll mode. before changing the division ratio, be sure to select the pll mode.
chapter 5 clock generator user?s manual u18279ej3v0ud 188 (3) when releasing stop m ode by interrupt request v dd0 , v dd1 <1> <2> <3> <4> <5> <6> h stop status in stop mode stop mode released ost counter 00h (initialization) 00h pll output stabilized status before stop mode was set is resumed after release of stop mode pll output clock x1 f cpu fixed oscillation stabilization time of clock from oscillator is 1/2 of set value of osts register pll lockup time is 1/2 of set value of osts register <1> when the stop mode is set, both the oscillator and pll stop. at this time, pll is stopped in the stop mode. the ost counter is initialized. <2> when the stop mode is released, the oscillator is activated and the ost counter starts counting the oscillation stabilization time. at this time, pll remains stopped. <3> when half the oscillation stabilization time set to the osts has elapsed, pll starts operating. the clock generated by the oscillator must be stabiliz ed before pll starts oper ating. the actual oscillation stabilization time is ?1/2 the oscillation stabilization time?. take this into consideration when setting a value to the osts register. <4> after half the oscillation stabilization time has elapsed, the lockup wait time starts. the remaining count time of the ost counter is the lockup wait time. <5> when the lockup time of pll is over, clock supply to t he internal circuitry is started. at this time, the status before the stop mode was set is recovered. <6> the operation to be performed when the stop mode is released by a reset signal (reset pin input, reset signal (lvires) generation by the low-vo ltage detector (lvi), reset signal (pocres) generation by the power-on-clear circuit (poc)) is the same as that in (1) power on (power-on reset) and (2) reset input with power on .
chapter 5 clock generator user?s manual u18279ej3v0ud 189 5.6 clock monitor (1) clock monitor function the clock monitor samples the clock generated by the oscill ator, by using the internal oscillation clock. when it detects stop of oscillation, output of the timer for mo tor control goes into a high-impedance state (for details, see chapter 10 motor control function ). the high-impedance state created by the clock monitor function is released by a reset signal (reset pin input, reset signal (pocres) generation by the power-on- clear circuit (poc)) and the pin enters the status after reset.
user?s manual u18279ej3v0ud 190 chapter 6 16-bit timer/ event counter aa (taa) timer aa (taa) is a 16-bit timer/event counter. the v850e/if3 and v850e/ig3 incorporate taa0 to taa4. 6.1 overview the taan of channels are outlined below (n = 0 to 4). table 6-1. taan overview item taa0 taa1 taa2 taa3 taa4 clock selection 8 ways 8 wa ys 8 ways 8 ways 8 ways capture trigger input pin none none 2 note 1 2 external event count input pin none none 1 note 2 1 external trigger input pin none none 1 note 2 1 timer counter 1 1 1 1 1 capture/compare register 2 note 3 2 note 3 2 2 note 4 2 capture/compare match interrupt request signal 2 note 3 2 note 3 2 2 note 4 2 overflow interrupt request signal 1 1 1 1 1 timer output pin none none 2 note 1 2 notes 1. v850e/if3: none v850e/ig3: 2 2. v850e/if3: none v850e/ig3: 1 3. compare function only 4. in the v850e/if3, compare function only
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 191 6.2 functions the functions of taan that can be realized differ from o ne channel to another, as shown in the table below (n = 0 to 4). table 6-2. taan functions function taa0 taa1 taa2 taa3 taa4 interval timer external event counter note 1 external trigger pulse output note 1 one-shot pulse output note 1 pwm output note 1 free-running timer note 2 note 2 note 3 pulse width measurement note 1 timer tuning operation (tab0) (tab1) notes 1. v850e/if3: v850e/ig3: 2. compare function only 3. in the v850e/if3, compare function only
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 192 6.3 configuration taan includes the following hardware (n = 0 to 4). table 6-3. configuration of taan item configuration timer register 16-bit counter 1 registers taan capture/compare registers 0, 1 (taanccr0, taanccr1) taan counter read buffer register (taancnt) ccr0 and ccr1 buffer registers timer input 6 in total (tia20, tia21, tia30 note 1 , tia31 note 1 , tia40, tia41 pins) notes 2, 3 timer output 6 in total (toa20, toa21, toa30 note 1 , toa31 note 1 , toa40, toa41 pins) notes 2, 3 control registers taan control registers 0, 1 (taanctl0, taanctl1) taam i/o control registers 0 to 2 (taamioc0 to taamioc2) taan option register 0 (taanopt0) notes 1. v850e/ig3 only 2. not provided for tmp0 and tmp1 3. tia20, tia30, and tia40 pins func tion as capture trigger input signal, external event count input signal, and external trigger input signal, and function alter nately (alternate-function) as timer output pins (toa20, toa30, toa40). tia21, tia31, and tia41 pins f unction alternately as capture trigger input signal and timer output pins (toa21, toa31, toa41). remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 193 figure 6-1. taa0 block diagram selector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 internal bus internal bus taa0cnt taa0ccr0 ccr1 buffer register taa0ccr1 16-bit counter ccr0 buffer register clear intta0ov controller intta0cc0 intta0cc1 remark f xx : peripheral clock
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 194 figure 6-2. taa1 block diagram selector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 internal bus internal bus taa1cnt taa1ccr0 ccr1 buffer register taa1ccr1 16-bit counter ccr0 buffer register clear intta1ov controller intta1cc0 intta1cc1 remark f xx : peripheral clock
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 195 figure 6-3. taa2 block diagram toa2off edge detector selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 internal bus internal bus taa2cnt taa2ccr0 ccr1 buffer register taa2ccr1 tia21 tia20 16-bit counter ccr0 buffer register clear intta2ov output controller intta2cc0 toa20 toa21 intta2cc1 selector selector sampling clock f xx edge detection/ noise eliminator edge detection/ noise eliminator f xx /4 remarks 1. f xx : peripheral clock 2. for the toa2off pin, see 10.3 (6) high-impedance output c ontrol registers 00, 01, 10, 11, 20, 21, 30, 31 (hzayctl0, hzayctl1) . 3. for the noise eliminator, see 4.6 noise eliminator .
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 196 figure 6-4. taa3 block diagram toa3off note edge detector selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 internal bus internal bus taa3cnt taa3ccr0 ccr1 buffer register taa3ccr1 tia31 note tia30 note 16-bit counter ccr0 buffer register clear intta3ov output controller intta3cc0 toa30 note toa31 note intta3cc1 selector selector sampling clock f xx edge detection/ noise eliminator edge detection/ noise eliminator f xx /4 note v850e/ig3 only remarks 1. f xx : peripheral clock 2. for the toa3off pin, see 10.3 (6) high-impedance output c ontrol registers 00, 01, 10, 11, 20, 21, 30, 31 (hzayctl0, hzayctl1) . 3. for the noise eliminator, see 4.6 noise eliminator .
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 197 figure 6-5. taa4 block diagram selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 internal bus internal bus taa4cnt taa4ccr0 ccr1 buffer register taa4ccr1 tia41 tia40 16-bit counter ccr0 buffer register clear intta4ov output controller intta4cc0 toa40 toa41 intta4cc1 selector selector sampling clock f xx edge detection/ noise eliminator edge detection/ noise eliminator f xx /4 remarks 1. f xx : peripheral clock 2. for the noise eliminator, see 4.6 noise eliminator .
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 198 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the taancnt register. when the taanctl0.taance bit = 0, t he value of the 16-bit counter is ffffh. if the taancnt register is read at this time, 0000h is read. reset sets the taance bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the taanccr0 register is used as a compare regist er, the value written to the taanccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttancc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, and the taanccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the taanccr1 register is used as a compare regist er, the value written to the taanccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttancc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, and the taanccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tia20, tia21, tia30 (v850e/ig3 only), tia31 (v850e/ig3 only), tia40, and tia41 pins. no edge, rising edge, fa lling edge, or both the rising and falling edges can be selected as the valid edge by using the taamioc1 and taamioc2 registers. (5) output controller this circuit controls the output of the toa20, toa21, toa30 (v85 0e/ig3 only), toa31 (v850e/ig3 only), toa40, and toa41 pins. the output controller is controlled by the taamioc0 registers. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 199 6.4 registers (1) taan control register 0 (taanctl0) the taanctl0 register is an 8-bit register that controls the operation of taan. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the taanctl0 register by software. after reset: 00h r/w address: taa0ctl0 fffff660h, taa1ctl0 fffff680h, taa2ctl0 fffff6a0h, taa3ctl0 fffffb00h, taa4ctl0 fffffb20h taance taan operation disabled (taan reset asynchronously note ) taan operation enabled. taan operation start taance 0 1 taan operation control taanctl0 (n = 0 to 4) 0000 taancks2 taancks1 taancks0 654321 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 taancks2 0 0 0 0 1 1 1 1 internal count clock selection taa0, taa1 taa2 to taa4 taancks1 0 0 1 1 0 0 1 1 taancks0 0 1 0 1 0 1 0 1 <7> note the taanopt0.taanovf bit and the 16-bit counter ar e reset simultaneously. moreover, timer outputs (toa20, toa21, toa30 (v850e/ig3 only), toa31 (v850e/ig3 only), toa40, toa41 pins) are reset to the taamioc0 register set status at the same time as the 16-bit counter is reset (v850e/if3: m = 2, 4, v850e/ig3: m = 2 to 4). cautions 1. set the taancks2 to taan cks0 bits when the taance bit = 0. when the value of the taance bit is change d from 0 to 1, the taan cks2 to taancks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 200 (2) taan control register 1 (taanctl1) the taanctl1 register is an 8-bit regist er that controls the taan operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) after reset: 00h r/w address: taa0ctl1 fffff661h, taa1ctl1 fffff681h, taa2ctl1 fffff6a1h, taa3ctl1 fffffb01h, taa4ctl1 fffffb21h taaasye note 1 taanctl1 taamest note 2 taameee note 2 0 0 taanmd2 taanmd1 taanmd0 654321 7 0 taamest note 2 0 1 software trigger control the read value of the taamest bit is always 0. ? generates a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the taamest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the taamest bit as the trigger. taaa single mode tuning operation mode (see 10.4.5 ) taaasye note 1 0 1 operation mode selection taaa can be used only as an a/d conversion start trigger factor of a/d converters 0 and 1 during the tuning operation. in the tuning operation mode, this bit always operates in synchronization with taba. v850e/if3 n = 0 to 4 m = 2, 4 a = 0, 1 v850e/ig3 n = 0 to 4 m = 2 to 4 a = 0, 1 notes 1. this bit can be set only in taa0 and taa1. be su re to set bit 7 of taa2 to taa4 to ?0?. for details of tuning operation mode, see chapter 10 motor control function . 2. in the v850e/if3, this bit can be set only in taa2 and taa4. be sure to set bits 5 and 6 of taa0, taa1, and taa3 to ?0?. in the v850e/ig3, this bit can be set only in taa2 to taa4. be sure to set bits 5 and 6 of taa0 and taa1 to ?0?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 201 (2/2) disable operation with external event count input (tiam0 pin). (perform counting with the count clock selected by the taamctl0.taamcks0 to taamctl0.taamcks2 bits.) enable operation note 2 with external event count input (tiam0 pin). (perform counting at every valid edge of the external event count input signal (tiam0 pin).) taameee note 1 0 1 count clock selection the taameee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. interval timer mode external event count mode external trigger pulse mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited taanmd2 0 0 0 0 1 1 1 1 timer mode selection taanmd1 0 0 1 1 0 0 1 1 taanmd0 0 1 0 1 0 1 0 1 notes 1. with the v850e/if3, this bit can be set only in taa2 and taa4. be sure to set bits 5 and 6 of taa0, taa1, and taa3 to ?0?. with the v850e/ig3, this bit can be set only in taa2 to taa4. be sure to set bits 5 and 6 of taa0 and taa1 to ?0?. 2. set the valid edge selection of capture trigger input (tiam0 pin) and external trigger input (tiam0 pin) to ?no edge detection?. cautions 1. the taamest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. external event count input is selected in th e external event count mode regardless of the value of the taameee bit. 3. set the taaasye, taameee, and taanmd2 to taanmd0 bits when the taanctl0.taance bit = 0. (the same value can be written when the taance bit = 1.) the operation is not guaranteed when rewriting is performed with the taance bit = 1. if rewriting was mistakenly performed, clear the taance bi t to 0 and then set the bits again. 4. be sure to set bits 3 and 4 to ?0?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 202 (3) taam i/o control register 0 (taamioc0) the taamioc0 register is an 8-bit register that controls the timer output (toam0, toam1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) 0 taamol1 0 1 toam1 pin output level setting note 2 toam1 pin starts output at high level. toam1 pin starts output at low level. taamioc0 0 0 0 taamol1 taamoe1 taamol0 taamoe0 6543<2>1 after reset: 00h r/w address: taa2ioc0 fffff6a2h, taa3ioc0 fffffb02h note 1 taa4ioc0 fffffb22h taamoe1 0 1 toam1 pin output setting timer output prohibited ? low level is output from the toam1 pin when the taamol1 bit = 0. ? high level is output from the toam1 pin when the taamol1 bit = 1. timer output enabled (a pulse is output from the toam1 pin.) taamol0 0 1 toam0 pin output level setting note 2 toam0 pin starts output at high level. toam0 pin starts output at low level. taamoe0 0 1 toam0 pin output setting timer output prohibited ? low level is output from the toam0 pin when the taamol0 bit = 0. ? high level is output from the toam0 pin when the taamol0 bit = 1. timer output enabled (a pulse is output from the toam0 pin.) 7 <0> v850e/if3 m = 2, 4 a = 0, 1 v850e/ig3 m = 2 to 4 a = 0, 1 notes 1. v850e/ig3 only 2. the output level of the timer output pins (toam0 and toam1) specified by the taamola bit is shown below. taamce bit toama pin output 16-bit counter taamce bit toama pin output 16-bit counter ? when taamola bit = 0 ? when taamola bit = 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 203 (2/2) cautions 1. if the setting of the taamioc0 register is changed when toam0 and toam1 are set in the output mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. rewrite the taamol1, taamoe1, taamol0, and taamoe0 bits when the taamctl0.taamce bit = 0. (the same value can be written when the taamce bit = 1.) if rewriting was mistakenly performed, clear the t aamce bit to 0 and then set the bits again. 3. even if the taamol0 or taamol1 bit is manipulated when the taamce, taamoe0, and taamoe1 bits are 0, the output level of the toam0 and toam1 pins changes.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 204 (4) taam i/o control register 1 (taamioc1) the taamioc1 register is an 8-bit re gister that controls the valid edge for the capture trigger input signals (tiam0, tiam1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taamis3 0 0 1 1 taamis2 0 1 0 1 capture trigger input signal (tiam1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges taamioc1 0 0 0 taamis3 taamis2 taamis1 taamis0 654321 after reset: 00h r/w address: taa2ioc1 fffff6a3h, taa3ioc1 fffffb03h note , taa4ioc1 fffffb23h taamis1 0 0 1 1 taamis0 0 1 0 1 capture trigger input signal (tiam0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 v850e/if3 m = 2, 4 v850e/ig3 m = 2 to 4 note v850e/ig3 only cautions 1. rewrite the taamis3 to taamis0 bits when the taamctl0.taamce bit = 0. (the same value can be written when the ta amce bit = 1.) if rewriting was mistakenly performed, clear the taamce bit to 0 and then set the bits again. 2. the taamis3 to taamis0 bits are valid onl y in the free-running time r mode (only when the taamopt0.taamccs1 and taamopt0.taamcc s0 bits = 11) and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 205 (5) taam i/o control register 2 (taamioc2) the taamioc2 register is an 8-bit register that controls the valid edge for the external event count input signal (tiam0 pin) and external trigger input signal (tiam0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taamees1 0 0 1 1 taamees0 0 1 0 1 external event count input signal (tiam0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges taamioc2 0 0 0 taamees1 taamees0 taamets1 taamets0 654321 after reset: 00h r/w address: taa2ioc2 fffff6a4h, taa3ioc2 fffffb04h note , taa4ioc2 fffffb24h taamets1 0 0 1 1 taamets0 0 1 0 1 external trigger input signal (tiam0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 v850e/if3 m = 2, 4 v850e/ig3 m = 2 to 4 note v850e/ig3 only cautions 1. rewrite the taamees1, taamees0, taamets1, and taamets0 bits when the taamctl0.taamce bit = 0. (the same value can be written when the taamce bit = 1.) if rewriting was mistakenly performed, clear the taam ce bit to 0 and then set the bits again. 2. the taamees1 and taamees0 bits are valid only when the taamctl1.taameee bit = 1 or when the external event count mode (the taamctl1.taammd2 to taamctl1.taammd0 bits = 001) has been set. 3. the taamets1 and taamets0 bits are valid only in the external trigger pulse mode or one-shot pulse output mode.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 206 (6) taan option register 0 (taanopt0) the taanopt0 register is an 8-bit register that sets the capture/compare operation and detects overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taamccs1 note 0 1 taamccr1 register capture/compare selection the taamccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by taamctl0.taamce bit = 0) 0 taamccs1 note taamccs0 note 0 0 0 taanovf 654321 after reset: 00h r/w address: taamccs0 note 0 1 taamccr0 register capture/compare selection the taamccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by taamctl0.taamce bit = 0) taanovf set (1) reset (0) taan overflow detection flag ? the taanovf bit is set to 1 when the 16-bit counter value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttanov) is generated at the same time that the taanovf bit is set to 1. the inttanov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the taanovf bit is not cleared to 0 even when the taanovf bit or the taanopt0 register are read when the taanovf bit = 1. ? before clearing the taanovf bit to 0 after generation of the inttanov signal, be sure to confirm (by reading) that the taanovf bit is set to 1. ? the taanovf bit can be both read and written, but the taanovf bit cannot be set to 1 by software. writing 1 has no effect on the operation of taan. overflow occurred 0 is written to taanovf bit or taanctl0.taance bit = 0 7 <0> taanopt0 v850e/if3 n = 0 to 4 m = 2, 4 v850e/ig3 n = 0 to 4 m = 2 to 4 taa0opt0 fffff665h, taa1opt0 fffff685h, taa2opt0 fffff6a5h, taa3opt0 fffffb05h, taa4opt0 fffffb25h note with the v850e/if3, this bit can be set only in taa2 and taa4. be sure to set bits 4 and 5 of taa0, taa1, and taa3 to ?0?. with the v850e/ig3, this bit can be set only in taa2 to taa4. be sure to set bits 4 and 5 of taa0 and taa1 to ?0?. cautions 1. rewrite the taamccs1 and taamccs0 bi ts when the taamce bit = 0. (the same value can be written when the taamce bit = 1.) if rewriting was mistakenly performed, clear the taamce bit to 0 and then set the bits again. 2. be sure to set bits 1 to 3, 6, and 7 to ?0?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 207 (7) taan capture/compare register 0 (taanccr0) the taamccr0 register is a 16-bit register that can be used as a capture regist er or compare register depending on the mode. the taakccr0 register is a 16- bit register that can only be used as a compare register. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the taamopt0.taamccs0 bit. in the pulse width measurement mode, the taamccr0 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the taanccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. remark v850e/if3: n = 0 to 4, m = 2, 4, k = 0, 1, 3 v850e/ig3: n = 0 to 4, m = 2 to 4, k = 0, 1 taanccr0 (n = 0 to 4) 12 10 8 6 4 2 after reset: 0000h r/w address: taa0ccr0 fffff666h, taa1ccr0 fffff686h, taa2ccr0 fffff6a6h, taa3ccr0 fffffb06h, taa4ccr0 fffffb26h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 208 (a) function as compare register the taanccr0 register can be rewritten even when the taanctl0.taance bit = 1. the set value of the taanccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttancc0) is generated. if toam0 pin output is enabled at this time , the output of the toam0 pin is inverted. when the taanccr0 register is used as a cycle regist er in the interval timer mode or the taamccr0 register is used as a cycle register in external even t count mode, external trigger pulse output mode, one- shot pulse output mode, or pwm output mode, the value of the 16-bit c ounter is cleared (0000h) if its count value matches the value of the ccr0 buffer register. the compare register is not cleared by setting the taanctl0.taance bit to 0. (b) function as capture register when the taamccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the taamccr0 register if the valid edge of the capture trigger input pin (tiam0 pin) is detected. in the pulse-width m easurement mode, the count value of the 16-bit counter is stored in the taamccr0 register and the 16-bit co unter is cleared (0000h) if the valid edge of the capture trigger input pin (tiam0 pin) is detected. even if the capture operation and reading the taam ccr0 register conflict, the correct value of the taamccr0 register can be read. the capture register is cleared by setting the taamctl0.taamce bit to 0. remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter note 1 compare register anytime write external trigger pulse output note 1 compare register batch write note 2 one-shot pulse output note 1 compare register anytime write pwm output note 1 compare register batch write note 2 free-running timer capture/compare register anytime write pulse width measurement note 1 capture register none notes 1. with the v850e/if3, this mode is only for taa2 an d taa4. with the v850e/ig3, this mode is only for taa2 to taa4. 2. writing to the taamccr1 register is the trigger. remark for anytime write and batch write, see 6.6 (2) anytime write and batch write .
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 209 (8) taan capture/compare register 1 (taanccr1) the taamccr1 register is a 16-bit register that can be used as a capture regist er or compare register depending on the mode. the taakccr1 register is a 16- bit register that can only be used as a compare register. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the taamopt0.taamccs1 bit. in the pulse width measurement mode, the taamccr1 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the taanccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. remark v850e/if3: n = 0 to 4, m = 2, 4, k = 0, 1, 3 v850e/ig3: n = 0 to 4, m = 2 to 4, k = 0, 1 taanccr1 (n = 0 to 4) 12 10 8 6 4 2 after reset: 0000h r/w address: taa0ccr1 fffff668h, taa1ccr1 fffff688h, taa2ccr1 fffff6a8h, taa3ccr1 fffffb08h, taa4ccr1 fffffb28h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 210 (a) function as compare register the taanccr1 register can be rewritten even when the taanctl0.taance bit = 1. the set value of the taanccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttancc1) is generated. if toam1 pin output is enabled at this time , the output of the toam1 pin is inverted. the compare register is not cleared by setting the taanctl0.taance bit to 0. (b) function as capture register when the taamccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the taamccr1 register if the valid edge of the capture trigger input pin (tiam1 pin) is detected. in the pulse-width m easurement mode, the count value of the 16-bit counter is stored in the taamccr1 register and the 16-bit co unter is cleared (0000h) if the valid edge of the capture trigger input pin (tiam1 pin) is detected. even if the capture operation and reading the taam ccr1 register conflict, the correct value of the taamccr1 register can be read. the capture register is cleared by setting the taamctl0.taamce bit to 0. remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter note 1 compare register anytime write external trigger pulse output note 1 compare register batch write note 2 one-shot pulse output note 1 compare register anytime write pwm output note 1 compare register batch write note 2 free-running timer capture/compare register anytime write pulse width measurement note 1 capture register none notes 1. in the v850e/if3, this mode is only for taa2 an d taa4. in the v850e/ig3 , this mode is only for taa2 to taa4. 2. writing to the taamccr1 register is the trigger. remark for anytime write and batch write, see 6.6 (2) anytime write and batch write .
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 211 (9) taan counter read buffer register (taancnt) the taancnt register is a read buffer register t hat can read the count va lue of the 16-bit counter. if this register is read when the taanctl0.taance bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the taancnt register is cleared to 0000h when the taance bit = 0. if the taancnt register is read at this time, the value of the 16-bit c ounter (ffffh) is not read, but 0000h is read. the value of the taancnt register is cleared to 0000 h after reset, and the taance bit is cleared to 0. taancnt (n = 0 to 4) 12 10 8 6 4 2 after reset: 0000h r address: taa0cnt fffff66ah, taa1cnt fffff68ah, taa2cnt fffff6aah, taa3cnt fffffb0ah, taa4cnt fffffb2ah 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 212 6.5 timer output operations the following table shows the operations and output levels of the toam0 and toam1 pins. table 6-6. timer output control in each mode operation mode toam1 pin toam0 pin interval timer mode pwm output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output pwm output free-running timer mode pwm output (only when compare function is used) pulse width measurement mode none remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 table 6-7. truth table of toam0 and toam1 pins under control of timer output control bits taamioc0.taamola bit taamioc0.taamoea bit taamctl0.taamce bit level of toama pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 213 6.6 operation the functions of taan that can be achieved differ from one channel to another. the functions of each channel are shown below. table 6-8. taa0 and taa1 specifications in each mode operation software trigger bit exte rnal trigger input capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode none external trigger pulse output mode none one-shot pulse output mode none pwm output mode none free-running timer mode invalid invalid compare only anytime write pulse width measurement mode none remarks 1. taaa does not have timer input pins (tiaa0, tia a1) and timer output pins (toaa0, toaa1). it has interrupt request signals (inttaacc0, inttaacc1) on a match between the value of the 16-bit counter and the values of the taaaccr0 and taaaccr1 registers. 2. taaa has a function to execute tuning with taba. for details, see chapter 10 motor control function . 3. a = 0, 1 table 6-9. taa2 to taa4 specifications in each mode operation taamctl1.taamest bit (software trigger bit) tiam0 pin (external trigger input) capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switchable note 3 anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. when using the external event count mode, set the tiam0 pin capture trigger input valid edge selection to ?no edge detection?. (clear the taamioc1. taamis1 and taamioc1.taamis0 bits to 00.) 2. when using the external trigger pulse output mode , one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the taamctl1.taameee bit to 0). 3. in taa3 of the v850e/if3, this setting is compare only. remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 214 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 (a) counter start operation ? in external event count mode when the taamctl0.taamce bit is set from 0 to 1, the 16-bit counter is set to 0000h. after that, it counts up to 0001h, 0002h, 0003h, ? each time the valid edge of external event count input (tiam0) is detected. ? in modes other than the above starts counting from the default value ffffh. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and is cleared, and when its value is c aptured and cleared. the counting op eration from ffffh to 0000h that takes place immediately after the counter has start ed counting or when the counter overflows is not a clearing operation. therefore, the inttancc0 and inttancc1 interrupt signals are not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running mode or pulse width measurement mode. if the counter overflows, the taanopt0.taanovf bit is set to 1 and an interrupt request signal (inttanov) is generated. note that the inttanov signal is not generated under the following conditions. ? immediately after a counti ng operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleare d in the pulse width measuremen t mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (inttanov) has been generated, be sure to check that the overflow flag (taanovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of taan can be re ad by using the taancnt register during the count operation. when the taanctl0.taance bit = 1, the va lue of the 16-bit counter can be read by reading the taancnt register. when the taanctl0.taance bit = 0, the 16-bit counter is ffffh and the taancnt register is 0000h.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 215 (e) interrupt operation taan generates the following three types of interrupt request signals. ? inttancc0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the taanccr0 register. ? inttancc1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the taanccr1 register. ? inttanov interrupt: this signal functi ons as an overflow interrupt request signal.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 216 (2) anytime write and batch write the taanccr0 and taanccr1 registers in taan can be rewritten during timer operation (taanctl0.taance bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the taanccr0 and taanccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. remark n = 0 to 4 figure 6-6. flowchart of basic operation for anytime write start initial settings ? set values to taanccra register ? timer operation enable (taance bit = 1) transfer values of taanccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttancc1 signal output taanccra register rewrite transfer to ccra buffer register inttancc0 signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 4 a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 217 figure 6-7. timing of anytime write d 01 d 01 d 01 d 01 0000h taance bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter taanccr0 register taanccr1 register inttancc0 signal inttancc1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : set values of the taanccr0 register d 11 , d 12 : set values of the taanccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 218 (b) batch write in this mode, data is transferred all at once fr om the taamccr0 and taamccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the taamccr1 register. whether to enable or disable the ne xt transfer timing is controlled by writing or not writing to the taamccr1 register. in order for the set value when the taamccr0 an d taamccr1 registers are rewritten to become the 16- bit counter comparison value (in other words, in order for this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite t he taamccr0 register and then write to the taamccr1 register before the 16-bit counter value and the ccr0 buff er register value match. therefore, the values of the taamccr0 and taamccr1 registers are transferre d to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. thus even when wishing only to rewrite the value of the taamccr0 register, also write the same value (same as preset value of the taamccr1 regi ster) to the taamccr1 register. remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 219 figure 6-8. flowchart of basic operation for batch write start initial settings ? set values to taamccra register ? timer operation enable (taamce bit = 1) transfer values of taamccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of taamccra register to ccra buffer register inttamcc1 signal output taamccr0 register rewrite taamccr1 register rewrite inttamcc0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the taamccr1 register incl udes enabling of batch write. thus, rewrite the taamccr1 register after rewriting the taamccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 220 figure 6-9. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 taamce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter taamccr0 register taamccr1 register inttamcc0 signal inttamcc1 signal toam1 pin output toam0 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the taamccr1 register was not rewritten, d 03 is not transferred. 2. because the taamccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between t he value of the 16-bit counter and the value of the taamccr0 register (d 01 ). 3. because the taamccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between t he value of the 16-bit counter and the value of the taamccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : set values of taamccr0 register d 11 , d 12 : set values of taamccr1 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. 3. v850e/if3: m = 2, 4 v850e/ig3: m= 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 221 6.6.1 interval timer mode (t aanmd2 to taanmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttancc0) is generated at the interval set by the taanccr0 register if the taanctl0.taance bit is set to 1. a pwm waveform with a duty factor of 50% whose half cycle is equal to the interval c an be output from the toam0 pin. the taanccr1 register is not used in the interval timer mo de. however, the set value of the taanccr1 register is transferred to the ccr1 buffer register, and when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttancc1) is generated. in addition, a pwm waveform with a duty factor of 50%, which is inverted when the inttam cc1 signal is generated, c an be output from the toam1 pin. the value of the taanccr0 and taanccr1 registers ca n be rewritten even while the timer is operating. figure 6-10. configuration of interval timer 16-bit counter output controller ccr0 buffer register taance bit taanccr0 register count clock selection clear match signal toam0 pin inttancc0 signal remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 figure 6-11. basic timing of oper ation in interval timer mode ffffh 16-bit counter 0000h taance bit taanccr0 register toam0 pin output inttancc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 222 when the taance bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter star ts counting. at this time, the output of the toam0 pin is inverted. additionally, the set value of the taanccr0 regist er is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the toam0 pin is in verted, and a compare match interrupt request signal (inttancc0) is generated. the interval can be calculated by the following expression. interval = (set value of taanccr0 register + 1) count clock cycle remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 figure 6-12. register setting for in terval timer mode operation (1/3) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 0 0 0/1 note 00 taanctl1 0, 0, 0: interval timer mode 000 taanmd2 taanmd1 taanmd0 taameee taamest taaasye 0: operate on count clock selected by taamcks0 to taamcks2 bits 1: count with external event count input signal note the taameee bit can be set to 1 only when timer output (toam1) is used. however, set the taamccr0 and taamccr1 registers to the same value.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 223 figure 6-12. register setting for in terval timer mode operation (2/3) (c) taam i/o control register 0 (taamioc0) 0 0 0 0 0/1 taamioc0 0: disable toam0 pin output 1: enable toam0 pin output setting of toam0 pin output level before count operation 0: low level 1: high level 0: disable toam1 pin output 1: enable toam1 pin output setting of toam1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 taamoe1 taamol0 taamoe0 taamol1 (d) taam i/o control register 2 (taamioc2) 0 0 0 0 0/1 note taamioc2 select valid edge of external event count input (tiam0 pin). 0/1 note 00 taamees0 taamets1 taamets0 taamees1 note the taamees1 and taamees0 bits can be set only when timer output (toam1) is used. however, set the taamccr0 and taamccr1 registers to the same value. (e) taan counter read buffer register (taancnt) by reading the taancnt regist er, the count value of the 16-bit counter can be read. (f) taan capture/compare register 0 (taanccr0) if the taanccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 224 figure 6-12. register setting for in terval timer mode operation (3/3) (g) taan capture/compare register 1 (taanccr1) the taanccr1 register is not used in the interval timer mode. however, the set value of the taanccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, the toam1 pi n output is inverted and a compare match interrupt request signal (inttancc1) is generated. by setting this register to the same value as the value set in the taanccr0 register, a pwm waveform with a duty factor of 50% can be output from the toam1 pin. when the taanccr1 register is not used, it is recommended to set the value to ffffh. also mask the register by the interrupt mask flag (taanccic1.taanccmk1). remarks 1. taam i/o control register 1 (taamioc1) and taan option register 0 (taanopt0) are not used in the interval timer mode. 2. v850e/if3: n = 0 to 4, m = 2, 4, a = 0, 1 v850e/ig3: n = 0 to 4, m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 225 (1) interval timer mode operation flow figure 6-13. software processing flow in interval timer mode (1/2) taance bit = 1 register initial setting taanctl0 register (taancks0 to taancks2 bits) taanctl1 register, taamioc0 register, taamioc2 register note , taanccr0 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). start <1> count operation start flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h taance bit taanccr0 register toam0 pin output inttancc0 signal note the taamees1 and taamees0 bits can be set only when timer output (toam1) is used. however, set the taamccr0 and taamccr1 registers to the same value. remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 226 figure 6-13. software processing flow in interval timer mode (2/2) taance bit = 0 the counter is initialized and counting is stopped by clearing the taance bit to 0. the output level of the toam0 pin is as specified by the taamioc0 register. stop <2> count operation stop flow remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 (2) interval timer mode operation timing (a) operation if taanccr0 register is set to 0000h if the taanccr0 register is set to 0000h, the inttancc0 signal is generated at each count clock, and the output of the toam0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter taance bit taanccr0 register toam0 pin output inttancc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 227 (b) operation if taanccr0 register is set to ffffh if the taanccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up ti ming. the inttancc0 signal is generated and the output of the toam0 pin is inverted. at this time, an overflow interrupt request signal (inttanov) is not generated, nor is the overflow flag (taanopt0.taanovf bit) set to 1. ffffh 16-bit counter 0000h taance bit taanccr0 register toam0 pin output inttancc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 228 (c) notes on rewriting taanccr0 register if the value of the taanccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. ffffh 16-bit counter 0000h taance bit taanccr0 register taamol0 bit toam0 pin output inttancc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4 if the value of the taanccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the taanccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttancc0 signal is generated and the output of the toam0 pin is inverted. therefore, the inttancc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but ma y be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 229 (d) operation of taanccr1 register figure 6-14. configuration of taanccr1 register ccr0 buffer register taanccr0 register taanccr1 register ccr1 buffer register toam0 pin inttancc0 signal toam1 pin inttancc1 signal 16-bit counter output controller taance bit count clock selection clear match signal output controller match signal remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 230 when the taanccr1 register is set to the same value as the taancc r0 register, the inttancc0 signal is generated at the same timing as the inttancc1 sig nal and the toam1 pin output is inverted. in other words, a pwm waveform with a duty factor of 50% can be output from the toam1 pin. the following shows the operation when the taanccr1 regi ster is set to other than the value set in the taanccr0 register. if the set value of the taanccr1 register is less than the set value of the taanccr0 register, the inttancc1 signal is generated once per cycle. at the same time, the output of the toam1 pin is inverted. the toam1 pin outputs a pwm waveform with a duty fa ctor of 50% after outputting a short-width pulse. figure 6-15. timing chart when d 01 d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register toam0 pin output inttancc0 signal taanccr1 register toam1 pin output inttancc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 231 if the set value of the taanccr1 register is greater than the set value of the taanccr0 register, the count value of the 16-bit counter does not match the valu e of the taanccr1 register. consequently, the inttancc1 signal is not generated, nor is the output of the toam1 pin changed. when the taanccr1 register is not used, it is recommended to set its value to ffffh. figure 6-16. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register toam0 pin output inttancc0 signal taanccr1 register toam1 pin output inttancc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 232 (3) operation by external event count input (tiam0) (a) operation to count the 16-bit counter at the va lid edge of the external event count input (tiam0) in the interval timer mode, the 16-bit counter is cleared from ffffh to 0000h by the valid edge of the external event count after the taamce bit is set from 0 to 1. when 0001h is set to both the taamccr0 and taamccr1 registers, the toam1 pin output is inverted each time the 16-bit counter counts twice. the taamctl1.taameee bit can be set to 1 in the in terval timer mode only when the timer output (toam1) is used with the external event count input. taamce bit taamccr0 register taamccr1 register toam1 pin output 16-bit counter ffffh 0000h external event count input (tiam0 pin input) 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h number of external events: 2 number of external events: 2 number of external events: 2 2-count width 2-count width 2-count width remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 233 6.6.2 external event count mode (taammd2 to taammd0 bits = 001) this mode is valid only in taa2, taa3 (v850e/ig3 only), and taa4. in the external event count mode, the valid edge of t he external event count input (tiam0) is counted when the taamctl0.taamce bit is set to 1, and an interrupt reques t signal (inttamcc0) is generated each time the number of edges set by the taamccr0 register have been coun ted. the toam0 and toam1 pins cannot be used. when using the toam1 pin for external event count input, set t he taamctl1.taameee bit to 1 in the interval timer mode (see 6.6.1 (3) operation by external event count input (tiam0) ). the taamccr1 register is not used in the external event count mode. figure 6-17. configuration in external event count mode 16-bit counter ccr0 buffer register taamce bit taamccr0 register edge detector clear match signal inttamcc0 signal tiam0 pin (external event count input) remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 234 figure 6-18. basic timing in external event count mode ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal d 0 d 0 d 0 d 0 16-bit counter taamccr0 register inttamcc0 signal external event count input (tiam0 pin input) d 0 external event count (d 0 + 1) external event count (d 0 + 1) external event count (d 0 + 1) d 0 ? 1d 0 0000 0001 remarks 1. this figure shows the basic timing when the ri sing edge is specified as the valid edge of the external event count input. 2. v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 235 when the taamce bit is set to 1, t he value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the taamccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttamcc0) is generated. the inttamcc0 signal is generated each time the valid edge of the external event count input has been detected ?value set to taamccr0 register + 1? times. figure 6-19. register setting for operati on in external event count mode (1/2) (a) taam control register 0 (taamctl0) 0/1 0 0 0 0 taamctl0 0: stop counting 1: enable counting 000 taamcks2 taamcks1 taamcks0 taamce (b) taam control register 1 (taamctl1) 00000 taamctl1 0, 0, 1: external event count mode 001 taammd2 taammd1 taammd0 taameee taamest taaasye (c) taam i/o control register 2 (taamioc2) 0 0 0 0 0/1 taamioc2 select valid edge of external event count input (tiam0 pin) 0/1 0 0 taamees0 taamets1 taamets0 taamees1 (d) taam counter read bu ffer register (taamcnt) the count value of the 16-bit counter can be read by reading the taamcnt register. (e) taam capture/compare register 0 (taamccr0) if the taamccr0 register is set to d 0 , the count is cleared when the nu mber of external events has reached (d 0 + 1) and the compare match interrupt req uest signal (inttamcc0) is generated.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 236 figure 6-19. register setting for operati on in external event count mode (2/2) (f) taam capture/compare register 1 (taamccr1) the taamccr1 register is not used in the external event count mode. however, the set value of the taamccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttamcc1) is generated. when the taamccr1 register is not used, it is recommended to set the value to ffffh. also mask the register by the interrupt mask flag (taamccic1.taamccmk1). cautions 1. set the taamioc0 register to 00h. 2. when an external clock is used as the count clock, the external clock can be input only from the tiam0 pin. at this time, set the taamioc1.taamis1 and taamioc1 . taamis0 bits to 00 (capture trigger input ( tiam0 pin): no edge detection) remarks 1. taam i/o control register 1 (taamioc1) and taam option register 0 (taamopt0) are not used in the external event count mode. 2. v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 237 (1) external event count mode operation flow figure 6-20. software processing flow in external event count mode taamce bit = 1 taamce bit = 0 register initial setting taamctl1 register, taamioc2 register, taamccr0, taamccr1 registers initial setting of these registers is performed before setting the taamce bit to 1. the counter is initialized and counting is stopped by clearing the taamce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 238 (2) operation timing in external event count mode caution in the external event count mode, use of th e timer output (toam0, toam1) is disabled. if using timer output (toam1) with external event count input (tiam0), set the interval timer mode, and select the operation enabled by the ex ternal event count input for the count clock (taamctl1.taameee bit = 1) (see 6.6.1 (3) op eration by external event count input (tiam0)). (a) operation if taamccr0 register is set to 0000h when the taamccr0 register is set to 0000h, the 16 -bit counter is repeatedly cleared to 0000h and generates the inttamcc0 signal each time it has det ected the valid edge of the external event count signal and its value has matched t hat of the ccr0 buffer register. the value of the 16-bit counter is always 0000h. ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal 0000h the inttamcc0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 239 (b) operation if taamccr0 register is set to ffffh if the taamccr0 register is set to ffffh, the 16- bit counter counts up to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttamcc0 signal is generated. at this time, the taamopt0.taamovf bit is not set. ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal ffffh external event count: 10000h external event count: 10000h external event count: 10000h remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 240 (c) operation with taamccr0 register set to ffffh and taamccr1 register to 0000h when the taamccr0 register is set to ffffh, the 16- bit counter counts up to ffffh each time it has detected the valid edge of the exte rnal event count signal. the count er is then cleared to 0000h in synchronization with the next count-up timing and the inttamcc0 signal is generated. at this time, the taamopt0.taamovf bit is not set. if the taamccr1 register is set to 0000h, the inttamcc1 signal is generated when the 16-bit counter is cleared to 0000h. ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal ffffh 0000h remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 241 (d) notes on rewriting the taamccr0 register if the value of the taamccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the overflow may occur, st op counting once and then change the set value. ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1): (d 1 + 1) external event count (ng): (10000h + d 2 + 1) external event count (2): (d 2 + 1) remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 if the value of the taamccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transfe rred to the ccr0 buffer regi ster as soon as the taamccr0 register has been rewritten. consequently, the va lue that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttamcc0 signal is generated. therefore, the inttamcc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 242 (e) operation of taamccr1 register figure 6-21. configuration of taamccr1 register ccr0 buffer register taamce bit taamccr0 register 16-bit counter taamccr1 register ccr1 buffer register clear match signal match signal inttamcc0 signal inttamcc1 signal edge detector tiam0 pin (external event count input) remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 if the set value of the taamccr1 register is smaller than the set value of the taamccr0 register, the inttamcc1 signal is generated once per cycle. figure 6-22. timing chart when d 01 d 11 ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 243 if the set value of the taamccr1 register is greate r than the set value of the taamccr0 register, the inttamcc1 signal is not generated because the count va lue of the 16-bit counter and the value of the taamccr1 register do not match. when the taamccr1 register is not used, it is recommended to set its value to ffffh. figure 6-23. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 244 6.6.3 external trigger pulse output m ode (taammd2 to taammd0 bits = 010) this mode is valid only in taa2, taa3 (v850e/ig3 only), and taa4. in the external trigger pulse output mode, 16-bit timer/event counter aa waits for a trigger when the taamctl0.taamce bit is set to 1. when the valid edge of an external trigger input (tiam0) is detected, 16-bit timer/event counter aa starts counting, and outputs a pwm waveform from the toam1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a pwm waveform with a duty factor of 50% that has the set value of t he taamccr0 register + 1 as half its cycle can also be output from the toam0 pin. figure 6-24. configuration in external trigger pulse output mode ccr0 buffer register taamce bit taamccr0 register 16-bit counter taamccr1 register ccr1 buffer register clear match signal match signal inttamcc0 signal output controller (rs-ff) output controller toam1 pin inttamcc1 signal toam0 pin note count clock selection count start control edge detector software trigger generation tiam0 pin note (external trigger input) transfer transfer s r note because the external trigger input pin (tiam0) and timer output pin (toam0) share the same alternate-function pin, the two functi ons cannot be used at the same time. caution in the external trigger pulse output mode , select the internal clock as the count clock (by clearing the taamctl1.taameee bit to 0). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 245 figure 6-25. basic timing in exte rnal trigger pulse output mode d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) toam0 pin output (only when software trigger is used) wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter aa waits for a trigger when the taamce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and outputs a pwm waveform from the toam1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of the toam0 pin is inverted. the toam1 pin ou tputs a high-level regar dless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of taamccr1 register) count clock cycle cycle = (set value of taamccr0 register + 1) count clock cycle duty factor = (set value of taamccr1 regist er)/(set value of taamccr0 register + 1) the compare match interrupt request signal inttamcc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttamcc1 is ge nerated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the taamccra register is transferred to the ccra buffer register when the count value of the 16- bit counter matches the value of the ccra buffer r egister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input (tiam0), or setting the software trigger (taamctl1.taamest bit) to 1 is used as the trigger. remark v850e/if3: m = 2, 4, a = 0, 1, v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 246 figure 6-26. setting of registers in exte rnal trigger pulse output mode (1/2) (a) taam control register 0 (taamctl0) 0/1 0 0 0 0 taamctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 taamcks2 taamcks1 taamcks0 taamce (b) taam control register 1 (taamctl1) 0 0/1 0 0 0 taamctl1 0: operate on count clock selected by taamcks0 to taamcks2 bits generate software trigger when 1 is written 010 taammd2 taammd1 taammd0 taameee taamest 0, 1, 0: external trigger pulse output mode taaasye (c) taam i/o control register 0 (taamioc0) 0 0 0 0 0/1 taamioc0 0: disable toam0 pin output 1: enable toam0 pin output setting of toam0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable toam1 pin output 1: enable toam1 pin output setting of toam1 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note taamoe1 taamol0 taamoe0 taamol1 toam1 pin output 16-bit counter ? when taamol1 bit = 0 toam1 pin output 16-bit counter ? when taamol1 bit = 1 note clear this bit to 0 when the toam0 pin is not used in the external trigger pulse output mode.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 247 figure 6-26. setting of registers in exte rnal trigger pulse output mode (2/2) (d) taam i/o control register 2 (taamioc2) 00000 taamioc2 select valid edge of external trigger input (tiam0 pin) 0 0/1 0/1 taamees0 taamets1 taamets0 taamees1 (e) taam counter read bu ffer register (taamcnt) the value of the 16-bit counter can be read by reading the taamcnt register. (f) taam capture/compare registers 0 and 1 (taamccr0 and taamccr1) if d 0 is set to the taamccr0 register and d 1 to the taamccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. taam i/o control register 1 (taamioc1) and taam option register 0 (taamopt0) are not used in the external trigger pulse output mode. 2. v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 248 (1) operation flow in extern al trigger pulse output mode figure 6-27. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h taamce bit taamccr0 register ccr0 buffer register inttamcc0 signal taamccr1 register ccr1 buffer register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) toam0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 249 figure 6-27. software processing flow in ex ternal trigger pulse output mode (2/2) taamce bit = 1 setting of taamccr0 register register initial setting taamctl0 register (taamcks0 to taamcks2 bits) taamctl1 register, taamioc0 register, taamioc2 register, taamccr0 register, taamccr1 register initial setting of these registers is performed before setting the taamce bit to 1. the taamcks0 to taamcks2 bits can be set at the same time when counting is enabled (taamce bit = 1). trigger wait status. writing same value (same as preset value of the taamccr1 register) to the taamccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the taamccra register is transferred to the ccra buffer register. start setting of taamccr1 register <1> count operation start flow <2> taamccr0 and taamccr1 register setting change flow setting of taamccr0 register when the counter is cleared after setting, the value of the taamccra register is transferred to the ccra buffer register. setting of taamccr1 register <4> taamccr0, taamccr1 register setting change flow only writing of the taamccr1 register must be performed when only the set duty factor is changed. when the counter is cleared after setting, the value of the taamccra register is transferred to the ccra buffer register. setting of taamccr1 register <3> taamccr0, taamccr1 register setting change flow taamce bit = 0 counting is stopped. stop <5> count operation stop flow remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 250 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the taamccr1 register last. rewrite the taamccra register after writing the taamccr1 register after the inttamcc0 signal is detected. ffffh 16-bit counter 0000h taamce bit taamccr0 register ccr0 buffer register inttamcc0 signal taamccr1 register ccr1 buffer register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) toam0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 251 in order to transfer data from the taamccra register to the ccra buffer register, the taamccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the taamccr0 register and then set the active level width to the taamccr1 register. to change only the cycle of the pwm waveform, first set the cycl e to the taamccr0 register, and then write the same value (same as preset value of the taamccr1 register) to the taamccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the taamccr1 register has to be set. after data is written to the taamccr1 register, the va lue written to the taamccra register is transferred to the ccra buffer register in synchronization with cl earing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the taamccr0 or taamccr1 register again after writing the taamccr1 register once, do so after the inttamcc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the taamccra register to the ccra buffer register conflicts with writing the taamccra register. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 252 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the taamccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttamcc0 and inttamcc1 signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter taamce bit taamccr0 register taamccr1 register inttamcc0 signal inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 note note note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 to output a 100% waveform, set a value of (set va lue of taamccr0 register + 1) to the taamccr1 register. if the set value of the taamccr0 regi ster is ffffh, 100% output cannot be produced. d 0 l d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter taamce bit taamccr0 register taamccr1 register inttamcc0 signal inttamcc1 signal toam1 pin output d 0 ? 1d 0 ? 1 external trigger input (tiam0 pin input) note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 253 (c) conflict between trigger detection and match with ccr1 buffer register if the trigger is detected immediately after the intt amcc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he toam1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr1 buffer register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 if the trigger is detected immediately before the inttamcc1 signal is generated, the inttamcc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the toam1 pin remains active. consequently, the acti ve period of the pwm waveform is extended. 16-bit counter ccr1 buffer register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 254 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the intt amcc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toam1 pin is extended by time from generation of the inttamcc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttamcc0 signal toam1 pin output external trigger input (tiam0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 if the trigger is detected immediately before the inttamcc0 signal is generated, the inttamcc0 signal is not generated. the 16-bit counter is cleared to 00 00h, the toam1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttamcc0 signal toam1 pin output external trigger input (tiam0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 255 (e) generation timing of compare match interrupt request signal (inttamcc1) the timing of generation of the inttamcc1 signal in the external trigger pulse output mode differs from the timing of inttamcc1 signals in other mode; the inttamcc1 signal is generated when the count value of the 16-bit counter matches the value of the taamccr1 register. count clock 16-bit counter taamccr1 register toam1 pin output inttamcc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 usually, the inttamcc1 signal is generated in sync hronization with the next count-up, after the count value of the 16-bit counter matches the value of the taamccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the toam1 pin.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 256 6.6.4 one-shot pulse output mode (taammd2 to taammd0 bits = 011) this mode is valid only in taa2, taa3 (v850e/ig3 only), and taa4. in the one-shot pulse output mode, 16-bit timer/event co unter aa waits for a trigger when the taamctl0.taamce bit is set to 1. when the valid edge of an external trig ger input is detected, 16-bit timer/event counter aa starts counting, and outputs a one-shot pulse from the toam1 pin. instead of the external trigger input (tiam0), a software trigger can also be generated to output the pulse. when the software trigger is used, the toam0 pin outputs the ac tive level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 6-28. configuration in one-shot pulse output mode ccr0 buffer register taamce bit taamccr0 register 16-bit counter taamccr1 register ccr1 buffer register clear match signal match signal inttamcc0 signal output controller (rs-ff) output controller (rs-ff) toam1 pin inttamcc1 signal toam0 pin note count clock selection count start control edge detector software trigger generation tiam0 pin note (external trigger input) transfer transfer s r s r note because the external trigger input pin (tiam0) and timer output pin (toam0) share the same alternate-function pin, the two functi ons cannot be used at the same time. caution in the one-shot pulse output mode, select the internal clock as the count clock (by clearing the taamctl1.taameee bit to 0). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 257 figure 6-29. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) toam0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) when the taamce bit is set to 1, 16-bit timer/event counte r aa waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pulse from the toam1 pin. after the one-shot pulse is output, the 16-bit counter is cleared to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit counter star ts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of taamccr1 register) count clock cycle active level width = (set value of taamccr0 register ? set value of taamccr1 register + 1) count clock cycle the compare match interrupt request signal (inttamcc0) is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register . the compare match interrupt request signal (inttamcc1) is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger input (tiam0 pin) or setting the software trigger (taamctl1.taanest bit) to 1 is used as the trigger. remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 258 figure 6-30. setting of registers in one-shot pulse output mode (1/2) (a) taam control register 0 (taamctl0) 0/1 0 0 0 0 taamctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 taamcks2 taamcks1 taamcks0 taamce (b) taam control register 1 (taamctl1) 0 0/1 0 0 0 taamctl1 0: operate on count clock selected by taamcks0 to taamcks2 bits generate software trigger when 1 is written 011 taammd2 taammd1 taammd0 taameee taamest 0, 1, 1: one-shot pulse output mode taaasye (c) taam i/o control register 0 (taamioc0) 0 0 0 0 0/1 taamioc0 0: disable toam0 pin output 1: enable toam0 pin output setting of toam0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable toam1 pin output 1: enable toam1 pin output setting of toam1 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note taamoe1 taamol0 taamoe0 taamol1 toam1 pin output 16-bit counter ? when taamol1 bit = 0 toam1 pin output 16-bit counter ? when taamol1 bit = 1 note clear this bit to 0 when the toam0 pin is not used in the one-shot pulse output mode.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 259 figure 6-30. setting of registers in one-shot pulse output mode (2/2) (d) taam i/o control register 2 (taamioc2) 00000 taamioc2 select valid edge of external trigger input (tiam0 pin) 0 0/1 0/1 taamees0 taamets1 taamets0 taamees1 (e) taam counter read bu ffer register (taamcnt) the value of the 16-bit counter can be read by reading the taamcnt register. (f) taam capture/compare registers 0 and 1 (taamccr0 and taamccr1) if d 0 is set to the taamccr0 register and d 1 to the taamccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = d 1 count clock cycle caution one-shot pulses are not output even in the one-shot pulse output mode, if the value set in the taamccr1 register is greater th an that set in the taamccr0 register. remarks 1. taam i/o control register 1 (taamioc1) and taam option register 0 (taamopt0) are not used in the one-shot pulse output mode. 2. v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 260 (1) operation flow in one-shot pulse output mode figure 6-31. software processing flow in one-shot pulse output mode <1> <2> <3> start stop d 10 d 11 d 00 d 01 d 00 d 10 d 11 d 01 setting of taamccr0, taamccr1 registers <2> taamccr0, taamccr1 register setting change flow taamce bit = 1 taamce bit = 0 register initial setting taamctl0 register (taamcks0 to taamcks2 bits) taamctl1 register, taamioc0 register, taamioc2 register, taamccr0 register, taamccr1 register initial setting of these registers is performed before setting the taamce bit to 1. the taamcks0 to taamcks2 bits can be set at the same time when counting has been started (taamce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <3> count operation stop flow ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal toam0 pin output (only when software trigger used) taamccr1 register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) as rewriting the taamccra register immediately forwards to the ccra buffer register, rewriting immediately after the generation of the inttamcc0 signal is recommended. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 261 (2) operation timing in one-shot pulse output mode (a) note on rewriting taamccra register if the value of the taamccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 ffffh 16-bit counter 0000h taamce bit taamccr0 register inttamcc0 signal taamccr1 register inttamcc1 signal toam1 pin output external trigger input (tiam0 pin input) toam0 pin output (only when software trigger is used) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the taamccr0 register is rewritten from d 00 to d 01 and the taamccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the taamccr1 register is rewri tten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the taamccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttamcc1 signal and asserts the toam1 pin output. when the count value matches d 01 , the counter generates the inttamcc0 signal, deasserts the toam1 pin output, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 262 (b) generation timing of compare match interrupt request signal (inttamcc1) the generation timing of the inttamcc1 signal in the one-shot pulse output mode is different from inttamcc1 signals; the inttamcc1 signal is generat ed when the count value of the 16-bit counter matches the value of the taamccr1 register. count clock 16-bit counter taamccr1 register toam1 pin output inttamcc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 usually, the inttamcc1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the taamccr1 register. in the one-shot pulse output mode, however, it is gener ated one clock earlier. this is because the timing is changed to match the change timing of the toam1 pin.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 263 6.6.5 pwm output mode (taammd2 to taammd0 bits = 100) this mode is valid only in taa2, taa3 (v850e/ig3 only), and taa4. in the pwm output mode, a pwm waveform is output from the toam1 pin when the taamctl0.taamce bit is set to 1. in addition, a pwm waveform with a duty factor of 50% with the set value of the taamccr0 register + 1 as half its cycle is output from the toam0 pin. figure 6-32. configuration in pwm output mode ccr0 buffer register taamce bit taamccr0 register 16-bit counter taamccr1 register ccr1 buffer register clear match signal match signal inttamcc0 signal output controller (rs-ff) output controller toam1 pin inttamcc1 signal toam0 pin note transfer transfer s r count clock selection internal count clock tiam0 pin note (external event count input) edge detector note because the external event count input pin (tia m0) and timer output pin (toam0) share the same alternate-function pin, the two functi ons cannot be used at the same time. remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 264 figure 6-33. basic timing in pwm output mode ffffh 16-bit counter 0000h taamce bit taamccr0 register ccr0 buffer register inttamcc0 signal toam0 pin output taamccr1 register ccr1 buffer register inttamcc1 signal toam1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 - d 10 + 1) when the taamce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs a pwm waveform from the toam1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of taamccr1 register) count clock cycle cycle = (set value of taamccr0 register + 1) count clock cycle duty factor = (set value of taamccr1 regist er)/(set value of taamccr0 register + 1) the pwm waveform can be changed by rewriting the taam ccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttamcc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttamcc1 is ge nerated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the taamccra register is transferred to the ccra buffer register when the count value of the 16- bit counter matches the value of the ccra buffer r egister and the 16-bit counter is cleared to 0000h. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 265 figure 6-34. setting of registers in pwm output mode (1/2) (a) taam control register 0 (taamctl0) 0/1 0 0 0 0 taamctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 taamcks2 taamcks1 taamcks0 taamce note the setting is invalid when the taamctl1.taameee bit = 1. (b) taam control register 1 (taamctl1) 0 0 0/1 0 0 taamctl1 100 taammd2 taammd1 taammd0 taameee taamest 1, 0, 0: pwm output mode 0: operate on count clock selected by taamcks0 to taamcks2 bits 1: count with external event count input signal taaasye (c) taam i/o control register 0 (taamioc0) 0 0 0 0 0/1 taamioc0 0: disable toam0 pin output 1: enable toam0 pin output setting of toam0 pin output level before count operation 0: low level 1: high level 0: disable toam1 pin output 1: enable toam1 pin output setting of toam1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 note taamoe1 taamol0 taamoe0 taamol1 toam1 pin output 16-bit counter ? when taamol1 bit = 0 toam1 pin output 16-bit counter ? when taamol1 bit = 1 note clear this bit to 0 when the toam0 pin is not used in the pwm output mode.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 266 figure 6-34. register setting in pwm output mode (2/2) (d) taam i/o control register 2 (taamioc2) 0 0 0 0 0/1 taamioc2 select valid edge of external event count input (tiam0 pin). 0/1 0 0 taamees0 taamets1 taamets0 taamees1 (e) taam counter read bu ffer register (taamcnt) the value of the 16-bit counter can be read by reading the taamcnt register. (f) taam capture/compare registers 0 and 1 (taamccr0 and taamccr1) if d 0 is set to the taamccr0 register and d 1 to the taamccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. taam i/o control register 1 (taamioc1) and taam option register 0 (taamopt0) are not used in the pwm output mode. 2. v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 267 (1) operation flow in pwm output mode figure 6-35. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h taamce bit taamccr0 register ccr0 buffer register inttamcc0 signal toam0 pin output taamccr1 register ccr1 buffer register inttamcc1 signal toam1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 268 figure 6-35. software processing flow in pwm output mode (2/2) taamce bit = 1 setting of taamccr0 register register initial setting taamctl0 register (taamcks0 to taamcks2 bits) taamctl1 register, taamioc0 register, taamioc2 register, taamccr0 register, taamccr1 register initial setting of these registers is performed before setting the taamce bit to 1. the taamcks0 to taamcks2 bits can be set at the same time when counting is enabled (taamce bit = 1). writing same value (same as preset value of the taamccr1 register) to the taamccr1 register is necessary when only the set cycle is changed. when the counter is cleared after setting, the value of the taamccra register is transferred to the ccra buffer register. start setting of taamccr1 register <1> count operation start flow <2> taamccr0, taamccr1 register setting change flow (cycle only) setting of taamccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of taamccr1 register <4> taamccr0, taamccr1 register setting change flow (cycle and duty) only writing of the taamccr1 register must be performed when only the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of taamccr1 register <3> taamccr0, taamccr1 register setting change flow (duty only) taamce bit = 0 counting is stopped. stop <5> count operation stop flow remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 269 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the taamccr1 register last. rewrite the taamccra register after writing the taamccr1 register after the inttamcc0 signal is detected. ffffh 16-bit counter 0000h taamce bit taamccr0 register ccr0 buffer register taamccr1 register ccr1 buffer register toam1 pin output inttamcc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the taamccra register to the ccra buffer register, the taamccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the taamccr0 register and then set the active level width to the taamccr1 register. to change only the cycle of the pwm waveform, first set the cycl e to the taamccr0 register, and then write the same value (same as preset value of the taamccr1 register) to the taamccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the taamccr1 register has to be set. after data is written to the taamccr1 register, the va lue written to the taamccra register is transferred to the ccra buffer register in synchronization with cl earing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the taamccr0 or taamccr1 register again after writing the taamccr1 register once, do so after the inttamcc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the taamccra register to the ccra buffer register conflicts with writing the taamccra register. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 270 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the taamccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttamcc0 and inttamcc1 signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter taamce bit taamccr0 register taamccr1 register inttamcc0 signal inttamcc1 signal toam1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 l note note note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 to output a 100% waveform, set a value of (set va lue of taamccr0 register + 1) to the taamccr1 register. if the set value of the taamccr0 regi ster is ffffh, 100% output cannot be produced. d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 0000 ffff 0000 d 00 0000 0001 count clock 16-bit counter taamce bit taamccr0 register taamccr1 register inttamcc0 signal inttamcc1 signal toam1 pin output d 00 ? 1d 00 ? 1 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 271 (c) generation timing of compare match interrupt request signal (inttamcc1) the timing of generation of the inttamcc1 signal in the pwm output mode differs from the timing of inttamcc1 signals; the inttamcc1 signal is generat ed when the count value of the 16-bit counter matches the value of the taamccr1 register. count clock 16-bit counter taamccr1 register toam1 pin output inttamcc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 usually, the inttamcc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the taamccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the toam1 pin.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 272 6.6.6 free-running timer mode (taanmd2 to taanmd0 bits = 101) the compare function is valid for all of taa0 to taa4. the capture function is valid only for taa2, taa3 (v850e/ig3 only), and taa4. in the free-running timer mode, 16-bit timer/event coun ter aa starts counting when the taanctl0.taance bit is set to 1. at this time, the taamccr0 and taamccr1 registers can be used as com pare registers or capture registers, depending on the setting of the taamopt0.taamccs0 and taamopt0.taamccs1 bits. figure 6-36. configuration in free-running timer mode taamccr0 register (capture) taance bit taamccr1 register (capture) 16-bit counter taanccr1 register (compare) taanccr0 register (compare) output controller taamccs0, taamccs1 bits (capture/compare selection) toam0 pin note 1 output controller toam1 pin note 2 edge detector count clock selection edge detector edge detector tiam0 pin note 1 (external event count input/ capture trigger input) tiam1 pin note 2 (capture trigger input) internal count clock 0 1 0 1 inttanov signal inttancc1 signal inttancc0 signal notes 1. because the external event count input pin (tia m0), capture trigger input pin (tiam0), and timer output pin (toam0) share the same alternate-functi on pin, the two or more functions cannot be used at the same time. 2. because the capture trigger input pin (tiam1) and timer output pin (toam1) share the same alternate-function pin, the two functi ons cannot be used at the same time. remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 273 ? compare operation when the taance bit is set to 1, 16-bit timer/event co unter aa starts counting, an d the output signal of the toama pin is inverted. when the count value of the 16-bit counter later ma tches the set value of the taanccra register, a compare match interrupt request signal (int tancca) is generated, and the output signal of the toama pin is inverted. the 16-bit counter continues counting in synchronization with th e count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttanov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (taanopt0.taanovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by ex ecuting the clr instruction via software. the taanccra register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. figure 6-37. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h taance bit taanccr0 register inttancc0 signal toam0 pin output taanccr1 register inttancc1 signal toam1 pin output inttanov signal taanovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark v850e/if3: n = 0 to 4, m = 2, 4, a = 0, 1 v850e/ig3: n = 0 to 4, m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 274 ? capture operation when the taamce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tiama pin is detected, the count value of the 16-bit counter is stored in the taamccra register, and a capture interrupt request signal (inttamcca) is generated. the 16-bit counter continues counting in synchronization with th e count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttamov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (taamopt0.taamovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 6-38. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h taamce bit tiam0 pin input taamccr0 register inttamcc0 signal tiam1 pin input taamccr1 register inttamcc1 signal inttamov signal taamovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 275 figure 6-39. register setting in free-running timer mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance note the setting is invalid when the taamctl1.taameee bit = 1 (b) taan control register 1 (taanctl1) 0 0 0/1 0 0 taanctl1 101 taanmd2 taanmd1 taanmd0 taameee taamest taaasye 1, 0, 1: free-running timer mode 0: operate with count clock selected by taamcks0 to taamcks2 bits 1: count on external event count input signal (c) taam i/o control register 0 (taamioc0) 0000 0/1 taamioc0 0: disable toam0 pin output 1: enable toam0 pin output setting of toam0 pin output level before count operation 0: low level 1: high level 0: disable toam1 pin output 1: enable toam1 pin output setting of toam1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 taamoe1 taamol0 taamoe0 taamol1 (d) taam i/o control register 1 (taamioc1) 0 0 0 0 0/1 taamioc1 select valid edge of tiam0 pin input note select valid edge of tiam1 pin input note 0/1 0/1 0/1 taamis2 taamis1 taamis0 taamis3 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 276 figure 6-39. register setting in free-running timer mode (2/2) (e) taam i/o control register 2 (taamioc2) 0 0 0 0 0/1 taamioc2 select valid edge of external event count input (tiam0 pin) note 0/1 0 0 taamees0 taamets1 taamets0 taamees1 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. (f) taan option register 0 (taanopt0) 0 0 0/1 0/1 0 taanopt0 overflow flag specifies if taamccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if taamccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 taamccs0 taanovf taamccs1 (g) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (h) taan capture/compare regist ers 0 and 1 (taanccr0 and taanccr1) these registers function as captur e registers or compare registers depending on the setting of the taamopt0.taamccsa bit. when the registers function as capture registers, th ey store the count value of the 16-bit counter when the valid edge input to the tiama pin is detected. when the registers function as compare registers and when d a is set to the taanccra register, the inttancca signal is generated when the counter reaches (d a + 1), and the output signals of the toam0 and toam1 pins are inverted. remark v850e/if3: n = 0 to 4, m = 2, 4, a = 0, 1 v850e/ig3: n = 0 to 4, m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 277 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 6-40. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> ffffh 16-bit counter 0000h taance bit taanccr0 register inttancc0 signal toam0 pin output taanccr1 register inttancc1 signal toam1 pin output inttanov signal taanovf bit remark n = 0 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 278 figure 6-40. software processing flow in fr ee-running timer mode (c ompare function) (2/2) taance bit = 1 read taanopt0 register (check overflow flag). register initial setting taanctl0 register (taancks0 to taancks2 bits) taanctl1 register, taamioc0 register, taamioc2 register, taanopt0 register, taanccr0 register, taanccr1 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). start execute instruction to clear taanovf bit (clr taanovf). <1> count operation start flow <2> overflow flag clear flow taance bit = 0 counter is initialized and counting is stopped by clearing taance bit to 0. stop <3> count operation stop flow taanovf bit = 1 no yes remark v850e/if3: n = 0 to 4, m = 2, 4 v850e/ig3: n = 0 to 4, m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 279 (b) when using capture/compare register as capture register figure 6-41. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h taamce bit tiam0 pin input taamccr0 register inttamcc0 signal tiam1 pin input taamccr1 register inttamcc1 signal inttamov signal taamovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 280 figure 6-41. software processing flow in fr ee-running timer mode (c apture function) (2/2) taamce bit = 1 read taamopt0 register (check overflow flag). register initial setting taamctl0 register (taamcks0 to taamcks2 bits) taamctl1 register, taamioc1 register, taamopt0 register initial setting of these registers is performed before setting the taamce bit to 1. the taamcks0 to taamcks2 bits can be set at the same time when counting has been started (taamce bit = 1). start execute instruction to clear taamovf bit (clr taamovf). <1> count operation start flow <2> overflow flag clear flow taamce bit = 0 counter is initialized and counting is stopped by clearing taamce bit to 0. stop <3> count operation stop flow taamovf bit = 1 no yes remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 281 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter aa is used as an interval timer with the taanccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttancca signal has been detected. ffffh 16-bit counter 0000h taance bit taanccr0 register inttancc0 signal toam0 pin output taanccr1 register inttancc1 signal toam1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding taanccra register must be re-set in the interrupt servicing that is executed when the inttancca signal is detected. the set value for re-setting the taanccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark v850e/if3: n = 0 to 4, m = 2, 4, a = 0, 1 v850e/ig3: n = 0 to 4, m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 282 (b) pulse width measurement with capture register when pulse width measurement is performed with the taamccra register used as a capture register, software processing is necessary for reading the capture register each time the inttamcca signal has been detected and for calculating an interval. 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 ffffh 16-bit counter 0000h taamce bit tiam0 pin input taamccr0 register inttamcc0 signal tiam1 pin input taamccr1 register inttamcc1 signal inttamov signal taamovf bit pulse interval (d 00 ) pulse interval (10000h + d 01 - d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculated by reading the value of the taamccra register in synchronization with the inttamcca signal, and calculating the difference between the read value and the previously read value. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 283 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h taamce bit tiam0 pin input taamccr0 register tiam1 pin input taamccr1 register inttamov signal taamovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the taamccr0 register (setting of t he default value of the tiam0 pin input). <2> read the taamccr1 register (setting of t he default value of the tiam1 pin input). <3> read the taamccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the taamccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 284 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h taamce bit inttamov signal taamovf bit taamovf0 flag note tiam0 pin input taamccr0 register taamovf1 flag note tiam1 pin input taamccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the taamovf0 and taamovf1 flags are set on the internal ram by software. <1> read the taamccr0 register (setting of t he default value of the tiam0 pin input). <2> read the taamccr1 register (setting of t he default value of the tiam1 pin input). <3> an overflow occurs. set the taamovf0 and taamovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the taamccr0 register. read the taamovf0 flag. if the taamovf0 flag is 1, clear it to 0. because the taamovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the taamccr1 register. read the taamovf1 flag. if the taamovf1 flag is 1, clear it to 0 (the taamovf0 flag is cleared in <4>, and the taamovf1 flag remains 1). because the taamovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 285 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h taamce bit inttamov signal taamovf bit taamovf0 flag note tiam0 pin input taamccr0 register taamovf1 flag note tiam1 pin input taamccr1 register d 10 d 11 d 00 l d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the taamovf0 and taamovf1 flags are set on the internal ram by software. <1> read the taamccr0 register (setting of t he default value of the tiam0 pin input). <2> read the taamccr1 register (setting of t he default value of the tiam1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the taamccr0 register. read the overflow flag. if the overflow flag is 1, set only the taamovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the taamccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the taamovf1 flag. if the taamovf1 flag is 1, clear it to 0. because the taamovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 286 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16 -bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h taamce bit tiama pin input taamccra register inttamov signal taamovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the taamccra register (setting of t he default value of the tiama pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the taamccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 287 example when capture trigger interval is long ffffh 16-bit counter 0000h taamce bit tiama pin input taamccra register inttamov signal taamovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the taamccra register (setting of t he default value of the tiama pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment t he overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the taamccra register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the taamovf bit to 0 with the clr instruction after reading the taamovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the taamopt0 register after reading the taamovf bit when it is 1.
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 288 6.6.7 pulse width measurement mode (taammd2 to taammd0 bits = 110) this mode is valid only in taa2, taa3 (v850e/ig3 only), and taa4. in the pulse width measurement mode, 16-bit ti mer/event counter aa starts counting when the taamctl0.taamce bit is set to 1. each time the valid edge input to the tiama pin has been detected, the count value of the 16-bit counter is stored in the taamccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the taamccra register after a capture interrupt request signal (inttamcca) occurs. as shown in figure 6-43, select either the tiam0 or tiam1 pin as the captur e trigger input pin and set the unused pins to ?no edge detection? by using the taamioc1 register. figure 6-42. configuration in pulse width measurement mode taamccr0 register (capture) taamce bit taamccr1 register (capture) count clock selection edge detector edge detector tiam0 pin (capture trigger input) tiam1 pin (capture trigger input) clear inttamov signal inttamcc0 signal inttamcc1 signal 16-bit counter caution in the pulse width measure ment mode, select the internal clock as the count clock (by clearing the taamctl1.taameee bit to 0). remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 289 figure 6-43. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h taamce bit tiama pin input taamccra register inttamcca signal inttamov signal taamovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1 when the taamce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tiama pin is later detected, the count value of the 16- bit counter is stored in the taamccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt reques t signal (inttamcca) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiama pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttamov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (taamopt0.taamovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h taamovf bit set (1) count + captured value) count clock cycle remark v850e/if3: m = 2, 4, a = 0, 1 v850e/ig3: m = 2 to 4, a = 0, 1
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 290 figure 6-44. register setting in pu lse width measurement mode (1/2) (a) taam control register 0 (taamctl0) 0/1 0 0 0 0 taamctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 taamcks2 taamcks1 taamcks0 taamce (b) taam control register 1 (taamctl1) 00000 taamctl1 110 taammd2 taammd1 taammd0 taameee taamest 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by taamcks0 to taamcks2 bits taaasye (c) taam i/o control register 1 (taamioc1) 0 0 0 0 0/1 taamioc1 select valid edge of tiam0 pin input select valid edge of tiam1 pin input 0/1 0/1 0/1 taamis2 taamis1 taamis0 taamis3
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 291 figure 6-44. register setting in pu lse width measurement mode (2/2) (d) taam option register 0 (taamopt0) 00000 taamopt0 overflow flag 0 0 0/1 taamccs0 taamovf taamccs1 (e) taam counter read bu ffer register (taamcnt) the value of the 16-bit counter can be read by reading the taamcnt register. (f) taam capture/compare registers 0 and 1 (taamccr0 and taamccr1) these registers store the count value of the 16-bit counter when the valid edge input to the tiam0 and tiam1 pins is detected. remarks 1. taam i/o control register 0 (taamioc0) and taam i/o control register 2 (taamioc2) are not used in the pulse width measurement mode. 2. v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 292 (1) operation flow in pul se width measurement mode figure 6-45. software processing flow in pulse width measurement mode <1> <2> taamce bit = 1 taamce bit = 0 register initial setting taamctl0 register (taamcks0 to taamcks2 bits), taamctl1 register, taamioc1 register, taamopt0 register initial setting of these registers is performed before setting the taamce bit to 1. the taamcks0 to taamcks2 bits can be set at the same time when counting has been started (taamce bit = 1). the counter is initialized and counting is stopped by clearing the taamce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h taamce bit tiam0 pin input taamccr0 register inttamcc0 signal d 0 0000h 0000h d 1 d 2 remark v850e/if3: m = 2, 4 v850e/ig3: m = 2 to 4
chapter 6 16-bit timer/event counter aa (taa) user?s manual u18279ej3v0ud 293 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the taamovf bit to 0 with the clr instruction after reading the taamovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the taamopt0 register after reading the taamovf bit when it is 1.
user?s manual u18279ej3v0ud 294 chapter 7 16-bit timer/ event counter ab (tab) timer ab (tab) is a 16-bit timer/event counter. the v850e/if3 and v850e/ig3 incorporate tab0 and tab1. 7.1 overview an outline of tabn is shown below (n = 0, 1). ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? overflow interrupt request signal: 1 ? timer output pins note : 4 note this is the number of output pins of tabn; it does not include the output pi ns of tmqopn. for details of the output pins of tmqopn, see chapter 10 motor control function . 7.2 functions tabn has the following functions (n = 0, 1). ? 6-phase pwm output note ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement note this is connected to tmqopn. for details, see chapter 10 motor control function .
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 295 7.3 configuration tabn includes the following hardware (n = 0, 1). table 7-1. tabn configuration item configuration timer register 16-bit counter 1 registers tabn counter read buffer register (tabncnt) tabn capture/compare registers 0 to 3 (tabnccr0 to tabnccr3) ccr0 to ccr3 buffer registers timer input 12 in total (tib00 to tib03, tib10 to tib13, evtb0, evtb1, trgb0, trgb1 pins) note timer output 8 in total (tob00 to tob03, tob10 to tob13 pins) note control registers tabn control registers 0, 1 (tabnctl0, tabnctl1) tabn i/o control registers 0 to 2 (tabnioc0 to tabnioc2) tabn option register 0 (tabnopt0) note the tibn1 to tibn3 pins func tion alternately as timer output pins (tobn1 to tobn3). remark n = 0, 1 figure 7-1. tabn block diagram selector selector edge detector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 internal bus internal bus tabncnt tabnccr0 ccr1 buffer register tabnccr1 tibn0 evtbn trgbn tibn1 tibn2 tibn3 output controller ccr0 buffer register tabnccr2 ccr3 buffer register tabnccr3 ccr2 buffer register clear intt bn ov intt bn cc0 intt bn cc1 intt bn cc2 intt bn cc3 to bn 0 to bn 1 to bn 2 to bn 3 16-bit counter sampling clock edge detection/ noise eliminator edge detection/ noise eliminator f xx /4 edge detection/ noise eliminator edge detection/ noise eliminator remarks 1. f xx : peripheral clock 2. for the noise eliminator, see 4.6 noise eliminator . 3. n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 296 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tabncnt register. when the tabnctl0.tabnce bit = 0, the value of the 16-bit counter is ffffh. if the tabncnt register is read at this time, 0000h is read. reset sets the tabnce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr0 register is used as a compare regist er, the value written to the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttbncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, and the tabnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr1 register is used as a compare regist er, the value written to the tabnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttbncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, and the tabnccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr2 register is used as a compare regist er, the value written to the tabnccr2 register is transferred to the ccr2 buffer register. when the count value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttbncc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after reset, and the tabnccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr3 register is used as a compare regist er, the value written to the tabnccr3 register is transferred to the ccr3 buffer register. when the count value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttbncc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after reset, and the tabnccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tib n0 to tibn3, evtbn, and trgbn pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tabnioc1 and tabnioc2 registers. (7) output controller this circuit controls the output of the tobn0 to tobn3 pins. the output controller is controlled by the tabnioc0 register. (8) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 297 7.4 registers (1) tabn control register 0 (tabnctl0) the tabnctl0 register is an 8-bit register that controls the operation of tabn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tabnctl0 register by software. tabnce tabn operation disabled (tabn reset asynchronously note ) tabn operation enabled. tabnce 0 1 tabn operation control tabnctl0 (n = 0, 1) 0000 tabncks2 tabncks1 tabncks0 654321 after reset: 00h r/w address: tab0ctl0 fffff5e0h, tab1ctl0 fffff620h 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tabncks2 0 0 0 0 1 1 1 1 internal count clock selection tabncks1 0 0 1 1 0 0 1 1 tabncks0 0 1 0 1 0 1 0 1 <7> note the tabnopt0.tabnovf bit and the 16-bit counter are re set simultaneously. moreover, timer outputs (tobn0 to tobn3 pins) are reset to the tabnioc0 regi ster set status at the same time as the 16-bit counter is reset. cautions 1. set the tabncks2 to tabncks 0 bits when the tabnce bit = 0. when the value of the tabnce bit is change d from 0 to 1, the tabncks2 to tabncks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 298 (2) tabn control register 1 (tabnctl1) the tabnctl1 register is an 8-bit register that controls the operation of tabn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tabnest 0 1 software trigger control tabnctl1 (n = 0, 1) tabnest tabneee 0 0 tabnmd2 tabnmd1 tabnmd0 654321 after reset: 00h r/w address: tab0ctl1 fffff5e1h, tab1ctl1 fffff621h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tabnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tabnest bit as the trigger. disable operation with external event count input (evtbn pin). (perform counting with the count clock selected by the tabnctl0.tabncks0 to tabncks2 bits.) tabneee 0 1 count clock selection the tabneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode 6-phase pwm output mode note tabnmd2 0 0 0 0 1 1 1 1 timer mode selection tabnmd1 0 0 1 1 0 0 1 1 tabnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input (evtbn pin). (perform counting at the valid edge of the external event count input signal (evtbn pin).) ? read value of the tabnest bit is always 0. note the 6-phase pwm output mode cannot be used when only tabn is used. for details, see chapter 10 motor control function . cautions 1. the tabnest bit is valid only in th e external trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. external event count input is selected in th e external event count mode regardless of the value of the tabneee bit. 3. set the tabneee and tabnmd2 to tabnmd0 bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tabnce bit = 1. if rewriting was mistakenly performed, clear the tabnce bit to 0 and then set the bits again. 4. be sure to set bits 3, 4, and 7 to ?0?.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 299 (3) tabn i/o control register 0 (tabnioc0) the tabnioc0 register is an 8-bit regi ster that controls the timer output (tobn0 to tobn3, tobnt1 to tobnt3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnol3 tabnola 0 1 tobna, tobntb pin output level setting note to b na and to b ntb pins start output at high level. to b na and to b ntb pins start output at low level. tabnoe3 tabnol2 tabnoe2 tabnol1 tabnoe1 tabnol0 tabnoe0 531 after reset: 00h r/w address: tab0ioc0 fffff5e2h, tab1ioc0 fffff622h tabnoea 0 to b na, to b ntb pin output setting timer output disabled ? when tabnola bit = 0: low level is output from the tobna and tobntb pins ? when tabnola bit = 1: high level is output from the tobna and tobntb pins 7 <0> <2> <4> <6> tabnioc0 n = 0, 1 a = 0 to 3 b = 1 to 3 timer output enabled (a pulse is output from the tobna and tobntb pins). 1 note the output level of the timer output pins (tobna an d tobntb) specified by the tabnola bit is shown below. tabnce bit tobna and tobntb output pins 16-bit counter ? when tabnola bit = 0 tabnce bit tobna and tobntb output pins 16-bit counter ? when tabnola bit = 1 cautions 1. if the setting of the tabnioc0 register is changed when tobna and tobntb are set in the output mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. rewrite the tabnola and tabnoea bits wh en the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1. ) if rewriting was mistakenly performed, clear (0) the tabnce bit and then set the bits again. 3. if the tabnola bit is manipulated when the tabnce and tabnoea bits are 0, the output level of the tobna and tobntb pins changes. 4. to generate the tobntb pin output and the a/d conversion start trigger signal of a/d converters 0 and 1 in the 6-phase pwm output mode, be sure to set the tobntb pin output using the tabnioc0 register. at this time, be sure to clear the tabnol0 bit to 0 and set the tabnoe0 bit to 1.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 300 (4) tabn i/o control register 1 (tabnioc1) the tabnioc1 register is an 8-bit r egister that controls t he valid edge of the capture trigger input signals (tibn0 to tibn3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnis7 tabnis7 0 0 1 1 tabnis6 0 1 0 1 capture trigger input signal (tibn3 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tabnioc1 (n = 0, 1) tabnis6 tabnis5 tabnis4 tabnis3 tabnis2 tabnis1 tabnis0 654321 after reset: 00h r/w address: tab0ioc1 fffff5e3h, tab1ioc1 fffff623h tabnis5 0 0 1 1 tabnis4 0 1 0 1 capture trigger input signal (tibn2 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tabnis3 0 0 1 1 tabnis2 0 1 0 1 capture trigger input signal (tibn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tabnis1 0 0 1 1 tabnis0 0 1 0 1 capture trigger input signal (tibn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tabnis7 to tabnis0 bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear the tabnce bit to 0 and then set the bits again. 2. the tabnis7 to tabnis0 bits are valid on ly in the free-running timer mode (only when the tabnopt0.tabnccsa bit = 1) and the pulse width measurement mode (a = 0 to 3). in all other modes, a capture operation is not possible.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 301 (5) tabn i/o control register 2 (tabnioc2) the tabnioc2 register is an 8-bit regist er that controls the valid edge of the external event count input signal (evtbn pin) and external trigger input signal (trgbn pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tabnees1 0 0 1 1 tabnees0 0 1 0 1 external event count input signal (evtbn pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tabnioc2 (n = 0, 1) 000 tabnees1 tabnees0 tabnets1 tabnets0 654321 after reset: 00h r/w address: tab0ioc2 fffff5e4h, tab1ioc2 fffff624h tabnets1 0 0 1 1 tabnets0 0 1 0 1 external trigger input signal (trgbn pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tabnees1, tabnees0, tabnets1, and tabnets0 bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear the tabnce bit to 0 an d then set the bits again. 2. the tabnees1 and tabnees0 bits are va lid only when the tabnctl1.tabneee bit = 1 or when the external event count mode (tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 001) has been set. 3. the tabnets1 and tabnets0 bits are va lid only in the external trigger pulse output mode or one-shot pu lse output mode.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 302 (6) tabn option register 0 (tabnopt0) the tabnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnccs3 tabnccsa 0 1 tabnccra register capture/compare selection the tabnccsa bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by tabnctl0.tabnce bit = 0) tabnopt0 tabnccs2 tabnccs1 tabnccs0 0 tabncms note tabncuf note tabnovf <6> <5> <4> 3 <2> <1> after reset: 00h r/w address: tab0opt0 fffff5e5h, tab1opt0 fffff625h tabnovf set (1) reset (0) tabn overflow flag ? the tabnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttbnov) is generated at the same time that thetabnovf bit is set to 1. the inttbnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tabnovf bit is not cleared to 0 even when the tabnovf bit or the tabnopt0 register are read when the tabnovf bit = 1. ? before clearing the tabnovf bit to 0 after generation of the inttbnov signal, be sure to confirm (by reading) that the tabnovf bit is set to 1. ? the tabnovf bit can be both read and written, but the tabnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tabn. overflow occurred tabnovf bit 0 written or tabnctl0.tabnce bit = 0 <7> <0> n = 0, 1 a = 0 to 3 note for details of the tabncms and tabncuf bits, see chapter 10 motor control function . cautions 1. rewrite the tabnccs3 to tabnccs0 bits when the tabn ce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear the tabnce bit to 0 and th en set the bits again. 2. be sure to set bit 3 to ?0?.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 303 (7) tabn capture/compare register 0 (tabnccr0) the tabnccr0 register is a 16-bit re gister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tabnopt0.tabnccs0 bit. in the pulse width measurement mode, the tabnccr0 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tabnccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tabnccr0 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr0 fffff5e6h, tab1ccr0 fffff626h 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 304 (a) function as compare register the tabnccr0 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttbncc0) is generated. if tobn0 pin output is ena bled at this time, the output of the tobn0 pin is inverted. when the tabnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared by setting the tabnctl0.tabnce bit to 0. (b) function as capture register when the tabnccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tabnccr0 register if the valid edge of the capture trigger input pin (tibn0 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tabnccr0 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tibn0 pin) is detected. even if the capture operation and re ading the tabnccr0 register c onflict, the correct value of the tabnccr0 register can be read. the capture register is cleared by setting the tabnctl0.tabnce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tabnccr1 register is the trigger. remark for anytime write and batch write, see 7.6 (2) anytime write and batch write .
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 305 (8) tabn capture/compare register 1 (tabnccr1) the tabnccr1 register, which consists of 16 bits, can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tabnopt0.tabnccs1 bit. in the pulse width measurement mode, the tabnccr1 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tabnccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tabnccr1 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr1 fffff5e8h, tab1ccr1 fffff628h 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 306 (a) function as compare register the tabnccr1 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttbncc1) is generated. if tobn1 pin output is ena bled at this time, the output of the tobn1 pin is inverted. the compare register is not cleared by setting the tabnctl0.tabnce bit to 0. (b) function as capture register when the tabnccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tabnccr1 register if the valid edge of the capture trigger input pin (tibn1 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tabnccr1 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tibn1 pin) is detected. even if the capture operation and re ading the tabnccr1 register c onflict, the correct value of the tabnccr1 register can be read. the capture register is cleared by setting the tabnctl0.tabnce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tabnccr1 r egister is the trigger. remark for anytime write and batch write, see 7.6 (2) anytime write and batch write .
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 307 (9) tabn capture/compare register 2 (tabnccr2) the tabnccr2 register is a 16-bit re gister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tabnopt0.tabnccs2 bit. in the pulse width measurement mode, the tabnccr2 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tabnccr2 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tabnccr2 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr2 fffff5eah, tab1ccr2 fffff62ah 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 308 (a) function as compare register the tabnccr2 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr2 register is transferred to the ccr2 buffer register. when the value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttbncc2) is generated. if tobn2 pin output is ena bled at this time, the output of the tobn2 pin is inverted. the compare register is not cleared by setting the tabnctl0.tabnce bit to 0. (b) function as capture register when the tabnccr2 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tabnccr2 register if the valid edge of the capture trigger input pin (tibn2 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tabnccr2 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tibn2 pin) is detected. even if the capture operation and re ading the tabnccr2 register c onflict, the correct value of the tabnccr2 register can be read. the capture register is cleared by setting the tabnctl0.tabnce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tabnccr1 r egister is the trigger. remark for anytime write and batch write, see 7.6 (2) anytime write and batch write .
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 309 (10) tabn capture/compare register 3 (tabnccr3) the tabnccr3 register, which consists of 16 bits, can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tabnopt0.tabnccs3 bit. in the pulse width measurement mode, the tabnccr3 register can be used only as a capture register . in any other mode, this register can be used only as a compare register. the tabnccr3 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tabnccr3 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr3 fffff5ech, tab1ccr3 fffff62ch 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 310 (a) function as compare register the tabnccr3 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr3 register is transferred to the ccr3 buffer register. when the value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttbncc3) is generated. if tobn3 pin output is ena bled at this time, the output of the tobn3 pin is inverted. the compare register is not cleared by setting the tabnctl0.tabnce bit to 0. (b) function as capture register when the tabnccr3 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tabnccr3 register if the valid edge of the capture trigger input pin (tibn3 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tabnccr3 register and t he 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tibn3 pin) is detected. even if the capture operation and re ading the tabnccr3 register c onflict, the correct value of the tabnccr3 register can be read. the capture register is cleared by setting the tabnctl0.tabnce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tabnccr1 r egister is the trigger. remark for anytime write and batch write, see 7.6 (2) anytime write and batch write .
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 311 (11) tabn counter read bu ffer register (tabncnt) the tabncnt register is a read buffer register t hat can read the count va lue of the 16-bit counter. if this register is read when the tabnctl0.tabnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tabncnt register is set to 0000h when th e tabnce bit = 0. if the tabncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tabncnt register is set to 0000h after reset, and the tabnce bit is cleared to 0. tabncnt (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r address: tab0cnt fffff5eeh, tab1cnt fffff62eh 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 312 7.5 timer output operations the following table shows the operations and out put levels of the tobn0 to tobn3 pins. table 7-6. timer output control in each mode operation mode tobn0 pin tobn1 pin tobn2 pin tobn3 pin interval timer mode pwm output external event count mode none external trigger pulse output mode external trigger pulse output external trigger pulse output external trigger pulse output one-shot pulse output mode one-shot pulse output one-shot pulse output one-shot pulse output pwm output mode pwm output pwm output pwm output pwm output free-running timer mode pwm output (only when compare function is used) pulse width measurement mode none remark n = 0, 1 table 7-7. truth table of tobn0 to tobn3 pins under control of timer output control bits tabnioc0.tabnola bit tabnioc0.tabnoea bit tabnctl0.tabnce bit level of tobna pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 313 7.6 operation tabn can perform the following functions. table 7-8. tabn specifications in each mode operation tabnctl1.tabnest bit (software trigger bit) trgbn pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode invalid invalid compare only anytime write external trigger pulse output mode va lid valid compare only batch write one-shot pulse output mode valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode invalid invalid capture only not applicable remarks 1. tabn has a function to execute tuning with taan. for details, see chapter 10 motor control function . 2 . n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 314 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark n = 0, 1 a = 0 to 3 (a) counter start operation ? in external event count mode when the tabnctl0.tabnce bit is set from 0 to 1, the 16-bit counter is set to 0000h. after that, it counts up to 0001h, 0002h, 0003h, each time the valid edge of external event count input (evtbn) is detected. ? in modes other than the above starts counting from the defau lt value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and when its value is captured. t he count operation from ffffh to 0000h that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. therefore, the inttbncca interrupt signal is not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running mode or pulse width measurement mode. if the counter overflows, the tabnopt0.tabnovf bit is set to 1 and an interrupt request signal (inttbnov) is generated. note that the inttbnov signal is not generated under the following conditions. ? immediately after a count operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured in the pulse width measur ement mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (inttbnov) has been generated, be sure to check that the overflow flag (tabnovf bit) is set to 1. (d) counter read operation during count operation the value of the 16-bit counter of tabn can be r ead by using the tabncnt register during the count operation. when the tabnctl0.tabnce bit = 1, the value of th e 16-bit counter can be read by reading the tabncnt register. when the tabnce bit = 0, the 16-bit counter is ffffh and t he tabncnt register is 0000h. (e) interrupt operation tabn generates the following five interrupt request signals. ? inttbncc0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the tabnccr0 register. ? inttbncc1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the tabnccr1 register.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 315 ? inttbncc2 interrupt: this signal functions as a match interrupt request signal of the ccr2 buffer register and as a capture interrupt request signal to the tabnccr2 register. ? inttbncc3 interrupt: this signal functions as a match interrupt request signal of the ccr3 buffer register and as a capture interrupt request signal to the tabnccr3 register. ? inttbnov interrupt: this signal functions as an overflow interrupt request signal.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 316 (2) anytime write and batch write the tabnccr0 to tabnccr3 registers can be rewritten in the tabn during timer operation (tabnctl0.tabnce bit = 1), but the write method (anytime write, batch write) of the ccr0 to ccr3 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tabnccr0 to tabnccr3 registers to the ccr0 to ccr3 buffer registers during the timer operation. figure 7-2. flowchart of basic operation for anytime write start initial settings ? set values to tabnccra register ? timer operation enable (tabnce bit = 1) transfer values of tabnccra register to ccra buffer register timer operation ? match between 16-bit counter and ccrb buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttbncc0 signal output tabnccra register rewrite transfer to ccra buffer register inttbnccb signal output note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccrb buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0, 1 a = 0 to 3 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 317 figure 7-3. timing of anytime write tabnce bit = 1 16-bit counter tabnccr0 register tabnccr1 register tabnccr2 register tabnccr3 register inttbncc0 signal inttbncc1 signal inttbncc2 signal inttbncc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 0000h ffffh remarks 1. d 01 , d 02 : set values of tabnccr0 register d 11 , d 12 : set values of tabnccr1 register d 21 : set value of tabnccr2 register d 31 : set value of tabnccr3 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 318 (b) batch write in this mode, data is transferred all at once from the tabnccr0 to tabnccr3 registers to the ccr0 to ccr3 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tabnccr1 register. whether to enable or disable the next transfer timi ng is controlled by writin g or not writing to the tabnccr1 register. in order for the set value when the tabnccr0 to t abnccr3 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 to ccr3 buffer registers), it is necessary to rewrite tabn ccr0 and finally write to the tabnccr1 register before the 16-bit counter value and the ccr0 buffer register value match. the values of the tabnccr0 to tabnccr3 registers are transferred to the ccr0 to ccr3 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer regi ster. thus, even when wishing only to rewrite the value of the tabnccr0, tabnccr2, or tabnccr3 register, also write the same value (same as preset value of the tabnccr1 register) to the tabnccr1 register.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 319 figure 7-4. flowchart of basic operation for batch write start initial settings ? set values to tabnccra register ? timer operation enable (tabnce bit = 1) transfer of values of tabnccra register to ccra buffer register timer operation ? match between 16-bit counter and ccrb buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tabnccra register to ccra buffer register inttbnccb signal output tabnccry register rewrite tabnccr1 register rewrite inttbncc0 signal output batch write enable note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccrb buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tabnccr1 register includes enabling of ba tch write. thus, rewrite the tabnccr1 register after rewriting the ta bnccr0, tabnccr2, and tabnccr3 registers. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. a = 0 to 3 b = 1 to 3 y = 0, 2, 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 320 figure 7-5. timing of batch write tabnce bit = 1 16-bit counter tabnccr0 register tabnccr1 register tabnccr2 register tabnccr3 register inttbncc0 signal inttbncc1 signal inttbncc2 signal inttbncc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 tobn0 pin output tobn1 pin output tobn2 pin output tobn3 pin output d 21 d 21 note 1 note 1 same value write 0000h ffffh note 1 note 1 note 1 note 1 note 1 note 1 note 2 note 3 d 21 d 21 notes 1. because the tabnccr1 register was not rewritten, d 02 is not transferred. 2. because tabnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tabnccr0 register (d 01 ). 3. because tabnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tabnccr0 register (d 12 ). remarks 1. d 01 , d 02 , d 03 : set values of tabnccr0 register d 11 , d 12 : set values of tabnccr1 register d 21 : set value of tabnccr2 register d 31 , d 32 , d 33 : set values of tabnccr3 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 321 7.6.1 interval timer mode (t abnmd2 to tabnmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttbncc0) is generated at the interval set by the tabnccr0 register if the tabnctl0.tabnce bit is set to 1. a pwm waveform with a duty factor of 50% whose half cycle is equal to the interval c an be output from the tobn0 pin. the tabnccr1 to tabnccr3 registers are not used in the interval timer mode. however, the set value of the tabnccr1 to tabnccr3 registers is transferred to the ccr1 to ccr3 buffer registers and, when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 bu ffer registers, compare match interrupt request signals (inttbncc1 to inttbncc3) are generated. in addition, a pwm waveform with a duty factor of 50%, which is inverted when the inttbncc1 to inttbncc3 signals are generated, can be output from the tobn1 to tobn3 pins. the value of the tabnccr1 to tabnccr3 registers ca n be rewritten even while the timer is operating. figure 7-6. interval timer configuration 16-bit counter output controller ccr0 buffer register tabnce bit tabnccr0 register count clock selection clear match signal tobn0 pin inttbncc0 signal remark n = 0, 1 figure 7-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 322 when the tabnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the tobn0 pin is inverted. additionally, the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the tobn0 pin is in verted, and a compare match interrupt request signal (inttbncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tabnccr0 register + 1) count clock cycle remark n = 0, 1 figure 7-8. register setting for in terval timer mode operation (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 0 0 0/1 note 00 tabnctl1 0, 0, 0: interval timer mode 000 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count with external event count input signal note the tabneee bit can be set to 1 only when timer output (tobn0 to tobn3) is used. however, set the tabnccr0 to tabnccr3 registers to the same value.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 323 figure 7-8. register setting for in terval timer mode operation (2/3) (c) tabn i/o control register 0 (tabnioc0) 0/1 0/1 0/1 0/1 0/1 tabnioc0 0: disable tobn0 pin output 1: enable tobn0 pin output setting of tobn0 pin output level before count operation 0: low level 1: high level 0: disable tobn1 pin output 1: enable tobn1 pin output setting of tobn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 0: disable tobn2 pin output 1: enable tobn2 pin output setting of tobn2 pin output level before count operation 0: low level 1: high level 0: disable tobn3 pin output 1: enable tobn3 pin output setting of tobn3 pin output level before count operation 0: low level 1: high level tabnoe3 tabnol2 tabnoe2 tabnol3 (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 note tabnioc2 0/1 note 00 tabnees0 tabnets1 tabnets0 tabnees1 select valid edge of external event count input (evtbn pin). note the tabnees1 and tabnees0 bits can be set only when timer output (tobn0 to tobn3) is used. however, set the tabnccr0 to tabnccr3 registers to the same value. (e) tabn counter read buffer register (tabncnt) by reading the tabncnt regist er, the count value of the 16-bit counter can be read. (f) tabn capture/compare register 0 (tabnccr0) if the tabnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 324 figure 7-8. register setting for in terval timer mode operation (3/3) (g) tabn capture/compare register s 1 to 3 (tabnccr1 to tabnccr3) the tabnccr1 to tabnccr3 registers are not used in the interval timer mode. however, the set values of the tabnccr1 to tabnccr3 registers are trans ferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit c ounter matches the value of the ccr1 to ccr3 buffer registers, the tobn1 to tobn3 pin outputs are inverted and a com pare match interrupt request signal (inttbncc1 to inttbncc3) is generated. when the tabnccr1 to tabnccr3 registers are not us ed, it is recommended to set their values to ffffh. also mask the registers by the in terrupt mask flags (tabnccic1.tabnccmk1 to tabnccic3.tabnccmk3). remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the interval timer mode. 2. n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 325 (1) interval timer mode operation flow figure 7-9. software processing flow in interval timer mode (1/2) tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register note , tabnccr0 register initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time as when counting starts (tabnce bit = 1). start <1> count operation start flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal note the tabnees1 and tabnees0 bits can be set only when timer output (tobn0 to tobn3) is used. however, set the tabnccr0 to tabncc r3 registers to the same value. remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 326 figure 7-9. software processing flow in interval timer mode (2/2) tabnce bit = 0 the counter is initialized and counting is stopped by clearing the tabnce bit to 0. the output level of the tobn0 pin is as specified by the tabnioc0 register. stop <2> count operation stop flow remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 327 (2) interval timer mode operation timing (a) operation if tabnccr0 register is set to 0000h if the tabnccr0 register is set to 0000h, the inttbnc c0 signal is generated at each count clock, and the output of the tobn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0, 1 (b) operation if tabnccr0 register is set to ffffh if the tabnccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up ti ming. the inttbncc0 signal is generated and the output of the tobn0 pin is inverted. at this time, an overflow interrupt request signal (inttbnov) is not generated, nor is the overflow flag (tabnopt0.tabnovf bit) set to 1. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 328 (c) notes on rewriting tabnccr0 register if the value of the tabnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the overflow may occur, st op counting once and then change the set value. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tabnol0 bit tobn0 pin output inttbncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0, 1 if the value of the tabnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tabnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttbncc0 signal is generated and the output of the tobn0 pin is inverted. therefore, the inttbncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 329 (d) operation of tabnccr 1 to tabnccr3 registers figure 7-10. configuration of tabnccr1 to tabnccr3 registers ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttbncc0 signal tobn3 pin inttbncc3 signal tobn0 pin tabnccr1 register ccr1 buffer register match signal tobn1 pin inttbncc1 signal tabnccr3 register ccr3 buffer register match signal tobn2 pin inttbncc2 signal tabnccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 330 when the tabnccrb register is set to the same valu e as the tabnccr0 register, the inttbnccb signal is generated at the same timing as the inttbncc0 si gnal and the tobnb pin output is inverted. in other words, a pwm waveform with a duty factor of 50% can be output from the tobnb pin. the following shows the operation when the tabnccrb register is set to other than the value set in the tabnccr0 register. if the set value of the tabnccrb register is less than the set value of the tabnccr0 register, the inttbnccb signal is generated once per cycle. at the same time, the output of t he tobnb pin is inverted. the tobnb pin outputs a pwm waveform with a duty fa ctor of 50% after outputting a short-width pulse. figure 7-11. timing chart when d 01 d b1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal tabnccr1 register tobn1 pin output inttbncc1 signal tabnccr2 register tobn2 pin output inttbncc2 signal tabnccr3 register tobn3 pin output inttbncc3 signal remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 331 if the set value of the tabnccrb register is greater than the set value of the tabnccr0 register, the count value of the 16-bit counter does not match the valu e of the tabnccrb register. consequently, the inttbnccb signal is not generated, nor is the output of the tobnb pin changed. when the tabnccrb register is not used, it is recommended to set its value to ffffh. figure 7-12. timing chart when d 01 < d b1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tobn0 pin output inttbncc0 signal tabnccr1 register tobn1 pin output inttbncc1 signal tabnccr2 register tobn2 pin output inttbncc2 signal tabnccr3 register tobn3 pin output inttbncc3 signal remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 332 (3) operation by external event count input (evtbn) (a) operation to count the 16-bit counter at the va lid edge of the external event count input (evtbn) in the interval timer mode, the 16-bit counter is cleared from ffffh to 0000h by the valid edge of the external event count input after the tabnce bit is set from 0 to 1. when 0001h is set to both the tabnccr0 and tabnccrb registers, the output of the tobn0 and tobnb pins is inverted each time the 16-bit counter counts twice (b = 1 to 3). the tabnctl1.tabneee bit can be set to 1 in the inte rval timer mode only when the timer output (tobn0, tobnb) is used with the external event count input. tabnce bit 16-bit counter tobn0 pin output tabnccr0 register tobn1 pin output tabnccr1 register tobn2 pin output tabnccr2 register tobn3 pin output tabnccr3 register ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h external event count input (evtbn pin input) number of external events: 2 number of external events: 2 number of external events: 2 2-count width 2-count width 2-count width remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 333 7.6.2 external event count mode (tabnmd2 to tabnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input (evtbn) is counted when the tabnctl0.tabnce bit is set to 1, and an interrupt request signal (inttbncc0) is generat ed each time the specified number of edges set by the tabnccr0 register have be en counted. the tobn0 to tobn3 pins cannot be used. when using the tobn0 to tobn3 pins for external event count input, set the tabnctl1.tabneee bit to 1 in the interval timer mode (see 7.6.1 (3) operation by external event count input (evtbn) ). the tabnccr1 to tabnccr3 registers are not used in the external event count mode. figure 7-13. configuration in external event count mode 16-bit counter ccr0 buffer register tabnce bit tabnccr0 register edge detector clear match signal inttbncc0 signal evtbn pin (external event count input) remark n = 0, 1 figure 7-14. basic timing in external event count mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal d 0 d 0 d 0 d 0 16-bit counter external event count input (evtbn pin input) d 0 external event count: (d 0 + 1) external event count: (d 0 + 1) external event count: (d 0 + 1) d 0 ? 1d 0 0000 0001 tabnccr0 register inttbncc0 signal remarks 1. this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. 2. n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 334 when the tabnce bit is set to 1, the value of the 16- bit counter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count inpu t is detected. additionally, the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttbncc0) is generated. the inttbncc0 signal is generated each time the valid edge of the external event count has been detected ?value set to tabnccr0 register + 1? times. figure 7-15. register setting for operati on in external event count mode (1/2) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 0: stop counting 1: enable counting 000 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 00000 tabnctl1 0, 0, 1: external event count mode 001 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest (c) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input (evtbn pin) 0/1 0 0 tabnees0 tabnees1 tabnets0 tabnets1 (d) tabn counter read buffer register (tabncnt) the count value of the 16-bit counter can be read by reading the tabncnt register. (e) tabn capture/compare register 0 (tabnccr0) if the tabnccr0 register is set to d 0 , the compare match interrupt request signal (inttbncc0) is generated when the number of external events has reached (d 0 + 1).
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 335 figure 7-15. register setting for operati on in external event count mode (2/2) (f) tabn capture/compare register s 1 to 3 (tabnccr 1 to tabnccr3) the tabnccr1 to tabnccr3 registers are not used in the external event count mode. however, the set value of the tabnccr1 to tabnccr3 registers are transferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, compare match interrupt request si gnals (inttbncc1 to inttbncc3) are generated. when the tabnccr1 to tabnccr3 registers are not used, it is recommended to set their values to ffffh. also mask the registers by the in terrupt mask flags (tabnccic1.tabnccmk1 to tabnccic3.tabnccmk3). caution set the tabnioc0 register to 00h. remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the external event count mode. 2. n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 336 (1) external event count mode operation flow figure 7-16. software processing flow in external event count mode tabnce bit = 1 tabnce bit = 0 register initial setting tabnctl1 register, tabnioc2 register, tabnccr0 to tabnccr3 registers initial setting of these registers is performed before setting the tabnce bit to 1. the counter is initialized and counting is stopped by clearing the tabnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 337 (2) operation timing in external event count mode caution in the external event count mode, use of th e timer output (tobn0 to tobn3) is disabled. if using timer output (tobn0 to tobn3) with external event count input (evtbn), set the interval timer mode, and select the operation en abled by the external event count input for the count clock (tabnctl1.tabneee bit = 1) (see 7.6.1 (3) operation by external event count input (evtbn)). (a) operation if tabnccr0 register is set to 0000h when the tabnccr0 register is set to 0000h, the 16-b it counter is repeatedly cleared to 0000h and generates an inttbncc0 signal each time it has detec ted the valid edge of the external event count signal and its value has matched t hat of the ccr0 buffer register. the value of the 16-bit counter is always 0000h. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal 0000h inttbncc0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 338 (b) operation if tabnccr0 register is set to ffffh if the tabnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttbncc0 signal is generated. at this time, the tabnopt0.tabnovf bit is not set. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal ffffh external event count: 10000h external event count: 10000h external event count: 10000h remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 339 (c) operation with tabnccr0 set to ffffh and tabnccrb register to 0000h when the tabnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time it has detected the valid edge of the external event count si gnal. the counter is then cleared to 0000h in synchronization with the next count-up timing and the inttbncc0 signal is generated. at this time, the tabnopt0.tabnovf bit is not set. if the tabnccrb register is set to 0000h, the inttbnc cb signal is generated when the 16-bit counter is cleared to 0000h. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tabnccr1 register inttbncc1 signal tabnccr2 register inttbncc2 signal tabnccr3 register inttbncc3 signal ffffh 0000h 0000h 0000h remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 340 (d) notes on rewriting the tabnccr0 register if the value of the tabnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the overflow may occur, st op counting once and then change the set value. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1) (d 1 + 1) external event count (ng) (10000h + d 2 + 1) external event count (2) (d 2 + 1) remark n = 0, 1 if the value of the tabnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tabnccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttbncc0 signal is generated. therefore, the inttbncc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 341 (e) operation of tabnccr1 to tabnccr3 registers figure 7-17. configuration of tabnccr1 to tabnccr3 registers ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttbncc0 signal inttbncc3 signal evtbn pin (external event count input) tabnccr1 register ccr1 buffer register match signal inttbncc1 signal tabnccr3 register ccr3 buffer register match signal inttbncc2 signal tabnccr2 register ccr2 buffer register match signal 16-bit counter edge detector remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 342 if the set value of the tabnccrb register is smalle r than the set value of the tabnccr0 register, the inttbnccb signal is generated once per cycle. figure 7-18. timing chart when d 01 d b1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tabnccr1 register inttbncc1 signal tabnccr2 register inttbncc2 signal tabnccr3 register inttbncc3 signal remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 343 if the set value of the tabnccrb register is greater than the set value of the tabnccr0 register, the inttbnccb signal is not generated because the count va lue of the 16-bit counte r and the value of the tabnccrb register do not match. when the tabnccrb register is not used, it is recommended to set its value to ffffh. figure 7-19. timing chart when d 01 < d b1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tabnccr1 register inttbncc1 signal tabnccr2 register inttbncc2 signal tabnccr3 register inttbncc3 signal remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 344 7.6.3 external trigger pulse output m ode (tabnmd2 to tabnmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter ab waits for a trigger when the tabnctl0.tabnce bit is set to 1. when the valid edge of an external trigger input signal (trgbn) is detected, 16-bit timer/event counter ab starts counting, and outputs a pwm waveform (up to 3-phas e) from the tobn1 to tobn3 pins. a pwm waveform with a duty factor of 50% whose half cycle is the set value of the tabnccr0 register + 1 can also be output from the tobn0 pin. pulses can also be output by generating a software trigger instead of using the external trigger input. figure 7-20. configuration in external trigger pulse output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttbncc0 signal tobn3 pin inttbncc3 signal tobn0 pin trgbn pin (external trigger input) transfer s r tabnccr1 register ccr1 buffer register match signal tobn1 pin inttbncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer tobn2 pin inttbncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller evtbn pin (external event count input) internal count clock edge detector count clock selection remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 345 figure 7-21. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tabnce bit external trigger input (trgbn pin input) tabnccr0 register inttbncc0 signal tobn0 pin output tabnccr1 register inttbncc1 signal tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 346 16-bit timer/event counter ab waits for a trigger when the tabn ce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the tobnb pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of th e tobn0 pin is inverted. the tobnb pin ou tputs a high-level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tabnccrb register) count clock cycle cycle = (set value of tabnccr0 register + 1) count clock cycle duty factor = (set value of tabnccrb regist er)/(set value of tabnccr0 register + 1) the compare match request signal inttbncc0 is generat ed when the 16-bit counter counts next time after its count value matches the value of the cc r0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttbnccb is generated when t he count value of the 16-bit counter matches the value of the ccrb buffer register. the value set to the tabnccra register is transferred to the ccra buffer register when the count value of the 16- bit counter matches the value of the ccr0 buffer r egister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal (trgbn ), or setting the software trigger (tabnctl1.tabnest bit) to 1 is used as the trigger. remark n = 0, 1 a = 0 to 3 b = 1 to 3 figure 7-22. setting of registers in exte rnal trigger pulse output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 347 figure 7-22. setting of registers in exte rnal trigger pulse output mode (2/3) (b) tabn control register 1 (tabnctl1) 0 0/1 0/1 0 0 tabnctl1 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count with external event count input signal generate software trigger when 1 is written 010 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest 0, 1, 0: external trigger pulse output mode (c) tabn i/o control register 0 (tabnioc0) 0/1 0/1 0/1 0/1 0/1 tabnioc0 0: disable tobn0 pin output 1: enable tobn0 pin output setting of tobn0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn1 pin output 1: enable tobn1 pin output setting of tobn1 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 tobnb pin output 16-bit counter ? when tabnolb bit = 0 tobnb pin output 16-bit counter ? when tabnolb bit = 1 tabnoe3 tabnol2 tabnoe2 tabnol3 setting of tobn3 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn2 pin output 1: enable tobn2 pin output setting of tobn2 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn3 pin output 1: enable tobn3 pin output
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 348 figure 7-22. setting of registers in exte rnal trigger pulse output mode (3/3) (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external trigger input (trgbn pin) select valid edge of external event count input (evtbn pin) 0/1 0/1 0/1 tabnees0 tabnets1 tabnets0 tabnees1 (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register, d 1 to the tabnccr1 register, d 2 to the tabnccr2 register, and d 3 , to the tabnccr3 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle tobn1 pin pwm waveform active level width = d 1 count clock cycle tobn2 pin pwm waveform active level width = d 2 count clock cycle tobn3 pin pwm waveform active level width = d 3 count clock cycle remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the external trigger pulse output mode. 2. n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 349 (1) operation flow in extern al trigger pulse output mode figure 7-23. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register ccr0 buffer register inttbncc0 signal tobn0 pin output tabnccr1 register ccr1 buffer register inttbncc1 signal tobn1 pin output tabnccr2 register ccr2 buffer register inttbncc2 signal tobn2 pin output tabnccr3 register ccr3 buffer register inttbncc3 signal tobn3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 external trigger input (trgbn pin input)
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 350 figure 7-23. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr3 registers initial setting of these registers is performed before setting the tabnce bit to 1. writing of the tabnccr1 register must be performed when the set duty factor is only changed after writing the tabnccr2 and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. writing same value (same as preset value of the tabnccr1 register) to the tabnccr1 register is necessary only when the set duty factor of the tobn2 and tobn3 pin outputs is changed. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. only writing of the tabnccr1 register must be performed when the set duty factor of the tobn1 is only changed. when counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. counting is stopped. the tabncks0 to tabncks2 bits can be set at the same time as when counting is enabled (tabnce bit = 1). trigger wait status writing of the tabnccr1 register must be performed after writing the tabnccr0, tabnccr2, and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer registers. writing same value (same as preset value of the tabnccr1 register) to the tabnccr1 register is necessary only when the set cycle is changed. <2> tabnccr0 to tabnccr3 register setting change flow <3> tabnccr0 register setting change flow <4> tabnccr1 to tabnccr3 register setting change flow <5> tabnccr2, tabnccr3 register setting change flow <6> tabnccr1 register setting change flow <7> count operation stop flow tabnce bit = 0 setting of tabnccr2 and tabnccr3 registers setting of tabnccr1 register setting of tabnccr2 and tabnccr3 registers setting of tabnccr1 register stop setting of tabnccr1 register setting of tabnccr0 register setting of tabnccr1 register setting of tabnccr0, tabnccr2, and tabnccr3 registers tabnccr1 register when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 351 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tabnccr1 register last. rewrite the tabnccrb register after writing the tabnccr1 register after the inttbncc0 signal is detected. remark n = 0, 1 b = 1 to 3 ffffh 16-bit counter 0000h tabnce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tabnccr0 register ccr0 buffer register inttbncc0 signal tabnccr1 register ccr1 buffer register inttbncc1 signal tobn1 pin output tabnccr2 register ccr2 buffer register inttbncc2 signal tobn2 pin output tabnccr3 register ccr3 buffer register inttbncc3 signal tobn3 pin output tobn0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 external trigger input (trgbn pin input)
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 352 in order to transfer data from the tabnccra register to the ccra buffer register, the tabnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tabnccr0 register, set the active level width to the tabnccr2 and tabnccr3 registers, and then set an active level to the tabnccr1 register. to change only the cycle of the pwm waveform, firs t set the cycle to the tabnccr0 register, and then write the same value (same as preset value of the tabnccr1 register) to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set an active level to the tabnccr2 and tabnccr3 registers and then set an active level to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the tobn1 pin, only the tabnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the tobn2 and tobn3 pins, first set an active level width to the tabnccr2 and tabnccr3 registers, and then write the same value (same as preset value of the tabnccr1 register) to the tabnccr1 register. after data is written to the tabnccr1 register, the val ue written to the tabnccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tabnccr0 to tabnccr3 registers again a fter writing the tabnccr1 register once, do so after the inttbncc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because timing of transferring data from t he tabnccra register to the ccra buffer register conflicts with writing the tabnccra register. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 353 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tabnccrb register to 0000h. the 16-bit counter is cleared to 0000h and the inttbncc0 and inttbnccb signals are generate d at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrb register inttbncc0 signal inttbnccb signal tobnb pin output external trigger input (trgbn pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 note note note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1, b = 1 to 3 to output a 100% waveform, set a value of (set value of tabnccr0 register + 1) to the tabnccrb register. if the set value of the tabnccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tabnce bit tabnccr0 register tabnccrb register inttbncc0 signal inttbnccb signal tobnb pin output d 0 ? 1d 0 ? 1 external trigger input (trgbn pin input) note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1, b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 354 (c) conflict between trigger detection and match with ccrb buffer register if the trigger is detected immediately after the inttb nccb signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the tobnb pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrb buffer register inttbnccb signal tobnb pin output external trigger input (trgbn pin input) d b d b ? 1d b 0000 ffff 0000 shortened remark n = 0, 1 b = 1 to 3 if the trigger is detected immediately before the inttb nccb signal is generated, the inttbnccb signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the tobnb pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrb buffer register inttbnccb signal tobnb pin output d b d b ? 2d b ? 1d b 0000 ffff 0000 0001 extended external trigger input (trgbn pin input) remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 355 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttb ncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the tobnb pin is extended by time from generation of the inttbncc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttbncc0 signal tobnb pin output d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended external trigger input (trgbn pin input) remark n = 0, 1 b = 1 to 3 if the trigger is detected immediately before the inttb ncc0 signal is generated, the inttbncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the tobnb pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttbncc0 signal tobnb pin output external trigger input (trgbn pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 356 (e) generation timing of compare match interrupt request signal (inttbnccb) the timing of generation of the inttbnccb signal in the external trigger pulse output mode differs from the timing of inttbnccb signals in other mode; the inttbnccb signal is generated when the count value of the 16-bit counter matches the va lue of the ccrb buffer register. count clock 16-bit counter ccrb buffer register tobnb pin output inttbnccb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1 b = 1 to 3 usually, the inttbnccb signal is generated in synchr onization with the next count up after the count value of the 16-bit counter matches the va lue of the ccrb buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the tobnb pin.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 357 7.6.4 one-shot pulse output mode (tabnmd2 to tabnmd0 bits = 011) in the one-shot pulse output mode, 16- bit timer/event counter ab waits for a trigger when the tabnctl0.tabnce bit is set to 1. when the valid edge of an external trigger input (trgbn) is detected, 16-bit timer/event counter ab starts counting, and outputs a one-shot pul se from the tobn1 to tobn3 pins. t he tobn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). instead of the external trigger input, a software trigger can also be generated to output the pulse. figure 7-24. configuration in one-shot pulse output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttbncc0 signal tobn3 pin inttbncc3 signal tobn0 pin trgbn pin (external trigger input) transfer s r s r tabnccr1 register ccr1 buffer register match signal tobn1 pin inttbncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer tobn2 pin inttbncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) evtbn pin (external event count input) internal count clock edge detector count clock selection remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 358 figure 7-25. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tabnce bit external trigger input (trgbn pin input) tabnccr0 register inttbncc0 signal tobn0 pin output tabnccr1 register inttbncc1 signal tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 359 when the tabnce bit is set to 1, 16-bit timer/event counter ab waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a one-shot pul se from the tobnb pin. after the one-shot pulse is output, the 16-bit counter is set to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bi t counter starts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tabnccrb register) count clock cycle active level width = (set value of tabnccr0 register ? set value of tabnccrb register + 1) count clock cycle the compare match interrupt request signal inttbncc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer regist er. the compare match interrupt request signal inttbnccb is generated when the count value of the 16-bit counter matches the va lue of the ccrb buffer register. the valid edge of an external trigger input (trgbn) or se tting the software trigger (tabnctl1.tabnest bit) to 1 is used as the trigger. remark n = 0, 1, b = 1 to 3 figure 7-26. setting of registers in one-shot pulse output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1. (b) tabn control register 1 (tabnctl1) 0 0/1 0/1 0 0 tabnctl1 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest 0, 1, 1: one-shot pulse output mode
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 360 figure 7-26. register setting in one-shot pulse output mode (2/3) (c) tabn i/o control register 0 (tabnioc0) 0/1 0/1 0/1 0/1 0/1 tabnioc0 0: disable tobn0 pin output 1: enable tobn0 pin output setting of tobn0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn1 pin output 1: enable tobn1 pin output setting of tobn1 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 setting of tobn3 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn2 pin output 1: enable tobn2 pin output setting of tobn2 pin output level while waiting for external trigger 0: low level 1: high level 0: disable tobn3 pin output 1: enable tobn3 pin output tobnb pin output 16-bit counter ? when tabnolb bit = 0 tobnb pin output 16-bit counter ? when tabnolb bit = 1 (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external trigger input (trgbn pin) select valid edge of external event count input (evtbn pin) 0/1 0/1 0/1 tabnees0 tabnets1 tabnets0 tabnees1 (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 361 figure 7-26. register setting in one-shot pulse output mode (3/3) (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register and d b to the tabnccrb register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d b ? d 0 + 1) count clock cycle output delay period = d b count clock cycle caution one-shot pulses are not output even in the one-shot pulse output mode, if the value set in the tabnccrb register is greater than that set in the tabnccr0 register. remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the one-shot pulse output mode. 2. n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 362 (1) operation flow in one-shot pulse output mode figure 7-27. software processing flow in one-shot pulse output mode (1/2) d 00 d 00 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> ffffh 16-bit counter 0000h tabnce bit external trigger input (trgbn pin input) tabnccr0 register inttbncc0 signal tobn0 pin output tabnccr1 register inttbncc1 signal tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 363 figure 7-27. software processing flow in one-shot pulse output mode (2/2) start stop tabnce bit = 1 tabnce bit = 0 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr3 registers initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time as when counting starts (tabnce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <2> count operation stop flow setting of tabnccr0 to tabnccr3 registers <2> tabnccr0 to tabnccr3 register setting change flow as rewriting the tabnccra register immediately forwards to the ccra buffer register, rewriting immediately after the generation of the inttbncc0 signal is recommended. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 364 (2) operation timing in one-shot pulse output mode (a) note on rewriting tabnccra register to change the set value of the tabnccra register to a smaller value, stop counting once, and then change the set value. when the overflow may occur, stop counting once, and then change the set value. d b0 d b1 d 01 d 01 d 00 d b1 d 01 d b0 d b0 d b1 d 00 d 00 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tobn0 pin output tabnccrb register inttbnccb signal tobnb pin output delay (d b0 ) active level width (d 0 ? d b0 + 1) active level width (d 01 ? d b1 + 1) active level width (d 01 ? d b1 + 1) delay (d b1 ) delay (10000h + d b1 ) external trigger input (trgbn pin input) when the tabnccr0 register is rewritten from d 00 to d 01 and the tabnccrb register from d b0 to d b1 where d 00 > d 01 and d b0 > d b1 , if the tabnccrb register is rewri tten when the count va lue of the 16-bit counter is greater than d b1 and less than d b0 and if the tabnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the c ount value. the count er counts up to ffffh and then counts up again from 0000h. when the count value matches d b1 , the counter generates the inttbnccb signal and asserts the tobnb pin. when the count value matches d 01 , the counter generates the inttbncc0 signal, deasserts the tobnb pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark n = 0, 1, a = 0 to 3, b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 365 (b) generation timing of compare match interrupt request signal (inttbnccb) the generation timing of the inttbnccb signal in th e one-shot pulse output mode is different from inttbnccb signals in other mode; the inttbnccb signal is generated when the count value of the 16-bit counter matches the value of the tabnccrb register. count clock 16-bit counter tabnccrb register tobnb pin output inttbnccb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1 b = 1 to 3 usually, the inttbnccb signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tabnccrb register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the tobnb pin.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 366 7.6.5 pwm output mode (tabnmd 2 to tabnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the tobn1 to tobn3 pins when the tabnctl0.tabnce bit is set to 1. in addition, a pwm waveform with a duty fa ctor of 50% with the set value of the tabnccr0 register + 1 as half its cycle is output from the tobn0 pin. figure 7-28. configuration in pwm output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttbncc0 signal tobn3 pin inttbncc3 signal tobn0 pin transfer s r tabnccr1 register ccr1 buffer register match signal tobn1 pin inttbncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer tobn2 pin inttbncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff) evtbn pin (external event count input) internal count clock edge detector count clock selection remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 367 figure 7-29. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tobn0 pin output tabnccr1 register inttbncc1 signal tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 368 when the tabnce bit is set to 1, t he 16-bit counter is cleared from ffff h to 0000h, starts counting, and outputs pwm waveform from the tobnb pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tabnccrb register) count clock cycle cycle = (set value of tabnccr0 register + 1) count clock cycle duty factor = (set value of tabnccrb regist er)/(set value of tabnccr0 register + 1) the pwm waveform can be changed by rewriting the tabnccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttbncc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttbnccb is gener ated when the count value of the 16-bit counter matches the value of the ccrb buffer register. remark n = 0, 1 a = 0 to 3 b = 1 to 3 figure 7-30. setting of registers in pwm output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1. (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 100 tabnmd2 tabnmd1tabnmd0 tabneee tabnest 1, 0, 0: pwm output mode 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count with external event count input signal
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 369 figure 7-30. setting of registers in pwm output mode (2/3) (c) tabn i/o control register 0 (tabnioc0) tobnb pin output 16-bit counter ? when tabnolb bit = 0 tobnb pin output 16-bit counter ? when tabnolb bit = 1 0/1 0/1 0/1 0/1 0/1 tabnioc0 0: disable tobn0 pin output 1: enable tobn0 pin output setting of tobn0 pin output level before count operation 0: low level 1: high level 0: disable tobn1 pin output 1: enable tobn1 pin output setting of tobn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 setting of tobn3 pin output level before count operation 0: low level 1: high level 0: disable tobn2 pin output 1: enable tobn2 pin output setting of tobn2 pin output level before count operation 0: low level 1: high level 0: disable tobn3 pin output 1: enable tobn3 pin output (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input (evtbn pin). 0/1 0 0 tabnees0 tabnees1 tabnets0 tabnets1 (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 370 figure 7-30. register setting in pwm output mode (3/3) (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register and d b to the tabnccrb register, t he cycle and active level of the pwm waveform are as follows. pwm waveform cycle = (d 0 + 1) count clock cycle pwm waveform active level width = d b count clock cycle remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the pwm output mode. 2. n = 0, 1 b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 371 (1) operation flow in pwm output mode figure 7-31. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register ccr0 buffer register inttbncc0 signal tobn0 pin output tabnccr1 register ccr1 buffer register inttbncc1 signal tobn1 pin output tabnccr2 register ccr2 buffer register inttbncc2 signal tobn2 pin output tabnccr3 register ccr3 buffer register inttbncc3 signal tobn3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 372 figure 7-31. software processing flow in pwm output mode (2/2) start <1> count operation start flow tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr1 registers initial setting of these registers is performed before setting the tabnce bit to 1. only writing of the tabnccr1 register must be performed when the set duty factor is only changed after writing the tabnccr2 and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. writing same value (same as preset value of the tabnccr1 register) to the tabnccr1 register is necessary only when the set duty factor of tobn2 and tobn3 pin outputs is changed. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. only writing of the tabnccr1 register must be performed when the set duty factor of tobn1 pin is only changed. when counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. counting is stopped. the tabncks0 to tabncks2 bits can be set at the same time as when counting is enabled (tabnce bit = 1). writing of the tabnccr1 register must be performed after writing the tabnccr0, tabnccr2, and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer registers. writing same value (same as preset value of the tabnccr1 register) to the tabnccr1 register is necessary only when the set cycle is changed. <2> tabnccr0 to tabnccr3 register setting change flow <3> tabnccr0 register setting change flow <4> tabnccr1 to tabnccr3 register setting change flow <5> tabnccr2, tabnccr3 register setting change flow <6> tabnccr1 register setting change flow <7> count operation stop flow tabnce bit = 0 setting of tabnccr2 and tabnccr3 registers setting of tabnccr1 register setting of tabnccr2 and tabnccr3 registers setting of tabnccr1 register stop setting of tabnccr1 register setting of tabnccr0 register setting of tabnccr1 register setting of tabnccr0, tabnccr2, and tabnccr3 registers tabnccr1 register when the counter is cleared after setting, the value of the tabnccra register is transferred to the ccra buffer register. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 373 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tabnccr1 register last. rewrite the tabnccra register after writing the tabnccr1 register after the inttbncc0 signal is detected. ffffh 16-bit counter 0000h tabnce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tabnccr0 register ccr0 buffer register inttbncc0 signal tabnccr1 register ccr1 buffer register inttbncc1 signal tobn1 pin output tabnccr2 register ccr2 buffer register inttbncc2 signal tobn2 pin output tabnccr3 register ccr3 buffer register inttbncc3 signal tobn3 pin output tobn0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 374 to transfer data from the tabnccra register to the ccra buffer register, the tabnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tabnccr0 register, set the active level width to the tabnccr2 and tabnccr3 registers, and then set an active level width to the tabnccr1 register. to change only the cycle of the pwm waveform, first set a cycle to the tabnccr0 register, and then write the same value (same as preset value of t he tabnccr1 register) to the tabnccr1 register. to change only the active level width (duty factor) of pwm waveform, first set the active level to the tabnccr2 and tabnccr3 registers, and then set an active level to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the tobn1 pin, only the tabnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the tobn2 and tobn3 pins, first set an active level width to the tabnccr2 and tabnccr3 registers, and then write the same value (same as preset value of the tabnccr1 register) to the tabnccr1 register. after the tabnccr1 register is written, the value wr itten to the tabnccra register is transferred to the ccra buffer register in synchronization with the ti ming of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. to write the tabnccr0 to tabnccr3 registers again a fter writing the tabnccr1 register once, do so after the inttbncc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tabnccra register to the ccra buffer register conflicts with writing the tabnccra register. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 375 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tabnccrb register to 0000h. the 16-bit counter is cleared to 0000h and the inttbncc0 and inttbnccb signals are generate d at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrb register inttbncc0 signal inttbnccb signal tobnb pin output d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 note note note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1, b = 1 to 3 to output a 100% waveform, set a value of (set value of tabnccr0 register + 1) to the tabnccrb register. if the set value of the tabnccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tabnce bit tabnccr0 register tabnccrb register inttbncc0 signal inttbnccb signal tobnb pin output d 0 ? 1d 0 ? 1 note note note the timing is actually delayed by one operating clock (f xx ). remark n = 0, 1, b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 376 (c) generation timing of compare match interrupt request signal (inttbnccb) the timing of generation of the inttbnccb signal in the pwm output mode differs from the timing of inttbnccb signals in other mode; the inttbnccb signal is generated when the count value of the 16-bit counter matches the value of the tabnccrb register. count clock 16-bit counter ccrb buffer register tobnb pin output inttbnccb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 note note note actually, the timing is delayed by one operating clock (f xx ). remark n = 0, 1 b = 1 to 3 usually, the inttbnccb signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tabnccrb register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the tobnb pin.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 377 7.6.6 free-running timer mode (tabnmd2 to tabnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter ab starts counting when the tabnctl0.tabnce bit is set to 1. at this time, the tabnccra register can be used as a compare register or a capture register, depending on the setting of the tabnopt0.tabnccsa bit. figure 7-32. configuration in free-running timer mode tobn3 pin note tobn2 pin note tobn1 pin note tobn0 pin inttbnov signal tabnccsa bit (capture/compare selection) inttbncc3 signal inttbncc2 signal inttbncc1 signal inttbncc0 signal tibn3 pin note (capture trigger input) tabnccr3 register (capture) evtbn pin (external event count input) internal count clock tabnce bit tibn1 pin note (capture trigger input) tibn2 pin note (capture trigger input) tabnccr0 register (capture) tabnccr1 register (capture) tabnccr2 register (capture) tabnccr3 register (compare) tabnccr2 register (compare) tabnccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tabnccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector tibn0 pin note (capture trigger input) note because the capture trigger input pin (tibnb) and timer output pin (tobnb) share the same alternate- function pin, the two functions cannot be used at the same time. remark n = 0, 1, a = 0 to 3, b = 1 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 378 ? compare operation when the tabnce bit is set to 1, 16-bit timer/event counter ab starts counting, and the output signals of the tobn0 to tobn3 pins are inverted. when the count valu e of the 16-bit counter later matches the set value of the tabnccra register, a compare match interrupt reque st signal (inttbncca) is generated, and the output signals of the tobn0 to tobn3 pins are inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttbnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tabnopt0.tabnov f bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. the tabnccra register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected at that time, and compared with the count value. remark n = 0, 1 a = 0 to 3 figure 7-33. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output inttbnov signal tabnovf bit tobn0 pin output tabnccr1 register inttbncc1 signal tabnce bit tabnccr0 register inttbncc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 379 ? capture operation when the tabnce bit is set to 1, t he 16-bit counter starts counting. when the valid edge input to the tibna pin is detected, the count val ue of the 16-bit counter is stored in t he tabnccra register, and a capture interrupt request signal (inttbncca) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttbnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tabnopt0.tabnov f bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 7-34. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tibn2 pin input tabnccr2 register inttbncc2 signal tibn3 pin input tabnccr3 register inttbncc3 signal inttbnov signal tabnovf bit tibn1 pin input tabnccr1 register inttbncc1 signal tabnce bit tibn0 pin input tabnccr0 register inttbncc0 signal remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 380 figure 7-35. register setting in free-running timer mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1 (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 101 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest 1, 0, 1: free-running timer mode 0: operate with count clock selected by tabncks0 to tabncks2 bits 1: count on external event count input signal
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 381 figure 7-35. register setting in free-running timer mode (2/3) (c) tabn i/o control register 0 (tabnioc0) 0/1 0/1 0/1 0/1 0/1 tabnioc0 0: disable tobn0 pin output 1: enable tobn0 pin output 0: disable tobn1 pin output 1: enable tobn1 pin output setting of tobn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 setting of tobn3 pin output level before count operation 0: low level 1: high level 0: disable tobn2 pin output 1: enable tobn2 pin output setting of tobn2 pin output level before count operation 0: low level 1: high level 0: disable tobn3 pin output 1: enable tobn3 pin output setting of tobn0 pin output level before count operation 0: low level 1: high level (d) tabn i/o control register 1 (tabnioc1) 0/1 0/1 0/1 0/1 0/1 tabnioc1 select valid edge of tibn0 pin input select valid edge of tibn1 pin input 0/1 0/1 0/1 tabnis2 tabnis1 tabnis0 tabnis3 tabnis6 tabnis5 tabnis4 tabnis7 select valid edge of tibn2 pin input select valid edge of tibn3 pin input
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 382 figure 7-35. register setting in free-running timer mode (3/3) (e) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input (evtbn pin) 0/1 0 0 tabnees0 tabnets1 tabnets0 tabnees1 (f) tabn option register 0 (tabnopt0) 0/1 0/1 0/1 0/1 0 tabnopt0 overflow flag specifies if tabnccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tabnccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tabnccs0 tabnovf tabnccs1 tabnccs2 tabnccs3 specifies if tabnccr2 register functions as capture or compare register 0: compare register 1: capture register specifies if tabnccr3 register functions as capture or compare register 0: compare register 1: capture register tabncms tabncuf (g) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. (h) tabn capture/compare register s 0 to 3 (tabnccr0 to tabnccr3) these registers function as captur e registers or compare registers depending on the setting of the tabnopt0.tabnccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tibna pin is detected. when the registers function as compare registers and when d a is set to the tabnccra register, the inttbncca signal is generated when the counter reaches (d a + 1), and the output signals of the tobn0 to tobn3 pins are inverted. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 383 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-36. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc 0 signal tobn0 pin output tabnccr1 register inttbncc 1 signal tobn1 pin output tabnccr2 register inttbncc 2 signal tobn2 pin output tabnccr3 register inttbncc 3 signal tobn3 pin output inttbnov signal tabnovf bit remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 384 figure 7-36. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tabnce bit = 1 read tabnopt0 register (check overflow flag). register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnopt0 register, tabnccr0 to tabnccr3 registers initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time as when counting starts (tabnce bit = 1). start execute instruction to clear tabnovf bit (clr tabnovf). <1> count operation start flow <2> overflow flag clear flow tabnce bit = 0 counter is initialized and counting is stopped by clearing tabnce bit to 0. stop <3> count operation stop flow tabnovf bit = 1 no yes remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 385 (b) when using capture/compare register as capture register figure 7-37. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tabnce bit tibn2 pin input tabnccr2 register inttbncc2 signal tibn3 pin input tabnccr3 register inttbncc3 signal inttbnov signal tabnovf bit tibn1 pin input tabnccr1 register inttbncc1 signal tibn0 pin input tabnccr0 register inttbncc0 signal remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 386 figure 7-37. software processing flow in fr ee-running timer mode (c apture function) (2/2) tabnce bit = 1 read tabnopt0 register (check overflow flag). register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc1 register, tabnopt0 register initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time as when counting starts (tabnce bit = 1). start execute instruction to clear tabnovf bit (clr tabnovf). <1> count operation start flow <2> overflow flag clear flow tabnce bit = 0 counter is initialized and counting is stopped by clearing tabnce bit to 0. stop <3> count operation stop flow tabnovf bit = 1 no yes remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 387 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter ab is used as an interval timer with the tabnccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttbncca signal has been detected. d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttbncc0 signal tobn0 pin output tabnccr1 register inttbncc1 signal tobn1 pin output tabnccr2 register inttbncc2 signal tobn2 pin output tabnccr3 register inttbncc3 signal tobn3 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30 ) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11 remark n = 0, 1, a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 388 when performing an interval operation in the free-running timer mode, four intervals can be set with one channel. to perform the interval operation, the value of the corresponding tabnccra register must be re-set in the interrupt servicing that is executed when the inttbncca signal is detected. the set value for re-setting the tabnccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 389 (b) pulse width measurement with capture register when pulse width measurement is performed with the tabnccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttbncca signal has been detected and for calculating an interval. d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tabnce bit tibn0 pin input tabnccr0 register inttbncc0 signal tibn2 pin input tabnccr2 register inttbncc2 signal tibn3 pin input tabnccr3 register inttbncc3 signal inttbnov signal tabnovf bit tibn1 pin input tabnccr1 register inttbncc1 signal
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 390 when executing pulse width measurement in the fr ee-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be ca lculated by reading the value of the tabnccra register in synchronization with the inttbncca si gnal, and calculating the difference between the read value and the previously read value. remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 391 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tabnce bit tibn0 pin input tabnccr0 register tibn1 pin input tabnccr1 register inttbnov signal tabnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tabnccr0 register (setting of t he default value of the tibn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tibn1 pin input). <3> read the tabnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tabnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark n = 0, 1 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 392 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tabnce bit inttbnov signal tabnovf bit tabnovf0 flag note tibn0 pin input tabnccr0 register tabnovf1 flag note tibn1 pin input tabnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tabnovf0 and tabnovf1 flags are set on the internal ram by software. <1> read the tabnccr0 register (setting of t he default value of the tibn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tibn1 pin input). <3> an overflow occurs. set the tabnovf0 and tabnovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tabnccr0 register. read the tabnovf0 flag. if the tabnovf0 flag is 1, clear it to 0. because the tabnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tabnccr1 register. read the tabnovf1 flag. if the tabnovf1 flag is 1, clear it to 0 (the tabnovf0 flag is cleared in <4>, and the tabnovf1 flag remains 1). because the tabnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 393 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tabnce bit inttbnov signal tabnovf bit tabnovf0 flag note tibn0 pin input tabnccr0 register tabnovf1 flag note tibn1 pin input tabnccr1 register d 10 l d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tabnovf0 and tabnovf1 flags are set on the internal ram by software. <1> read the tabnccr0 register (setting of t he default value of the tibn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tibn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tabnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tabnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tabnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tabnovf1 flag. if the tabnovf1 flag is 1, clear it to 0. because the tabnovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 394 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tabnce bit tibna pin input tabnccra register inttbnov signal tabnovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width in the free-running timer mode. <1> read the tabnccra register (setting of t he default value of the tibna pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tabnccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark n = 0, 1, a = 0 to 3 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 395 example when capture trigger interval is long ffffh 16-bit counter 0000h tabnce bit tibna pin input tabnccra register inttbnov signal tabnovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tabnccra register (setting of t he default value of the tibna pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tabnccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark n = 0, 1 a = 0 to 3 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tabnovf bit to 0 with the clr instruction after reading the tabnovf bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the tabnopt0 register after reading the tabnovf bit when it is 1.
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 396 7.6.7 pulse width measurement mode (tabnmd2 to tabnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter ab starts counting when the tabnctl0.tabnce bit is set to 1. each time the valid edge input to the ti bna pin has been detected, the co unt value of the 16-bit counter is stored in the tabnccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readi ng the tabnccra register after a capture interrupt request signal (inttbncca) occurs. as shown in figure 7-39, select either of the tibn0 to tibn3 pins as the capt ure trigger input pin. specify ?no edge detection? by using the tabnioc1 register for the unused pins. figure 7-38. configuration in pulse width measurement mode inttbnov signal inttbncc0 signal inttbncc1 signal inttbncc2 signal inttbncc3 signal tibn3 pin (capture trigger input) tabnccr3 register (capture) evtbn pin (external event count input) internal count clock tabnce bit tibn1 pin (capture trigger input) tibn2 pin (capture trigger input) tabnccr0 register (capture) tabnccr1 register (capture) tabnccr2 register (capture) 16-bit counter clear edge detector edge detector edge detector edge detector edge detector count clock selection tibn0 pin (capture trigger input) remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 397 figure 7-39. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tabnce bit tibna pin input tabnccra register inttbncca signal inttbnov signal tabnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0, 1 a = 0 to 3 when the tabnce bit is set to 1, the 16-bit counter starts counting. when t he valid edge input to the tibna pin is later detected, the count value of the 16-bit counter is stored in the tabnc cra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttbncca) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input even when the 16-bit coun ter counted up to ffffh, an overflow interrupt request signal (inttbnov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tabnopt0.tabnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tabnovf bit set (1) count + captured value) count clock cycle remark n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 398 figure 7-40. register setting in pu lse width measurement mode (1/2) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note setting is invalid when the tabnctl1.tabneee bit = 1. (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 110 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tabncks0 to tabncks2 bits 1: count external event count input signal (c) tabn i/o control register 1 (tabnioc1) 0/1 0/1 0/1 0/1 0/1 tabnioc1 select valid edge of tibn0 pin input select valid edge of tibn1 pin input 0/1 0/1 0/1 tabnis2 tabnis1 tabnis0 tabnis3 tabnis6 tabnis5 tabnis4 tabnis7 select valid edge of tibn2 pin input select valid edge of tibn3 pin input (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input (evtbn pin) 0/1 0 0 tabnees0 tabnets1 tabnets0 tabnees1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 399 figure 7-40. register setting in pu lse width measurement mode (2/2) (e) tabn option register 0 (tabnopt0) 00000 tabnopt0 overflow flag 0 0 0/1 tabnccs0 tabnovf tabncuf tabncms tabnccs1 tabnccs2 tabnccs3 (f) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. (g) tabn capture/compare register s 0 to 3 (tabnccr0 to tabnccr3) these registers store the count valu e of the 16-bit counter when the valid edge input to the tibna pin is detected. remarks 1. tabn i/o control register 0 (tabnioc0) is not used in the puls e width measurement mode. 2. n = 0, 1 a = 0 to 3
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 400 (1) operation flow in pul se width measurement mode figure 7-41. software processing flow in pulse width measurement mode tabnce bit = 1 tabnce bit = 0 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc1 register, tabnioc2 register, tabnopt0 register initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time as when counting starts (tabnce bit = 1). the counter is initialized and counting is stopped by clearing the tabnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow <1> <2> ffffh 16-bit counter 0000h tabnce bit tibn0 pin input tabnccr0 register inttbncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0, 1
chapter 7 16-bit timer/event counter ab (tab) user?s manual u18279ej3v0ud 401 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tabnovf bit to 0 with the clr instruction after reading the tabnovf bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the tabnopt0 register after reading the tabnovf bit when it is 1.
user?s manual u18279ej3v0ud 402 chapter 8 16-bit timer/event counter t (tmt) timer t (tmt) is a 16-bit timer/event counter. an encoder count function and other functions are added to the timer aa (taa). however, tmt does not have a function to operate with an external event count i nput when it operates in the interval timer mode. the v850e/if3 and v850e/ig3 incorporate tmt0 and tmt1. 8.1 overview the tmtn channels are outlined below (n = 0, 1). table 8-1. tmtn overview item tmt0 tmt1 clock selection 8 ways 8 ways capture trigger input pin note 1 2 external event count input pin note 2 1 external trigger input pin note 2 1 encoder input pin note 1 2 encoder clear input pin note 2 1 timer counter 1 1 capture/compare register 2 note 3 2 capture/compare match interrupt request signal 2 note 3 2 overflow interrupt request signal 1 1 encoder clear interrupt request signal note 1 1 timer output pin note 4 2 notes 1. v850e/if3: none v850e/ig3: 2 2. v850e/if3: none v850e/ig3: 1 3. in the v850e/if3, compare function only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 403 8.2 functions the tmtn functions that can be implemented differ from on e channel to another, as shown in the table below (n = 0, 1). table 8-2. tmtn functions function tmt0 tmt1 interval timer external event counter note 1 external trigger pulse output note 1 one-shot pulse output note 1 pwm output note 1 free-running timer note 2 pulse width measurement triangular-wave pwm output mode note 1 encoder count function note 1 notes 1. v850e/if3: v850e/ig3: 2. in the v850e/if3, compare function only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 404 8.3 configuration tmtn includes the following hardware (n = 0, 1). table 8-3. configuration of tmtn item configuration timer register 16-bit counter 1 registers tmtn capture/compare re gisters 0, 1 (ttnccr0, ttnccr1) tmtn counter read buffer register (ttncnt) tmtm counter write register (ttmtcw) ccr0 and ccr1 buffer registers timer input 2 in total (tit00 note 1 , tit01 note 1 , tit10, tit11, evtt0 note 1 , evtt1, tenc00 note 1 , tenc01 note 1 , tenc10, tenc11, tecr0 note 1 , tecr1 pins) note 2 timer output 4 in total (tot00 note 1 , tot01 note 1 , tot10, tot11 pins) note 2 control registers tmtn control re gisters 0, 1 (ttnctl0, ttnctl1) tmtm control register 2 (ttmctl2) tmtm i/o control registers 0 to 3 (ttmioc0 to ttmioc3) tmtn option register 0 (ttnopt0) tmtm option register 1 (ttmopt1) tmtm capture input select register (ttislm) notes 1. v850e/ig3 only 2. tit00/tecr0 and tit10/tecr1 pins function alternately as capture tr igger input pins (tit00, tit10), encoder clear input pins (tecr0, tecr1), and timer output pins (tot00, tot10). tenc00/evtt0 and tenc10/evtt1 pins function al ternately as encoder input pins (tenc00, tenc10), external event count input pins (evtt0, evtt1), and external trigger input pins (evtt0, evtt1). tit01/tenc01 and tit11/tenc11 pins function alternately as capture tr igger input pins (tit01, tit11), encoder input pins (tenc01, tenc11), and timer output pins (tot01, tot11). remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 405 figure 8-1. block diagram of tmt0 for v850e/if3 selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 internal bus internal bus tt0cnt tt0ccr0 ccr1 buffer register tt0ccr1 16-bit counter ccr0 buffer register counter control clear intttiov0 controller inttteqc00 inttteqc01 remark f xx : peripheral clock
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 406 figure 8-2. block diagram of tmt1 for v850e/if3 and tmt0 and tmt1 for v850e/ig3 selector selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 internal bus internal bus ttmcnt ttmtcw note ttmccr0 ccr1 buffer register ttmccr1 16-bit counter ccr0 buffer register counter control clear intttiovm output controller inttteqcm0 totm0 totm1 inttteqcm1 inttiecm tencm1/titm1 tecrm/titm0 tencm0/evttm selector sampling clock f xx f xx /4 f xx /8 f xx /16 edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator f xx /32 f xx /64 note the initial value set from the ttmtcw register to t he 16-bit counter is valid only in the encoder compare mode. rewrite the ttmtcw register when the ttmctl0.ttmce bit = 0. the value of the ttmtcw register is transferred to the 16-bit counter when the ttmce bit = 1. remarks 1. f xx : peripheral clock 2. for the noise eliminator, see 4.6 noise eliminator . 3. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 407 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the ttncnt register. when the ttnctl0.ttnce bit = 0, the va lue of the 16-bit counter is ffffh. if the ttncnt register is read at this time, 0000h is read. reset sets the ttnce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the ttnccr0 register is used as a compare regist er, the value written to the ttnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttte qcn0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is set to 0000h after reset, and the ttnccr0 register is set to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the ttnccr1 register is used as a compare regist er, the value written to the ttnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttte qcn1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is set to 0000h after reset, and the ttnccr1 register is set to 0000h. (4) edge detector this circuit detects the valid edges input to the tit00 (v850e/ig3 only), ti t01 (v850e/ig3 only), tit10, tit11, evtt0 (v850e/ig3 only), evtt1, tenc00 (v850e/ig3 onl y), tenc01 (v850e/ig3 only), tenc10, tenc11, tecr0 (v850e/ig3 only), and tecr1 pins. no edge, rising edge, falling edge, or bo th the rising and falling edges can be selected as the valid edge by using the ttmioc1, ttmioc2, and ttmioc3 registers. (5) output controller this circuit controls the output of the tot00 (v850e/ig3 only), tot01 (v850e/ig3 only), tot10, and tot11 pins. the output controller is c ontrolled by the ttmioc0 registers. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. (7) counter control the count operation is controlled by the ti mer mode selected by the ttnctl1 register.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 408 8.4 registers (1) tmtn control register 0 (ttnctl0) the ttnctl0 register is an 8-bit register that controls the operation of tmtn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the ttnctl0 register by software. ttnce tmtn operation disabled (tmtn reset asynchronously note ) tmtn operation enabled. tmtn operation start ttnce 0 1 tmtn operation control ttnctl0 (n = 0, 1) 0 0 0 0 ttncks2 ttncks1 ttncks0 654321 after reset: 00h r/w address: tt0ctl0 fffff580h, tt1ctl0 fffff5c0h <7> 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 ttncks2 0 0 0 0 1 1 1 1 internal count clock selection ttncks1 0 0 1 1 0 0 1 1 ttncks0 0 1 0 1 0 1 0 1 note the ttnopt0.ttnovf bit and the 16-bit counter are reset simultaneously. moreover, timer outputs (tot00 (v850e/ig3 only), tot01 (v850e/ig3 only), to t10, and tot11 pins) are reset to the ttmioc0 register set status at the same ti me as the 16-bit counter is reset (v850e/if3: m = 1, v850e/ig3: m = 0, 1). cautions 1. set the ttncks2 to ttncks0 bits when the ttnce bit = 0. when the value of the ttnce bit is changed from 0 to 1, the ttncks2 to ttncks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 409 (2) tmtn control register 1 (ttnctl1) the ttnctl1 register is an 8-bit register that controls the tmtn operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) 0 ttnctl1 ttmest note ttmeee note 0 ttnmd3 ttnmd2 ttnmd1 ttnmd0 654321 after reset: 00h r/w address: tt0ctl1 fffff581h, tt1ctl1 fffff5c1h 7 0 ttmest note 0 1 software trigger control generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the ttmest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the ttmest bit as the trigger. disable operation with external event count input (evttm pin). (perform counting with the count clock selected by the ttmctl0.ttmcks0 to ttmctl0.ttmcks2 bits.) ttmeee note 0 1 count clock selection the ttmeee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. enable operation with external event count input (evttm pin). (perform counting at the valid edge of the external event count input signal (evttm pin).) ? the read value of the ttmest bit is always 0. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode triangular-wave pwm output mode encoder compare mode setting prohibited timer mode selection ttnmd3 0 0 0 0 0 0 0 0 1 other than above ttnmd2 0 0 0 0 1 1 1 1 0 ttnmd1 0 0 1 1 0 0 1 1 0 ttnmd0 0 1 0 1 0 1 0 1 0 v850e/if3 n = 0, 1 m = 1 v850e/ig3 n = 0, 1 m = 0, 1 note in the v850e/if3, this bit can be set only in tmt1. be sure to set bits 5 and 6 of tmt0 to ?0?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 410 (2/2) cautions 1. the ttmest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. the ttmeee bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, pwm output mode , free-running timer mode, pulse width measurement mode, or triangular-wave pwm outpu t mode. in any other mode, writing 1 to this bit is ignored. 3. external event count input (evttm) or enc oder inputs (tencm0, tencm1) is selected in the external event count mode or encoder co mpare mode regardless of the value of the ttmeee bit. 4. set the ttmeee and ttnmd3 to ttnmd0 bits when the ttnctl0.ttnce bit = 0. (the same value can be written when the ttnce bit = 1.) the operation is not guaranteed when rewriting is performed with the ttnce bit = 1. if rewriting was mistakenly performed, clear the ttnce bit to 0 and then set the bits again. 5. be sure to set bits 4 and 7 to ?0?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 411 (3) tmtm control register 2 (ttmctl2) the ttmctl2 register is an 8-bit register that controls the encoder count function operation. the ttmctl2 register is valid onl y in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution for details of each bit of the ttmctl2 register, see 8.6.9 (5) controlling bits of ttmctl2 register. (1/2) ttmecc ttmctl2 0 0 ttmlde ttmecm1 ttmecm0 ttmuds1 ttmuds0 654321 disables transfer of set value of ttmccr0 to 16-bit counter in case of underflow. enables transfer of set value of ttmccr0 to 16-bit counter in case of underflow. ttmlde 0 1 transfer setting to 16-bit counter after reset: 00h r/w address: tt0ctl2 fffff582h note , tt1ctl2 fffff5c2h 0 7 the 16-bit counter is not cleared to 0000h when its count value matches value of ccr1 register. the 16-bit counter is cleared to 0000h when its count value matches value of ccr1 register. ttmecm1 0 1 control of encoder clear operation 1 the 16-bit counter is not cleared to 0000h when its count value matches value of ccr0 register. the 16-bit counter is cleared to 0000h when its count value matches value of ccr0 register. ttmecm0 0 1 control of encoder clear operation 0 v850e/if3 m = 1 v850e/ig3 m = 0, 1 normal operation holds count value of 16-bit counter when ttmctl0.ttmce bit = 0. ttmecc 0 1 encoder counter control note v850e/ig3 only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 412 (2/2) when valid edge of tencm0 input is detected counts down when tencm1 = high level. counts up when tencm1 = low level. counts up when valid edge of tencm0 input is detected. counts down when valid edge of tencm1 input is detected. counts down when rising edge of tencm0 input is detected. counts up when falling edge of tencm0 input is detected. however, count operation is performed only when tencm1 = low level. both rising and falling edges of tencm0 and tencm1 are detected. count operation is automatically identified by combination of edge detection and level detection. ttmuds1 0 0 1 1 up/down count selection ttmuds0 0 1 0 1 cautions 1. the ttmecc bit is valid only in the en coder compare mode. in any other mode, writing ?1? to this bit is ignored. if the ttmctl0.ttmce bit is cleared to 0 while the ttmecc bit = 1, the values of the timer/counter and capture registers ( ttmccr0 and ttmccr1), and the ttmopt1, ttmeuf, ttmeof, and ttmesf flags are retained. if the ttmce bit is set from 0 to 1 when the ttmecc bit = 1, the value of the ttmtcw register is not transferred to the 16-bit counter. 2. the ttmlde bit is valid only when the ttme cm1 and ttmecm0 bits = 00, 01. writing ?1? to this bit is ignored when the ttmecm1 and ttmecm0 bits = 10, 11. 3. the edge detection of the tencm0 and tencm1 inputs specified by the ttmioc3.ttmeis1 and ttmioc3.ttmeis0 bits is in valid and fixed to both the rising and falling edges when the ttmuds1 and ttmuds0 bits = 10, 11. 4. set the ttmlde, ttmecm1, ttmecm0, ttmuds1, and ttmuds0 bits when the ttmctl0.ttmce bit = 0 (the same value can be written to these bits when the ttmce bit = 1). if the value of these bits is changed wh en the ttmce bit = 1, the operation cannot be guaranteed. if it is changed by mistake, clear the ttmce bit and then set the correct value. 5. be sure to set bits 5 and 6 to ?0?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 413 (4) tmtm i/o control register 0 (ttmioc0) the ttmioc0 register is an 8-bit register that controls the timer output (totm0, totm1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 414 0 ttmol1 0 1 totm1 pin output level setting note 2 totm1 pin starts output at high level. totm1 pin starts output at low level. ttmioc0 0 0 0 ttmol1 ttmoe1 ttmol0 ttmoe0 6543<2>1 ttmoe1 0 1 totm1 pin output setting timer output prohibited ? low level is output from the totm1 pin when the ttmol1 bit = 0. ? high level is output from the totm1 pin when the ttmol1 bit = 1. timer output enabled (a pulse is output from the totm1 pin.) ttmol0 0 1 totm0 pin output level setting note 2 totm0 pin starts output at high level. totm0 pin starts output at low level. ttmoe0 0 1 totm0 pin output setting timer output prohibited ? low level is output from the totm0 pin when the ttmol0 bit = 0. ? high level is output from the totm0 pin when the ttmol0 bit = 1. timer output enabled (a pulse is output from the totm0 pin.) 7 <0> after reset: 00h r/w address: tt0ioc0 fffff583h note 1 , tt1ioc0 fffff5c3h v850e/if3 m = 1 v850e/ig3 m = 0, 1 notes 1. v850e/ig3 only 2. the output level of the timer output pins (totm0 , totm1) in modes other than the triangular-wave pwm output mode, which is specified by t he ttmola bit, is as follows (a = 0, 1). ttmce bit totma pin output 16-bit counter ttmce bit totma pin output 16-bit counter ? when ttmola bit = 0 ? when ttmola bit = 1 for the output level in the triangular-wave pwm output mode, see figure 8-44 basic timing in triangular-wave pwm output mode . cautions 1. if the setting of the ttmioc0 register is changed when totm0 and totm1 outputs are set for the port mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance stat e, noting changes in the pin status. 2. rewrite the ttmol1, ttmoe1, ttmol0, a nd ttmoe0 bits when the ttmctl0.ttmce bit = 0. (the same value can be written when the ttmce bit = 1.) if rewriting was mistakenly performed, clear the ttmce bit to 0 and then set the bits again. 3. even if the ttmol0 or ttmol1 bit is ma nipulated when the ttmce, ttmoe0, and ttmoe1 bits are 0, the output level of th e totm0 and totm1 pins changes.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 415 (5) tmtm i/o control register 1 (ttmioc1) the ttmioc1 register is an 8-bit regist er that controls the valid edge fo r the capture trigger input signals (titm0, titm1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ttmis3 0 0 1 1 ttmis2 0 1 0 1 capture trigger input signal (titm1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 0 0 0 ttmis3 ttmis2 ttmis1 ttmis0 654321 ttmis1 0 0 1 1 ttmis0 0 1 0 1 capture trigger input signal (titm0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 ttmioc1 after reset: 00h r/w address: tt0ioc1 fffff584h note , tt1ioc1 fffff5c4h v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only cautions 1. rewrite the ttmis3 to ttmis0 bits when the ttmctl0.ttmce bit = 0. (the same value can be written when the ttm ce bit = 1.) if rewriting was mistakenly performed, clear the ttmce bit to 0 and then set the bits again. 2. the ttmis3 and ttmis2 bits are valid only in the free-running timer mode (only when the ttmopt0.ttmccs1 bit = 1) and the pulse width m easurement mode. in all other modes, a capture operation is not possible. the ttmis1 and ttmis0 bits are valid only in the free-running timer mode (only when the ttmopt0. ttmccs0 bit = 1) and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 416 (6) tmtm i/o control register 2 (ttmioc2) the ttmioc2 register is an 8-bit register that controls the valid edge for the external event count input signal (evttm pin) and external trigger input signal (evttm pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ttmees1 0 0 1 1 ttmees0 0 1 0 1 external event count input signal (evttm pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges 0 0 0 ttmees1ttmees0 ttmets1 ttmets0 654321 ttmets1 0 0 1 1 ttmets0 0 1 0 1 external trigger input signal (evttm pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 ttmioc2 after reset: 00h r/w address: tt0ioc2 fffff585h note , tt1ioc2 fffff5c5h v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only cautions 1. rewrite the ttmees1 , ttmees0, ttmets1, and ttmets0 bits when the ttmctl0.ttmce bit = 0. (the same value can be written when the ttmce bit = 1.) if rewriting was mistakenly performed, clear the ttmce bit to 0 and then set the bits again. 2. the ttmees1 and ttmees0 bits are valid only when the ttmctl1.ttmeee bit = 1 or when the external event count mode (the ttmctl1.ttmmd3 to tt mctl1.ttmmd0 bits = 0001) has been set. 3. the ttmets1 and ttmets0 bi ts are valid only in the extern al trigger pulse mode or one- shot pulse output mode.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 417 (7) tmtm i/o control register 3 (ttmioc3) the ttmioc3 register is an 8-bit register that controls the encoder clear function operation. the ttmioc3 register is valid only in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) ttmsce ttmioc3 ttmzcl ttmbcl ttmacl ttmecs1ttmecs0 ttmeis1 ttmeis0 654321 after reset: 00h r/w address: tt0ioc3 fffff586h note , tt1ioc3 fffff5c6h 7 0 ttmsce 0 1 encoder clear selection ? clears 16-bit counter to 0000h when valid edge of tecrm pin specified by the ttmecs1 and ttmecs0 bits is detected when the ttmsce bit = 0. ? clears 16-bit counter to 0000h when clear level conditions of the ttmzcl, ttmbcl, and ttmacl bits match input levels of the tecrm, tencm1, and tencm0 pins when ttmsce bit = 1. ? setting of the ttmzcl, ttmbcl, and ttmacl bits is valid and that of the ttmecs1 and ttmecs0 bits is invalid when the ttmsce bit = 1. encoder clear interrupt request signal (inttiecm) is not generated. ? setting of the ttmzcl, ttmbcl, and ttmacl bits is invalid and setting of the ttmecs1 and ttmecs0 bits is valid when the ttmsce bit = 0. the inttiecm signal is generated when valid edge specified by the ttmecs1 and ttmecs0 bits is detected. ? be sure to set the ttmctl2.ttmuds1 and ttmctl2.ttmuds0 bits to 10 or 11 when the ttmsce bit = 1. operation is not guaranteed if the ttmuds1 and ttmuds0 bits = 00 or 01 and the ttmsce bit = 1. clears 16-bit counter on detection of edge of encoder clear signal (tecrm pin). clears 16-bit counter on detection of clear level condition of the tencm0, tencm1, and tecrm pins. ttmzcl 0 1 clear level selection of encoder clear signal (tecrm pin) setting of the ttmzcl bit is valid only when the ttmsce bit = 1. clears low level of the tecrm pin. clears high level of the tecrm pin. ttmbcl 0 1 clear level selection of encoder input signal (tencm1 pin) setting of the ttmbcl bit is valid only when the ttmsce bit = 1. clears low level of the tencm1 pin. clears high level of the tencm1 pin. ttmacl 0 1 clear level selection of encoder input signal (tencm0 pin) setting of the ttmacl bit is valid only when the ttmsce bit = 1. clears low level of the tencm0 pin. clears high level of the tencm0 pin. v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 418 (2/2) ttmecs1 0 0 1 1 ttmecs0 0 1 0 1 valid edge setting of encoder clear signal (tecrm pin) detects no edge (clearing encoder is invalid). detects rising edge. detects falling edge. detects both edges. ttmeis1 0 0 1 1 ttmeis0 0 1 0 1 valid edge setting of encoder input signals (tencm0, tencm1 pins) detects no edge (inputting encoder is invalid). detects rising edge. detects falling edge. detects both edges. cautions 1. rewrite the ttmsce, ttmzcl, ttm bcl, ttmacl, ttmecs1, ttmecs0, ttmeis1, and ttmeis0 bits when the ttmctl0.ttmce bit = 0. (the same value can be written to these bits when the ttmce bit = 1.) if rewriting was mistakenly performed, clear the ttmce bit to 0 and then set these bits again. 2. the ttmecs1 and ttm ecs0 bits are valid only when the ttmsce bit = 0 and the encoder compare mode is set. 3. the ttmeis1 and ttmeis0 bits are valid only when the ttmctl2.ttmuds1 and ttmctl2.ttmuds0 bits = 00 or 01.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 419 (8) tmtn option register 0 (ttnopt0) the ttnopt0 register is an 8-bit register that sets the capture/compare operat ion and detects overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ttmccs1 note 0 1 ttmccr1 register capture/compare selection the ttmccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by the ttmctl0.ttmce bit = 0) 0 ttmccs1 note ttmccs0 note 0 0 0 ttnovf 654321 ttmccs0 note 0 1 ttmccr0 register capture/compare selection the ttmccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by the ttmctl0.ttmce bit = 0) ttnovf set (1) reset (0) tmtn overflow detection flag ? the ttnovf bit is set to 1 when the 16-bit counter value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (intttiovn) is generated at the same time that the ttnovf bit is set to 1. the intttiovn signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the ttnovf bit is not cleared to 0 even when the ttnovf bit or the ttnopt0 register are read when the ttnovf bit = 1. ? before clearing the ttnovf bit to 0 after generation of the intttiovn signal, be sure to confirm (by reading) that the ttnovf bit is set to 1. ? the ttnovf bit can be both read and written, but the ttnovf bit cannot be set to 1 by software. writing 1 has no effect on the operation of tmtn. overflow occurred 0 written to ttnovf bit or ttnctl0.ttnce bit = 0 7 <0> ttnopt0 after reset: 00h r/w address: tt0opt0 fffff587h, tt1opt0 fffff5c7h v850e/if3 n = 0, 1 m = 1 v850e/ig3 n = 0, 1 m = 0, 1 note in the v850e/if3, this bit can be set only in tmt1. be sure to set bits 4 and 5 of tmt0 to ?0?. cautions 1. rewrite the ttmccs1 and ttmccs0 bits wh en the ttmce bit = 0. (the same value can be written when the ttmce bit = 1.) if rewrit ing was mistakenly performed, clear the ttmce bit to 0 and then set these bits again. 2. be sure to set bits 1 to 3, 6, and 7 to ?0?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 420 (9) tmtm option register 1 (ttmopt1) the ttmopt1 register is an 8-bit register that detects the overflow, underflow, and count-up/down operation of the encoder count function. the ttmopt1 register is valid only in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. this register can be rewritten even when the ttmctl0.ttmce bit = 1. (1/2) 0 ttmopt1 0 0 0 0 ttmeuf ttmeof ttmesf 6 5 4 3 <2> <1> after reset: 00h r/w address: tt0opt1 fffff588h note , tt1opt1 fffff5c8h ttmeuf set (1) reset (0) tmtm underflow detection flag ? the ttmeuf bit is set to 1 when 16-bit counter underflows from 0000h to ffffh in encoder compare mode. ? when the ttmctl2.ttmlde bit = 1, ttmeuf bit is set to 1 when value of 16-bit counter is changed from 0000h to set value of the ttmccr0 register. ? overflow interrupt request signal (intttiovm) is generated as soon as the ttmeuf bit is set to 1. ? the ttmeuf bit is not cleared to 0 even if the ttmeuf bit or ttmopt1 register is read when the ttmeuf bit = 1. ? status of the ttmeuf bit is retained even if the ttmctl0.ttmce bit is cleared to 0 when the ttmctl2.ttmecc bit = 1. ? before clearing the ttmeuf bit to 0 after the intttiovm signal is generated, be sure to confirm (read) that the ttmeuf bit is set to 1. ? the ttmeuf bit can be read or written, but it cannot be set to 1 by software. setting this bit to 1 does not affect operation of tmtm. underflow occurs. cleared by writing to ttmeuf bit or when ttmctl0.ttmce bit = 0 7 <0> v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 421 (2/2) ttmesf 0 1 tmtm count-up/-down operation status detection flag ? this bit is cleared to 0 if the ttmctl0.ttmce bit = 0 when the ttmctl2.ttmecc bit = 0. ? status of the ttmesf bit is retained even if the ttmce bit = 0 when the ttmecc bit = 1. tmtm is counting up. tmtm is counting down. ttmeof set (1) reset (0) overflow detection flag for tmtm encoder function ? the ttmeof bit is set to 1 when 16-bit counter overflows from ffffh to 0000h in encoder compare mode. ? as soon as the ttmeof bit has been set to 1, an overflow interrupt request signal (intttiovm) is generated. at this time, the ttmopt0.ttmovf bit is not set to 1. ? the ttmeof bit is not cleared to 0 even if the ttmeof bit or ttmopt1 register is read when the ttmeof bit = 1. ? status of the ttmeof bit is retained even if the ttmctl0.ttmce bit is cleared to 0 when the ttmctl2.ttmecc bit = 1. ? before clearing the ttmeof bit to 0 after the intttiovm signal is generated, be sure to confirm (read) that the ttmeof bit is set to 1. ? the ttmeof bit can be read or written, but it cannot be set to 1 by software. writing 1 to this bit does not affect operation of tmtm. overflow occurs. cleared by writing 0 to the ttmeof bit or when the ttmctl0.ttmce bit = 0 caution be sure to set bits 3 to 7 to ?0?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 422 (10) tmtm capture input select register (ttislm) the ttislm register is used to sele ct which of titm0 or titm1 pin is used to input a capture trigger input signal when the ttmccr0 register is used as a capture register. this register can be read or written in 8-bit or 1-bit units. reset makes this register undefined. 0 ttislm 0 0 0 0 0 0 ttislm 654321 after reset: undefined r/w address: ttisl0 fffff5a4h note , ttisl1 fffff5a6h 7 0 ttislm 0 1 capture trigger input signal selection of ttmccr0 register titm0 input titm1 input v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 423 (11) tmtn capture/compare register 0 (ttnccr0) the ttmccr0 register is a 16-bit regi ster that can be used as a captur e register or compare register depending on the mode. the tt0ccr0 register of the v850e /if3 is a 16-bit registers that can only be used as a compare register. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the ttmopt0.ttmccs0 bit. in the pulse width measurement mode, the ttmccr0 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the ttnccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 ttnccr0 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tt0ccr0 fffff58ah, tt1ccr0 fffff5cah 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 424 (a) function as compare register the ttnccr0 register can be rewritten even when the ttnctl0.ttnce bit = 1. the set value of the ttnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttteqcn0) is generated. if totm0 pin output is enabled at this time, the output of the totm0 pin is inverted. when the ttnccr0 register is used as a cycle register in the interval timer mode, or when the ttmccr0 register is used as a cycle register in the external event count mode, external trigger pulse output mode, one-shot pulse output mode, pwm output mode, triangu lar-wave pwm output mode, or encoder compare mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared by setting the ttnctl0.ttnce bit to 0. (b) function as capture register when the ttmccr0 register is used as a capture regi ster in the free-running timer mode (when the ttmccr0 register is used as a captur e register), the count value of t he 16-bit counter is stored in the ttmccr0 register if the valid edge of the capture trigger input pin (titm0 pin) is detected. in the pulse- width measurement mode, the count value of the 16-bit counter is stored in the ttmccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of t he capture trigger input pin (titm0 pin) is detected. even if the capture operation and reading the ttmccr0 register co nflict, the correct value of the ttmccr0 register can be read. the capture register is cleared by setting the ttmctl0.ttmce bit to 0. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode ttnccr0 register how to write compare register interval timer compare register anytime write external event counter note 1 compare register anytime write external trigger pulse output note 1 compare register batch write note 2 one-shot pulse output note 1 compare register anytime write pwm output note 1 compare register batch write note 2 free-running timer capture/compare register anytime write pulse width measurement note 1 capture register none triangular-wave wpm output note 1 compare register batch write note 2 encoder compare note 1 compare register anytime write notes 1. in the v850e/if3, this mode can be set only in tmt1. 2. writing to the ttnccr1 register is the trigger. remark for anytime write and batch write, see 8.6 (2) anytime write and batch write .
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 425 (12) tmtn capture/compare register 1 (ttnccr1) the ttmccr1 register is a 16-bit regi ster that can be used as a captur e register or compare register depending on the mode. the tt0ccr1 register of the v850e /if3 is a 16-bit registers that can only be used as a compare register. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the ttmopt0.ttmccs1 bit. in the pulse width measurement mode, the ttmccr1 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the ttnccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 ttnccr1 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tt0ccr1 fffff58ch, tt1ccr1 fffff5cch 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 426 (a) function as compare register the ttnccr1 register can be rewritten even when the ttnctl0.ttnce bit = 1. the set value of the ttnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttteqcn1) is generated. if totm1 pin output is enabled at this time, the output of the totm1 pin is inverted. the compare register is not cleared by setting the ttnctl0.ttnce bit to 0. (b) function as capture register when the ttnccr1 register is used as a capture re gister in the free-running timer mode (when the ttmccr1 register is used as a captur e register), the count value of t he 16-bit counter is stored in the ttmccr1 register if the valid edge of the capture trigger input pin (titm1 pin) is detected. in the pulse- width measurement mode, the count value of the 16-bit counter is stored in the ttmccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of t he capture trigger input pin (titm1 pin) is detected. even if the capture operation and reading the ttmccr1 register co nflict, the correct value of the ttmccr1 register can be read. the capture register is cleared by setting the ttmctl0.ttmce bit to 0. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode ttnccr1 register how to write compare register interval timer compare register anytime write external event counter note 1 compare register anytime write external trigger pulse output note 1 compare register batch write note 2 one-shot pulse output note 1 compare register anytime write pwm output note 1 compare register batch write note 2 free-running timer capture/compare register anytime write pulse width measurement note 1 capture register none triangular-wave pwm output note 1 compare register batch write note 2 encoder compare note 1 compare register anytime write notes 1. in the v850e/if3, this mode can be set only in tmt1. 2. writing to the ttnccr1 register is the trigger. remark for anytime write and batch write, see 8.6 (2) anytime write and batch write .
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 427 (13) tmtm counter writ e register (ttmtcw) the ttmtcw register is used to set the initial value of the 16-bit counter. the ttmtcw register is valid only in the encoder compare mode. this register can be read or written in 16-bit units. rewrite the ttmtcw register when the ttmctl0.ttmce bit = 0. the value of the ttmtcw register is transferred to the 16-bit counter when the ttmce bit is set (1). reset sets this register to 0000h. ttmtcw 12 10 8 6 4 2 after reset: 0000h r/w address: tt0tcw fffff590h note , tt1tcw fffff5d0h 14 0 13 11 9 7 5 3 15 1 v850e/if3 m = 1 v850e/ig3 m = 0, 1 note v850e/ig3 only (14) tmtn counter read buffer register (ttncnt) the ttncnt register is a read buffer register t hat can read the count valu e of the 16-bit counter. if this register is read when the ttnctl0.ttnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the ttmcnt register is set to 0000h when the ttmctl2.ttmecc and ttmce bits = 0. if the ttmcnt register is read at this time , the value of the 16-bit counter (ffffh ) is not read, but 0000h is read. the ttmcnt register is not set to 0000h but the prev ious value is read when the ttmecc bit = 1 and ttmce bit = 0. the ttmecc and ttmce bits are set to 0 after reset, and the value of the ttmcnt register is set to 0000h. ttncnt (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r address: tt0cnt fffff58eh, tt1cnt fffff5ceh 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 428 8.5 timer output operations the following table shows the operations and output levels of the totm0 and totm1 pins. table 8-6. timer output control in each mode operation mode totm1 pin totm0 pin interval timer mode pwm output external event count mode note none external trigger pulse output mode note external trigger pulse output one-shot pulse output mode note one-shot pulse output pwm output mode note pwm output pwm output free-running timer mode pwm output (only when compare function is used) pulse width measurement mode note none triangular-wave pwm output mode note triangular-wave pwm output encoder compare mode note none note in the v850e/if3, this mode can be set only in tmt1. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1 table 8-7. truth table of totm0 and totm1 pins under control of timer output control bits ttmioc0.ttmola bit ttmioc0.ttmoea bit ttmctl0.ttmce bit level of totma pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 429 8.6 operation the functions of tmtn that c an be implemented differ from one channel to another. the functions of each channel are shown below (n = 0, 1). table 8-8. tmtm specifications in each mode operation ttmctl1.ttmest bit (software trigger bit) evttm pin (external trigger input) capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode invalid invalid compare only anytime write external trigger pulse output mode va lid valid compare only batch write one-shot pulse output mode valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switchable anytime write pulse width measurement mode invalid invalid capture only not applicable triangular-wave pwm output mode invalid invalid compare only batch write encoder compare mode invalid invalid compare only anytime write remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 table 8-9. tmt0 specifications in each mode of v850e/if3 operation software trigger bit external trigger input capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode none external trigger pulse output mode none one-shot pulse output mode none pwm output mode none free-running timer mode invalid invalid compare only anytime write pulse width measurement mode none triangular-wave pwm output mode none encoder compare mode none remark tmt0 of the v850e/if3 does not have timer in put pins (tit00, tit01, tecr0, tenc00, tenc01, evtt0) and timer output pins (tot00, tot01). it has interrupt request signals (inttteqc00, inttteqc01) indicating a match between the value of the 16-bit counter an d the values of the tt0ccr0 and tt0ccr1 registers.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 430 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 (a) counter start operation ? in external event count mode when the ttmctl0.ttmce bit is set from 0 to 1, the 16-bit counter is set to 0000h. after that, it counts up to 0001h, 0002h, 0003h, each time the valid edge of external event count input (evttm) is detected. ? encoder compare mode the count operation is controlled by tencm0 and tencm1 phases. when the 16-bit counter initial setting is performed by transferring the set value of the ttmtcw register to the 16-bit counter and the count operation is started. (when t he ttmctl2.ttmecc bit = 0, the ttmtcw register set value is transferred to the 16-b it counter at the timing when the ttmctl0.ttmce bit changes from 0 to 1.) ? triangular-wave pwm mode the 16-bit counter starts counting from the initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h, and so on. following count up operation, the counter counts down upon a match between the 16-bit count value and the ccr0 buffer register. ? mode other than above the 16-bit counter starts counting from the initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its va lue matches the value of the compare register and cleared, when the value of the 16-bit counter is capt ured and cleared, when the edge of the encoder clear signal is detected and cleared, and when the clear level condition of the tencm0, tencm1, and tecrm pins is detected and cleared. the count operation from ffffh to 0000h that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. therefore, the inttteqcn0 and inttteqcn1 in terrupt signals ar e not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running mode, pulse width measurement mode, and encoder co mpare mode. if the counter overflows, the ttnopt0.ttnovf bit is set to 1 and an interrupt re quest signal (intttiovn) is generated in the free- running mode and pulse width measurement mode. if the counter overflows, the ttnopt1.ttneof bit is se t to 1 and an interrupt request signal (intttiovn) is generated in the encoder compare mode. note that the intttiovn signal is not generated under the following conditions. ? immediately after a count operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleared to 0000h in the pulse width measurement mode
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 431 caution after the overflow interrupt request signa l (intttiovn) has been generated, be sure to check that the overflow flag (ttnovf, ttmeof bits) is set to 1. (d) count value holding operation the value of the 16-bit counter is held by the ttm ctl2.ttmecc bit in the encoder compare mode. the value of the 16-bit counter is reset to ffffh when the ttmecc bit = 0 and ttmctl0.ttmce bit = 0. when the ttmce bit is set to 1 next time, the set value of the ttmtcw register is transferred to the 16-bit counter and the counter continues its count operation. if the ttmecc bit = 1 and ttmce bit = 0, the value of the 16-bit counter is held. when the ttmce bit is set to 1 next time, the counter resumes the count operation from the held value. (e) counter read operation during count operation the value of the 16-bit counter of tmtn can be read by using the ttncnt register during the count operation. when the ttnctl0.ttnce bit = 1, the valu e of the 16-bit counter can be read by reading the ttncnt register. if the ttmcnt register is read when the ttmctl2.ttmecc bit = 0 and ttmce bit = 0, however, it is 0000h. the held value of the ttmcnt register is read if the register is read when the ttmecc bit = 1 and ttmce bit = 0. (f) underflow operation the 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000h to ffffh in the encoder compare mode. when underflow occurs, the ttmop t1.ttmeuf bit is set to 1 and an interrupt request signal (intttiovm) is generated. (g) interrupt operation tmtn generates the following four types of interrupt request signals. ? inttteqcn0 interrupt: this signal functions as a ma tch interrupt request sig nal of the ccr0 buffer register and as a capture interrupt request signal to the ttnccr0 register. ? inttteqcn1 interrupt: this signal functions as a ma tch interrupt request sig nal of the ccr1 buffer register and as a capture interrupt request signal to the ttnccr1 register. ? intttiovn interrupt: this signal functions as an overflow interrupt request signal. ? inttiecm interrupt: this signal functions as a valid edge detection interrupt request signal of the encoder clear input (tecrm pin).
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 432 (2) anytime write and batch write the ttnccr0 and ttnccr1 registers in tmtn can be rewr itten during timer operation (ttnctl0.ttnce bit = 1), but the write method (anytime writ e, batch write) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the ttnccr0 and ttnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation (n = 0, 1). figure 8-3. flowchart of basic operation for anytime write start initial settings ? set values to ttnccra register ? timer operation enable (ttnce bit = 1) transfer values of ttnccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttteqcn1 signal output ttnccra register rewrite transfer to ccra buffer register inttteqcn0 signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0, 1 a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 433 figure 8-4. timing of anytime write d 01 d 01 d 01 d 01 0000h ttnce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter ttnccr0 register ttnccr1 register inttteqcn0 signal inttteqcn1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : set values of ttnccr0 register d 11 , d 12 : set values of ttnccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 434 (b) batch write in this mode, data is transferred all at once from the ttmccr0 and ttmccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the ttmccr1 register. whether to enable or disable the ne xt transfer timing is controlled by writing or not writing to the ttmccr1 register. in order for the set value when the ttmccr0 and ttmccr1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the ttm ccr0 register and then write to the ttmccr1 register before the 16-bit counter value and the ccr0 buffer register value match. therefore, the values of the ttmccr0 and ttmccr1 registers are transferred to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the valu e of the ccr0 buffer register. thus even when wishing only to rewrite the value of the ttmccr0 regi ster, also write the same value (same as preset value of the ttmccr1 register) to the ttmccr1 register. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 435 figure 8-5. flowchart of basic operation for batch write start initial settings ? set values to ttmccra register ? timer operation enable (ttmce bit = 1) transfer values of ttmccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of ttmccra register to ccra buffer register inttteqcm1 signal output ttmccr0 register rewrite ttmccr1 register rewrite inttteqcm0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the ttmccr1 register includes en abling of batch write. thus, rewrite the ttmccr1 register after rewriting the ttmccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 436 figure 8-6. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 ttmce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter ttmccr0 register ttmccr1 register inttteqcm0 signal inttteqcm1 signal totm1 pin output totm0 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the ttmccr1 register was not rewritten, d 03 is not transferred. 2. because the ttmccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the ttmccr0 register (d 01 ). 3. because the ttmccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the ttmccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : set values of ttmccr0 register d 11 , d 12 : set values of ttmccr1 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. 3. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 437 8.6.1 interval timer mode ( ttnmd3 to ttnmd0 bits = 0000) in the interval timer mode, an interr upt request signal (inttteqcn0) is gene rated at the interval set by the ttnccr0 register if the ttnctl0.ttnce bit is set to 1. a pwm waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the totm0 pin. the ttnccr1 register is not used in the interval timer mo de. however, the set value of the ttnccr1 register is transferred to the ccr1 buffer register, and when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttteqcn1) is generated. in addition, a pwm waveform with a duty factor of 50%, which is inverted when the inttteqcm1 signal is generated, can be output from the totm1 pin. the value of the ttnccr0 and ttnccr1 registers can be rewritten even while the timer is operating. figure 8-7. configuration of interval timer 16-bit counter output controller ccr0 buffer register ttnce bit ttnccr0 register count clock selection clear match signal totm0 pin inttteqcn0 signal remark v850e/if3: m = 1, n = 0, 1 v850e/ig3: m = 0, 1, n = 0, 1 figure 8-8. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark v850e/if3: m = 1, n = 0, 1 v850e/ig3: m = 0, 1, n = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 438 when the ttnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts counting. at this time, the output of the totm0 pin is inverted. additionally, the set value of the ttnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the totm0 pin is in verted, and a compare match interrupt request signal (inttteqcn0) is generated. the interval can be calculated by the following expression. interval = (set value of ttnccr0 register + 1) count clock cycle remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 figure 8-9. register setting for in terval timer mode operation (1/2) (a) tmtn control register 0 (ttnctl0) 0/1 0 0 0 0 ttnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 ttncks2 ttncks1 ttncks0 ttnce (b) tmtn control register 1 (ttnctl1) 00000 ttnctl1 0, 0, 0, 0: interval timer mode 000 ttnmd2 ttnmd3 ttnmd1 ttnmd0 ttmeee ttmest (c) tmtm i/o control register 0 (ttmioc0) 0 0 0 0 0/1 ttmioc0 0: disable totm0 pin output 1: enable totm0 pin output setting of totm0 pin output level before count operation 0: low level 1: high level 0: disable totm1 pin output 1: enable totm1 pin output setting of totm1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 ttmoe1 ttmol0 ttmoe0 ttmol1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 439 figure 8-9. register setting for in terval timer mode operation (2/2) (d) tmtn counter read buffer register (ttncnt) by reading the ttncnt register, the count va lue of the 16-bit counter can be read. (e) tmtn capture/compare register 0 (ttnccr0) if the ttnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmtn capture/compare register 1 (ttnccr1) the ttnccr1 register is not used in the interval timer mode. however, the set value of the ttnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, the totm1 pi n output is inverted and a compare match interrupt request signal (inttte qcn1) is generated. by setting this register to the same value as the value set in the ttnccr0 register, a pwm waveform with a duty factor of 50% can be output from the totm1 pin. when the ttnccr1 register is not used, it is recommended to se t its value to ffffh. also mask the register by the interrupt mask flag (ttnccic1.ttnccmk1). remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 1 (ttmioc1), tmtm i/o control register 2 (ttmioc2), tmtm i/o c ontrol register 3 (ttmioc3), tmtn option register 0 (ttnopt0), tmtm option register 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter write register (ttmtcw) are not used in the interval timer mode. 2. v850e/if3: m = 1, n = 0, 1 v850e/ig3: m = 0, 1, n = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 440 (1) interval timer mode operation flow figure 8-10. software processing flow in interval timer mode ttnce bit = 1 ttnce bit = 0 register initial setting ttnctl0 register (ttncks0 to ttncks2 bits) ttnctl1 register, ttmioc0 register, ttnccr0 register initial setting of these registers is performed before setting the ttnce bit to 1. the ttncks0 to ttncks2 bits can be set at the same time as when counting starts (ttnce bit = 1). the counter is initialized and counting is stopped by clearing the ttnce bit to 0. the output level of the totm0 pin is as specified by the ttmioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 441 (2) interval timer mode operation timing (a) operation if ttnccr0 re gister is set to 0000h if the ttnccr0 register is set to 0000h, the inttteqcn0 signal is generated at each count clock, and the output of the totm0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 (b) operation if ttnccr0 re gister is set to ffffh if the ttnccr0 register is set to ffffh, the 16-bit count er counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttteqcn0 signal is generated and the output of the totm0 pin is inverted. at this time, an overflow interrupt request signal (intttiovn) is not generated, nor is the overflow flag (ttnopt0.ttnovf bit) set to 1. ffffh 16-bit counter 0000h ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 442 (c) notes on rewriting ttnccr0 register if the value of the ttnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. ffffh 16-bit counter 0000h ttnce bit ttnccr0 register ttmol0 bit totm0 pin output inttteqcn0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1 if the value of the ttnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the ttnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttteqcn0 signal is generated and the output of the totm0 pin is inverted. therefore, the inttteqcn0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but ma y be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 443 (d) operation of ttnccr1 register figure 8-11. configuration of ttnccr1 register ccr0 buffer register ttnccr0 register ttnccr1 register ccr1 buffer register totm0 pin inttteqcn0 signal totm1 pin inttteqcn1 signal 16-bit counter output controller ttnce bit count clock selection clear match signal output controller match signal remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 444 when the ttnccr1 register is set to the same value as the ttnccr0 register, the inttteqcn0 signal is generated at the same timing as the inttteqcn1 signal and the totm1 pin output is inverted. in other words, a pwm waveform with a duty factor of 50% can be output from the totm1 pin. the following shows the operation when the ttnccr1 regi ster is set to other than the value set in the ttnccr0 register. if the set value of the ttnccr1 register is less than the set value of the ttnccr0 register, the inttteqcn1 signal is generated once per cycle. at t he same time, the output of the totm1 pin is inverted. the totm1 pin outputs a pwm waveform with a duty fa ctor of 50% after outputting a short-width pulse. figure 8-12. timing chart when d 01 d 11 ffffh 16-bit counter 0000h ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal ttnccr1 register totm1 pin output inttteqcn1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 445 if the set value of the ttnccr1 register is greater than the set value of the ttnccr0 register, the count value of the 16-bit counter does not match the va lue of the ttnccr1 register. consequently, the inttteqcn1 signal is not generated, nor is the output of the totm1 pin changed. when the ttnccr1 register is not used, it is recommended to set it s value to ffffh. figure 8-13. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h ttnce bit ttnccr0 register totm0 pin output inttteqcn0 signal ttnccr1 register totm1 pin output inttteqcn1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 446 8.6.2 external event count mode (ttmmd3 to ttmmd0 bits = 0001) this mode is valid only in tmt0 (v850e/ig3 only) and tmt1. in the external event count mode, the valid edge of the external event count input (evttm) is counted when the ttmctl0.ttmce bit is set to 1, and an interrupt request signal (inttteqcm0) is generated each time the number of edges set by the ttmccr0 register have been count ed. the totm0 and totm1 pins cannot be used. the ttmccr1 register is not used in the external event count mode. figure 8-14. configuration in external event count mode 16-bit counter ccr0 buffer register ttmce bit ttmccr0 register edge detector note clear match signal inttteqcm0 signal evttm pin (external event count input) note set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 447 figure 8-15. basic timing in external event count mode ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal d 0 d 0 d 0 d 0 16-bit counter ttmccr0 register inttteqcm0 signal external event count input (evttm pin input) d 0 external event count (d 0 + 1) external event count (d 0 + 1) external event count (d 0 + 1) d 0 ? 1d 0 0000 0001 remarks 1. this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 448 when the ttmce bit is set to 1, the value of the 16-bit count er is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the ttmccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttteqcm0) is generated. the inttteqcm0 signal is generated each time the valid edge of the ex ternal event count input has been detected ?value set to ttmccr0 register + 1? times. figure 8-16. register setting for operati on in external event count mode (1/2) (a) tmtm control register 0 (ttmctl0) 0/1 0 0 0 0 ttmctl0 0: stop counting 1: enable counting 000 ttmcks2 ttmcks1 ttmcks0 ttmce (b) tmtm control register 1 (ttmctl1) 00000 ttmctl1 0, 0, 0, 1: external event count mode 001 ttmmd2 ttmmd3 ttmmd1 ttmmd0 ttmeee ttmest (c) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external event count input (evttm pin) 0/1 0 0 ttmees0 ttmets1 ttmets0 ttmees1 (d) tmtm counter read buffer register (ttmcnt) the count value of the 16-bit counter can be read by reading the ttmcnt register. (e) tmtm capture/compare register 0 (ttmccr0) if the ttmccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 + 1) and the compare match interrupt req uest signal (inttteqcm0) is generated.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 449 figure 8-16. register setting for operati on in external event count mode (2/2) (f) tmtm capture/compare register 1 (ttmccr1) the ttmccr1 register is not used in the external event count mode. however, the set value of the ttmccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttteqcm1) is generated. when the ttmccr1 register is not used, it is recomme nded to set its value to ffffh. also mask the register by the interrupt mask flag (ttmccic1.ttmccmk1). caution be sure to set the ttmioc0 register to 00h. remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 1 (ttmioc1), tmtm i/o control register 3 (ttmioc3), tmtm option r egister 0 (ttmopt0), tmtm option register 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter write register (ttmtcw) are not used in the external event count mode. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 450 (1) external event count mode operation flow figure 8-17. software processing flow in external event count mode ttmce bit = 1 ttmce bit = 0 register initial setting ttmctl1 register, ttmioc2 register, ttmccr0, ttmccr1 registers initial setting of these registers is performed before setting the ttmce bit to 1. the counter is initialized and counting is stopped by clearing the ttmce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 451 (2) operation timing in external event count mode caution the use of timer output (totm0, totm1) is prohibited in the external event count mode. (a) operation if ttmccr0 re gister is set to 0000h when the ttmccr0 register is set to 0000h, the 16-bit counter is repeatedly cleared to 0000h and generates the inttteqcm0 si gnal each time it has detec ted the valid edge of t he external event count signal and its value has matched t hat of the ccr0 buffer register. the value of the 16-bit counter is always 0000h. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal 0000h inttteqcm0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 (b) operation if ttmccr0 register is set to ffffh if the ttmccr0 register is set to ffffh, the 16-bit counter counts up to ffffh each time the valid edge of the external event count signa l has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-u p timing, and the inttteqcm0 signal is generated. at this time, the ttmopt0.ttmovf bit is not set. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal ffffh external event count: 10000h external event count: 10000h external event count: 10000h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 452 (c) operation with ttmccr0 set to ff ffh and ttmccr1 register to 0000h when the ttmccr0 register is set to ffffh, the 16- bit counter counts up to ffffh each time it has detected the valid edge of the exte rnal event count signal. the count er is then cleared to 0000h in synchronization with the next count- up timing and the inttteqcm0 signal is generated. at this time, the ttmopt0.ttmovf bit is not set. if the ttmccr1 register is set to 0000h, the inttteqcm1 signal is generated wh en the 16-bit counter is cleared to 0000h. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal ttmccr1 register inttteqcm1 signal ffffh 0000h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 453 (d) notes on rewriting the ttmccr0 register if the value of the ttmccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the overflow may occur, stop counting once and then change the set value. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1): (d 1 + 1) external event count (ng): (10000h + d 2 + 1) external event count (2): (d 2 + 1) remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 if the value of the ttmccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the ttmccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttteqcm0 signal is generated. therefore, the inttteqcm0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be ge nerated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 454 (e) operation of ttmccr1 register figure 8-18. configuration of ttmccr1 register ccr0 buffer register ttmce bit ttmccr0 register 16-bit counter ttmccr1 register ccr1 buffer register clear match signal match signal inttteqcm0 signal inttteqcm1 signal edge detector note evttm pin (external event count input) note set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 455 if the set value of the ttmccr1 register is smaller than the set value of the ttmccr0 register, the inttteqcm1 signal is generated once per cycle. figure 8-19. timing chart when d 01 d 11 ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal ttmccr1 register inttteqcm1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 456 if the set value of the ttmccr1 register is greate r than the set value of the ttmccr0 register, the inttteqcm1 signal is not g enerated because the count value of the 16-b it counter and the value of the ttmccr1 register do not match. when the ttmccr1 register is not used, it is recommended to set its value to ffffh. figure 8-20. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal ttmccr1 register inttteqcm1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 457 8.6.3 external trigger pulse output m ode (ttmmd3 to ttmmd0 bits = 0010) this mode is valid only in tmt0 (v850e/ig3 only) and tmt1. in the external trigger pulse output mode, 16-bit timer/event counter t waits for a trigger when the ttmctl0.ttmce bit is set to 1. when the valid edge of an external trigger input (evttm) is detected, 16-bit timer/event counter t starts counting, and outputs a pwm waveform from the totm1 pin. a pwm waveform with a duty factor of 50% that has the set va lue of the ttmccr0 register + 1 as hal f its cycle can also be output from the totm0 pin. pulses can also be output by generating a software trigger instead of using the external trigger. figure 8-21. configuration in external trigger pulse output mode ccr0 buffer register ttmce bit ttmccr0 register 16-bit counter ttmccr1 register ccr1 buffer register clear match signal match signal inttteqcm0 signal output controller (rs-ff) output controller totm1 pin inttteqcm1 signal totm0 pin count clock selection internal count clock count start control edge detector note 2 software trigger generation evttm pin note 1 (external trigger input/ external event count input) edge detector note 3 transfer transfer s r notes 1. because the external trigger input pin (evttm) and external event count input pin (evttm) share the same alternate-function pin, the two fu nctions cannot be used at the same time. 2. edge detector for external trigger input. set by the ttmioc2.ttmets1 and ttmioc2.ttmets0 bits. 3. edge detector for external event count input. set by the ttmioc2.ttmees1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 458 figure 8-22. basic timing in exte rnal trigger pulse output mode d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal totm0 pin output ttmccr1 register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter t waits for a trigger when the ttmce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the sa me time, and outputs a pwm waveform from the totm1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of the totm0 pin is inverted. th e totm1 pin outputs a high-lev el regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of ttmccr1 register) count clock cycle cycle = (set value of ttmccr0 register + 1) count clock cycle duty factor = (set value of ttmccr1 register)/(set value of ttmccr0 register + 1) the compare match request signal (inttte qcm0) is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register , and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttteqcm1) is generated w hen the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the ttmccra register is transferred to t he ccra buffer register when t he count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input (evttm), or setting the software trigger (ttmctl1.ttmest bit) to 1 is used as the trigger. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 459 figure 8-23. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmtm control register 0 (ttmctl0) 0/1 0 0 0 0 ttmctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 ttmcks2 ttmcks1 ttmcks0 ttmce note the setting is invalid when the ttmctl1.ttmeee bit = 1. (b) tmtm control register 1 (ttmctl1) 0 0/1 0/1 0 0 ttmctl1 0: operate on count clock selected by ttmcks0 to ttmcks2 bits 1: count with external event count input signal generate software trigger when 1 is written 010 ttmmd2 ttmmd1 ttmmd0 ttmeee ttmest 0, 0, 1, 0: external trigger pulse output mode ttmmd3 (c) tmtm i/o control register 0 (ttmioc0) 0 0 0 0 0/1 ttmioc0 0: disable totm0 pin output 1: enable totm0 pin output setting of totm0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable totm1 pin output 1: enable totm1 pin output setting of totm1 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 ttmoe1 ttmol0 ttmoe0 ttmol1 totm1 pin output 16-bit counter ? when ttmol1 bit = 0 totm1 pin output 16-bit counter ? when ttmol1 bit = 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 460 figure 8-23. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external trigger input (evttm pin) note select valid edge of external event count input (evttm pin) note 0/1 0/1 0/1 ttmees0 ttmets1 ttmets0 ttmees1 note set the valid edge selection of the unused alternate external input signals to ?no edge detection?. (e) tmtm counter read bu ffer register (ttmcnt) the value of the 16-bit counter can be read by reading the ttmcnt register. (f) tmtm capture/compare regist ers 0 and 1 (ttmccr0 and ttmccr1) if d 0 is set to the ttmccr0 register and d 1 to the ttmccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 1 (ttmioc1), tmtm i/o control register 3 (ttmioc3), tmtm option r egister 0 (ttmopt0), tmtm option register 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter write register (ttmtcw) are not used in t he external trigger pulse output mode. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 461 (1) operation flow in extern al trigger pulse output mode figure 8-24. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register inttteqcm0 signal totm0 pin output ttmccr1 register ccr1 buffer register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 462 figure 8-24. software processing flow in ex ternal trigger pulse output mode (2/2) ttmce bit = 1 setting of ttmccr0 register register initial setting ttmctl0 register (ttmcks0 to ttmcks2 bits) ttmctl1 register, ttmioc0 register, ttmioc2 register, ttmccr0 register, ttmccr1 register initial setting of these registers is performed before setting the ttmce bit to 1. the ttmcks0 to ttmcks2 bits can be set at the same time as when counting is enabled (ttmce bit = 1). trigger wait status. writing same value (same as preset value of the ttmccr1 register) to the ttmccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the ttmccra register is transferred to the ccra buffer register. start setting of ttmccr1 register <1> count operation start flow <2> ttmccr0 and ttmccr1 register setting change flow setting of ttmccr0 register when the counter is cleared after setting, the value of the ttmccra register is transferred to the ccra buffer register. setting of ttmccr1 register <4> ttmccr0, ttmccr1 register setting change flow only writing of the ttmccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the ttmccra register is transferred to the ccra buffer register. setting of ttmccr1 register <3> ttmccr0, ttmccr1 register setting change flow ttmce bit = 0 counting is stopped. stop <5> count operation stop flow remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 463 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the ttmccr1 register last. rewrite the ttmccra register a fter writing the ttmccr1 register after the inttteqcm0 signal is detected. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register inttteqcm0 signal totm0 pin output ttmccr1 register ccr1 buffer register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 464 in order to transfer data from the ttmccra register to the ccra buffer register, the ttmccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the ttmccr0 register and then set the active level width to the ttmccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the ttmccr0 register, and then write the same value (same as preset value of the ttmccr1 register) to the ttmccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the ttmccr1 register has to be set. after data is written to the ttmccr1 register, the valu e written to the ttmccra register is transferred to the ccra buffer register in synchronization with clea ring of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the ttmccr0 or ttmccr1 register again afte r writing the ttmccr1 register once, do so after the inttteqcm0 signal is generated. otherwise, th e value of the ccra buff er register may become undefined because the timing of transferring data from the ttmccra register to the ccra buffer register conflicts with writing the ttmccra register. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 465 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the ttmccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttteqcm0 and inttteqcm1 si gnals are generated at the next timing after a match between the count value of the 16-bi t counter and the value of the ccr0 buffer register. count clock 16-bit counter ttmce bit ttmccr0 register ttmccr1 register inttteqcm0 signal inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 note note note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 466 to output a 100% waveform, set a value of (set value of ttmccr0 register + 1) to the ttmccr1 register. if the set value of the ttmccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter ttmce bit ttmccr0 register ttmccr1 register inttteqcm0 signal inttteqcm1 signal totm1 pin output d 0 ? 1d 0 ? 1 external trigger input (evttm pin input) note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 467 (c) conflict between trigger detection and match with ccr1 buffer register if the trigger is detected immediately after the in ttteqcm1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he totm1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr1 buffer register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 if the trigger is detected immediately before t he inttteqcm1 signal is generated, the inttteqcm1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the totm1 pin remains active. consequent ly, the active period of the pwm waveform is extended. 16-bit counter ccr1 buffer register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 468 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the in ttteqcm0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the totm1 pin is extended by time from generation of the inttte qcm0 signal to trigger detection. 16-bit counter ccr0 buffer register inttteqcm0 signal totm1 pin output external trigger input (evttm pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 if the trigger is detected immediately before t he inttteqcm0 signal is generated, the inttteqcm0 signal is not generated. the 16-bit counter is cleared to 0000h, the totm1 pin is asserted, and the counter continues counting. consequently, the inac tive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttteqcm0 signal totm1 pin output external trigger input (evttm pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 469 (e) generation timing of compare match interrupt request signal (inttteqcm1) the timing of generation of the in ttteqcm1 signal in the external trigger pulse output mode differs from the timing of inttteqcm1 signals in other mode; the inttteqcm1 signal is generated when the count value of the 16-bit counter matches the value of the ttmccr1 register. count clock 16-bit counter ttmccr1 register totm1 pin output inttteqcm1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 usually, the inttteqcm1 signal is ge nerated in synchronization with th e next count-up, after the count value of the 16-bit counter matches the value of the ttmccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the totm1 pin.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 470 8.6.4 one-shot pulse output mode (ttmmd3 to ttmmd0 bits = 0011) this mode is valid only in tmt0 (v850e/ig3 only) and tmt1. in the one-shot pulse output mode, 16-bit timer/event c ounter t waits for a trigger when the ttmctl0.ttmce bit is set to 1. when the valid edge of an external trigger in put (evttm) is detected, 16-bit timer/event counter t starts counting, and outputs a one-shot pulse fr om the totm1 pin. the totm0 pin output s the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). instead of the external trigger input (evttm), a softw are trigger can also be generated to output the pulse. figure 8-25. configuration in one-shot pulse output mode ccr0 buffer register ttmce bit ttmccr0 register 16-bit counter ttmccr1 register ccr1 buffer register clear match signal match signal inttteqcm0 signal output controller (rs-ff) output controller (rs-ff) totm1 pin inttteqcm1 signal totm0 pin count clock selection internal count clock count start control edge detector note 2 software trigger generation edge detector note 3 transfer transfer s r s r evttm pin note 1 (external trigger input/ external event count input) notes 1. because the external trigger input pin (evttm) and external event count input pin (evttm) share the same alternate-function pin, the two fu nctions cannot be used at the same time. 2. edge detector for external trigger input. set by the ttmioc2.ttmets1 and ttmioc2.ttmets0 bits. 3. edge detector for external event count input. set by the ttmioc2.ttmees1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 471 figure 8-26. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal totm0 pin output ttmccr1 register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) when the ttmce bit is set to 1, 16-bit timer/event counter t waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a one-shot pul se from the totm1 pin. after the one-shot pulse is output, the 16- bit counter is cleared to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit counter star ts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of ttmccr1 register) count clock cycle active level width = (set value of ttmccr0 register ? set value of ttmccr1 register + 1) count clock cycle the compare match interrupt request si gnal (inttteqcm0) is generated when th e 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal (inttteqcm1) is generated when the count value of the 16-bit counter matc hes the value of the ccr1 buffer register. the valid edge of an external trigger input (evttm pin) or setting the software trigger (ttmctl1.ttmest bit) to 1 is used as the trigger. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 472 figure 8-27. setting of registers in one-shot pulse output mode (1/2) (a) tmtm control register 0 (ttmctl0) 0/1 0 0 0 0 ttmctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 ttmcks2 ttmcks1 ttmcks0 ttmce note the setting is invalid when the ttmctl1.ttmeee bit = 1. (b) tmtm control register 1 (ttmctl1) 0 0/1 0/1 0 0 ttmctl1 0: operate on count clock selected by ttmcks0 to ttmcks2 bits 1: count external event input signal generate software trigger when 1 is written 011 ttmmd2 ttmmd1 ttmmd0 ttmeee ttmest 0, 0, 1, 1: one-shot pulse output mode ttmmd3 (c) tmtm i/o control register 0 (ttmioc0) 0 0 0 0 0/1 ttmioc0 0: disable totm0 pin output 1: enable totm0 pin output setting of totm0 pin output level while waiting for external trigger 0: low level 1: high level 0: disable totm1 pin output 1: enable totm1 pin output setting of totm1 pinoutput level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 ttmoe1 ttmol0 ttmoe0 ttmol1 totm1 pin output 16-bit counter ? when ttmol1 bit = 0 totm1 pin output 16-bit counter ? when ttmol1 bit = 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 473 figure 8-27. setting of registers in one-shot pulse output mode (2/2) (d) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external trigger input (evttm pin) note select valid edge of external event count input (evttm pin) note 0/1 0/1 0/1 ttmees0 ttmets1 ttmets0 ttmees1 note set the valid edge selection of the unused alternate external input signals to ?no edge detection?. (e) tmtm counter read bu ffer register (ttmcnt) the value of the 16-bit counter can be read by reading the ttmcnt register. (f) tmtm capture/compare regist ers 0 and 1 (ttmccr0 and ttmccr1) if d 0 is set to the ttmccr0 register and d 1 to the ttmccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = d 1 count clock cycle caution one-shot pulses are not output even in the one-shot pulse output mode, if the value set in the ttmccr1 register is greater than that set in the ttmccr0 register. remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 1 (ttmioc1), tmtm i/o control register 3 (ttmioc3), tmtm option r egister 0 (ttmopt0), tmtm option register 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter write register (ttmtcw) are not used in the one-shot pulse output mode. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 474 (1) operation flow in one-shot pulse output mode figure 8-28. software processing flow in one-shot pulse output mode <1> <2> <3> start stop d 10 d 11 d 00 d 01 d 00 d 10 d 11 d 01 setting of ttmccr0, ttmccr1 registers <2> ttmccr0, ttmccr1 register setting change flow ttmce bit = 1 ttmce bit = 0 register initial setting ttmctl0 register (ttmcks0 to ttmcks2 bits) ttmctl1 register, ttmioc0 register, ttmioc2 register, ttmccr0 register, ttmccr1 register initial setting of these registers is performed before setting the ttmce bit to 1. the ttmcks0 to ttmcks2 bits can be set at the same time as when counting starts (ttmce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <3> count operation stop flow ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal totm0 pin output ttmccr1 register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) as rewriting the ttmccra register immediately forwards to the ccra buffer register, rewriting immediately after the generation of the inttteqcm0 signal is recommended. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 475 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng ttmccra register if the value of the ttmccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 ffffh 16-bit counter 0000h ttmce bit ttmccr0 register inttteqcm0 signal totm0 pin output ttmccr1 register inttteqcm1 signal totm1 pin output external trigger input (evttm pin input) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the ttmccr0 register is rewritten from d 00 to d 01 and the ttmccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the ttmccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the ttmccr0 register is re written when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the coun t value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttteqcm1 signal and asserts the totm1 pin. when the count value matches d 01 , the counter ge nerates the inttteqcm0 signal, deasserts the totm1 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 476 (b) generation timing of compare match interrupt request signal (inttteqcm1) the generation timing of the inttteqc m1 signal in the one-shot pulse output mode is different from inttteqcm1 signals in other mode; the inttteqcm1 signal is generated when the count value of the 16-bit counter matches the value of the ttmccr1 register. count clock 16-bit counter ttmccr1 register totm1 pin output inttteqcm1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 usually, the inttteqcm1 signal is gene rated when the 16-bit counter count s up next time after its count value matches the value of the ttmccr1 register. in the one-shot pulse output mode, however, it is gener ated one clock earlier. this is because the timing is changed to match the change timing of the totm1 pin.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 477 8.6.5 pwm output mode (ttm md3 to ttmmd0 bits = 0100) this mode is valid only in tmt0 (v850e/ig3 only) and tmt1. in the pwm output mode, a pwm waveform is output fr om the totm1 pin when the ttmctl0.ttmce bit is set to 1. in addition, a pwm waveform with a duty factor of 50% wit h the set value of the ttmccr0 register + 1 as half its cycle is output from the totm0 pin. figure 8-29. configuration in pwm output mode ccr0 buffer register ttmce bit ttmccr0 register 16-bit counter ttmccr1 register ccr1 buffer register clear match signal match signal inttteqcm0 signal output controller (rs-ff) output controller totm1 pin inttteqcm1 signal totm0 pin transfer transfer s r count clock selection internal count clock evttm pin (external event count input) edge detector note note set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 478 figure 8-30. basic timing in pwm output mode ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register inttteqcm0 signal totm0 pin output ttmccr1 register ccr1 buffer register inttteqcm1 signal totm1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 - d 10 + 1) when the ttmce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the totm1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of ttmccr1 register) count clock cycle cycle = (set value of ttmccr0 register + 1) count clock cycle duty factor = (set value of ttmccr1 register)/(set value of ttmccr0 register + 1) the pwm waveform can be changed by rewriting the ttmccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request si gnal (inttteqcm0) is genera ted when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request sign al (inttteqcm1) is genera ted when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the ttmccra register is transferred to t he ccra buffer register when t he count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. remark v850e/if3: m = 1, a = 0, 1, v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 479 figure 8-31. setting of registers in pwm output mode (1/2) (a) tmtm control register 0 (ttmctl0) 0/1 0 0 0 0 ttmctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 ttmcks2 ttmcks1 ttmcks0 ttmce note the setting is invalid when the ttmctl1.ttmeee bit = 1. (b) tmtm control register 1 (ttmctl1) 0 0 0/1 0 0 ttmctl1 100 ttmmd2 ttmmd1 ttmmd0 ttmeee ttmest 0, 1, 0, 0: pwm output mode 0: operate on count clock selected by ttmcks0 to ttmcks2 bits 1: count with external event count input signal ttmmd3 (c) tmtm i/o control register 0 (ttmioc0) 0 0 0 0 0/1 ttmioc0 0: disable totm0 pin output 1: enable totm0 pin output setting of totm0 pin output level before count operation 0: low level 1: high level 0: disable totm1 pin output 1: enable totm1 pin output setting of totm1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 ttmoe1 ttmol0 ttmoe0 ttmol1 totm1 pin output 16-bit counter ? when ttmol1 bit = 0 totm1 pin output 16-bit counter ? when ttmol1 bit = 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 480 figure 8-31. register setting in pwm output mode (2/2) (d) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external event count input (evttm pin). 0/1 0 0 ttmees0 ttmets1 ttmets0 ttmees1 (e) tmtm counter read bu ffer register (ttmcnt) the value of the 16-bit counter can be read by reading the ttmcnt register. (f) tmtm capture/compare regist ers 0 and 1 (ttmccr0 and ttmccr1) if d 0 is set to the ttmccr0 register and d 1 to the ttmccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 1 (ttmioc1), tmtm i/o control register 3 (ttmctl3), tmtm option r egister 0 (ttmopt0), tmtm option register 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter write register (ttmtcw) are not used in the pwm output mode. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 481 (1) operation flow in pwm output mode figure 8-32. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register inttteqcm0 signal totm0 pin output ttmccr1 register ccr1 buffer register inttteqcm1 signal totm1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 482 figure 8-32. software processing flow in pwm output mode (2/2) ttmce bit = 1 setting of ttmccr0 register register initial setting ttmctl0 register (ttmcks0 to ttmcks2 bits) ttmctl1 register, ttmioc0 register, ttmioc2 register, ttmccr0 register, ttmccr1 register initial setting of these registers is performed before setting the ttmce bit to 1. the ttmcks0 to ttmcks2 bits can be set at the same time as when counting is enabled (ttmce bit = 1). writing same value (same as preset value of the ttmccr1 register) to the ttmccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the ttmccra register is transferred to the ccra buffer register. start setting of ttmccr1 register <1> count operation start flow <2> ttmccr0, ttmccr1 register setting change flow (cycle only) setting of ttmccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of ttmccr1 register <4> ttmccr0, ttmccr1 register setting change flow (cycle and duty) only writing of the ttmccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of ttmccr1 register <3> ttmccr0, ttmccr1 register setting change flow (duty only) ttmce bit = 0 counting is stopped. stop <5> count operation stop flow remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 483 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the ttmccr1 register last. rewrite the ttmccra register a fter writing the ttmccr1 register after the inttteqcm0 signal is detected. ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register ttmccr1 register ccr1 buffer register totm1 pin output inttteqcm0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the ttmccra register to the ccra buffer register, the ttmccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the ttmccr0 register and then set the active level to the ttmccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the ttmccr0 register, and then write the same value (same as preset value of the ttmccr1 register) to the ttmccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the ttmccr1 register has to be set. after data is written to the ttmccr1 register, the valu e written to the ttmccra register is transferred to the ccra buffer register in synchronization with clea ring of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the ttmccr0 or ttmccr1 register again afte r writing the ttmccr1 register once, do so after the inttteqcm0 signal is generated. otherwise, th e value of the ccra buff er register may become undefined because the timing of transferring data from the ttmccra register to the ccra buffer register conflicts with writing the ttmccra register. remark v850e/if3: m = 1, a = 0, 1, v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 484 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the ttmccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttteqcm0 and inttteqcm1 si gnals are generated at the next timing after a match between the count value of the 16-bi t counter and the value of the ccr0 buffer register. count clock 16-bit counter ttmce bit ttmccr0 register ttmccr1 register inttteqcm0 signal inttteqcm1 signal totm1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 l note note note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 to output a 100% waveform, set a value of (set value of ttmccr0 register + 1) to the ttmccr1 register. if the set value of the ttmccr0 register is ffffh, 100% output cannot be produced. d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 0000 ffff 0000 d 00 0000 0001 count clock 16-bit counter ttmce bit ttmccr0 register ttmccr1 register inttteqcm0 signal inttteqcm1 signal totm1 pin output d 00 ? 1d 00 ? 1 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 485 (c) generation timing of compare match interrupt request signal (inttteqcm1) the timing of generation of the in ttteqcm1 signal in the pwm output mode differs from the timing of inttteqcm1 signals in other modes; the inttteqcm1 si gnal is generated when the count value of the 16-bit counter matches the value of the ttmccr1 register. count clock 16-bit counter ttmccr1 register totm1 pin output inttteqcm1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 usually, the inttteqcm1 signal is gene rated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the ttmccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the totm1 pin.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 486 8.6.6 free-running timer mode ( ttnmd3 to ttnmd0 bits = 0101) the compare function is valid for a ll of tmt0 and tmt1. the capture fu nction is valid only for tmt0 (v850e/ig3 only) and tmt1. in the free-running timer mode, 16-bit timer/event counte r t starts counting when the ttnctl0.ttnce bit is set to 1. at this time, the ttmccr0 and ttmccr1 registers c an be used as compare registers or capture registers, depending on the setting of the ttmopt0.ttmccs0 and ttmopt0.ttmccs1 bits. figure 8-33. configuration in free-running timer mode ttmccr0 register (capture) ttnce bit ttmccr1 register (compare) 16-bit counter ttnccr1 register (compare) ttnccr0 register (capture) output controller ttmccs0, ttmccs1 bits (capture/compare selection) totm0 pin note 1 output controller totm1 pin note 1 edge detector note 2 count clock selection edge detector note 3 edge detector note 4 evttm pin (external event count input) titm0 pin note 1 (capture trigger input) titm1 pin note 1 (capture trigger input) internal count clock 0 1 0 1 intttiovn signal inttteqcn1 signal inttteqcn0 signal notes 1. because the capture trigger input pins (titm0, titm1) and timer output pins (totm0, totm1) share the same alternate-function pins, the two fu nctions cannot be used at the same time. 2. set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. 3. set by the ttmioc1.ttmis1 and ttmioc1.ttmis0 bits. 4. set by the ttmioc1.ttmis3 and ttmioc1.ttmis2 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 487 ? compare operation when the ttnce bit is set to 1, 16-bit timer/event count er t starts counting, and the output signal of the totma pin is inverted. when the count value of the 16-bit count er later matches the set value of the ttnccra register, a compare match interrupt request sign al (inttteqcna) is generated, and the output signal of the totna pin is inverted. the 16-bit counter continues counting in synchronization with th e count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (intttiovn) at the next clock, is clear ed to 0000h, and continues counting. at this time, the overflow flag (ttnopt0.ttnovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. the ttnccra register can be rewritten whil e the counter is operating. if it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. figure 8-34. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h ttnce bit ttnccr0 register inttteqcn0 signal totm0 pin output ttnccr1 register inttteqcn1 signal totm1 pin output intttiovn signal ttnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark v850e/if3: n = 0, 1, m = 1, a = 0, 1 v850e/ig3: n = 0, 1, m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 488 ? capture operation when the ttmce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the titma pin is detected, the count value of the 16-bit counter is stored in the ttmccra register, and a capture interrupt request signal (inttteqcma) is generated. the 16-bit counter continues counting in synchronization with th e count clock. when it counts up to ffffh, it generates an overflow interrupt reques t signal (intttiovm) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (ttmopt0.ttmovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 8-35. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h ttmce bit titm0 pin input ttmccr0 register inttteqcm0 signal titm1 pin input ttmccr1 register inttteqcm1 signal intttiovm signal ttmovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 489 figure 8-36. register setting in free-running timer mode (1/2) (a) tmtn control register 0 (ttnctl0) 0/1 0 0 0 0 ttnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 ttncks2 ttncks1 ttncks0 ttnce note the setting is invalid when the ttmctl1.ttmeee bit = 1 (b) tmtn control register 1 (ttnctl1) 0 0 0/1 0 0 ttnctl1 101 ttnmd2 ttnmd1 ttnmd0 ttmeee ttmest ttnmd3 0, 1, 0, 1: free-running timer mode 0: operate with count clock selected by ttmcks0 to ttmcks2 bits 1: count on external event count input signal (c) tmtm i/o control register 0 (ttmioc0) 0 0 0 0 0/1 ttmioc0 0: disable totm0 pin output 1: enable totm0 pin output setting of totm0 pin output level before count operation 0: low level 1: high level 0: disable totm1 pin output 1: enable totm1 pin output setting of totm1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 ttmoe1 ttmol0 ttmoe0 ttmol1 (d) tmtm i/o control register 1 (ttmioc1) 0 0 0 0 0/1 ttmioc1 select valid edge of titm0 pin input select valid edge of titm1 pin input 0/1 0/1 0/1 ttmis2 ttmis1 ttmis0 ttmis3
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 490 figure 8-36. register setting in free-running timer mode (2/2) (e) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external event count input (evttm pin) 0/1 0 0 ttmees0 ttmets1 ttmets0 ttmees1 (f) tmtn option register 0 (ttnopt0) 0 0 0/1 0/1 0 ttnopt0 overflow flag specifies if ttmccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if ttmccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 ttmccs0 ttnovf ttmccs1 (g) tmtn counter read buffer register (ttncnt) the value of the 16-bit counter can be read by reading the ttncnt register. (h) tmtn capture/compare regist ers 0 and 1 (ttnccr0 and ttnccr1) these registers function as capt ure registers or compare regist ers depending on the setting of the ttmopt0.ttmccsa bit. when the registers function as capture registers, th ey store the count value of the 16-bit counter when the valid edge input to the titma pin is detected. when the registers function as compare registers and when d a is set to the ttnccra register, the inttteqcna signal is generated when the counter reaches (d a + 1), and the output signals of the totm0 and totm1 pins are inverted. remark v850e/if3: n = 0, 1, m = 1, a = 0, 1 v850e/ig3: n = 0, 1, m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 491 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-37. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> ffffh 16-bit counter 0000h ttnce bit ttnccr0 register inttteqcn0 signal totm0 pin output ttnccr1 register inttteqcn1 signal totm1 pin output intttiovn signal ttnovf bit remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 492 figure 8-37. software processing flow in fr ee-running timer mode (c ompare function) (2/2) ttnce bit = 1 read ttnopt0 register (check overflow flag). register initial setting ttnctl0 register (ttncks0 to ttncks2 bits) ttnctl1 register, ttmioc0 register, ttmioc2 register, ttnopt0 register, ttnccr0 register, ttnccr1 register initial setting of these registers is performed before setting the ttnce bit to 1. the ttncks0 to ttncks2 bits can be set at the same time as when counting starts (ttnce bit = 1). start execute instruction to clear ttnovf bit (clr ttnovf). <1> count operation start flow <2> overflow flag clear flow ttnce bit = 0 counter is initialized and counting is stopped by clearing ttnce bit to 0. stop <3> count operation stop flow ttnovf bit = 1 no yes remark v850e/if3: n = 0, 1, m = 1 v850e/ig3: n = 0, 1, m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 493 (b) when using capture/compare register as capture register figure 8-38. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h ttmce bit titm0 pin input ttmccr0 register inttteqcm0 signal titm1 pin input ttmccr1 register inttteqcm1 signal intttiovm signal ttmovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 494 figure 8-38. software processing flow in fr ee-running timer mode (c apture function) (2/2) ttmce bit = 1 read ttmopt0 register (check overflow flag). register initial setting ttmctl0 register (ttmcks0 to ttmcks2 bits) ttmctl1 register, ttmioc1 register, ttmopt0 register initial setting of these registers is performed before setting the ttmce bit to 1. the ttmcks0 to ttmcks2 bits can be set at the same time as when counting starts (ttmce bit = 1). start execute instruction to clear ttmovf bit (clr ttmovf). <1> count operation start flow <2> overflow flag clear flow ttmce bit = 0 counter is initialized and counting is stopped by clearing ttmce bit to 0. stop <3> count operation stop flow ttmovf bit = 1 no yes remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 495 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter t is used as an in terval timer with the ttnccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time t he inttteqcna signal has been detected. ffffh 16-bit counter 0000h ttnce bit ttnccr0 register inttteqcn0 signal totm0 pin output ttnccr1 register inttteqcn1 signal totm1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding ttnccra register must be re-set in the interrupt servicing that is executed when the inttteqcna si gnal is detected. the set value for re-setting the ttnccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark v850e/if3: n = 0, 1, m = 1, a = 0, 1 v850e/ig3: n = 0, 1, m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 496 (b) pulse width measurement with capture register when pulse width measurement is performed with the ttmccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttteqcma signal has been detected and for calculating an interval. 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 ffffh 16-bit counter 0000h ttmce bit titm0 pin input ttmccr0 register inttteqcm0 signal titm1 pin input ttmccr1 register inttteqcm1 signal intttiovm signal ttmovf bit pulse interval (d 00 ) pulse interval (10000h + d 01 - d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculated by reading the value of the ttmccra register in synchronization with the inttteqcma signal, and calculat ing the difference between the read value and the previously read value. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 497 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h ttmce bit titm0 pin input ttmccr0 register titm1 pin input ttmccr1 register intttiovm signal ttmovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the ttmccr0 register (setting of t he default value of the titm0 pin input). <2> read the ttmccr1 register (setting of t he default value of the titm1 pin input). <3> read the ttmccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the ttmccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 498 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h ttmce bit intttiovm signal ttmovf bit ttmovf0 flag note titm0 pin input ttmccr0 register ttmovf1 flag note titm1 pin input ttmccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the ttmovf0 and ttmovf1 flags are set on the internal ram by software. <1> read the ttmccr0 register (setting of t he default value of the titm0 pin input). <2> read the ttmccr1 register (setting of t he default value of the titm1 pin input). <3> an overflow occurs. set the ttmovf0 and ttmovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the ttmccr0 register. read the ttmovf0 flag. if the ttmovf0 flag is 1, clear it to 0. because the ttmovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the ttmccr1 register. read the ttmovf1 flag. if the ttmovf1 flag is 1, clear it to 0 (the ttmovf0 flag is cleared in <4>, and the ttmovf1 flag remains 1). because the ttmovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 499 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h ttmce bit intttiovm signal ttmovf bit ttmovf0 flag note titm0 pin input ttmccr0 register ttmovf1 flag note titm1 pin input ttmccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the ttmovf0 and ttmovf1 flags are set on the internal ram by software. <1> read the ttmccr0 register (setting of t he default value of the titm0 pin input). <2> read the ttmccr1 register (setting of t he default value of the titm1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the ttmccr0 register. read the overflow flag. if the overflow flag is 1, set only the ttmovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the ttmccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the ttmovf1 flag. if the ttmovf1 flag is 1, clear it to 0. because the ttmovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 500 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16 -bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h ttmce bit titma pin input ttmccra register intttiovm signal ttmovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the ttmccra register (setting of t he default value of the titma pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the ttmccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pu lse width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 501 example when capture trigger interval is long ffffh 16-bit counter 0000h ttmce bit titma pin input ttmccra register intttiovm signal ttmovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the ttmccra register (setting of t he default value of the titma pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the ttmccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e ttmovf bit to 0 with the clr instruction after reading the ttmovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the ttmopt0 register after reading the ttmovf bit when it is 1.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 502 8.6.7 pulse width measurement mode (ttmmd3 to ttmmd0 bits = 0110) this mode is valid only in tmt0 (v850e/ig3 only) and tmt1. in the pulse width measurement mode, 16-bit timer/event counter t starts counting when the ttmctl0.ttmce bit is set to 1. each time the valid edge input to the titma pi n has been detected, the count va lue of the 16-bit counter is stored in the ttmccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the ttmccra register after a capture interrupt request signal (inttteqcma) occurs. as shown in figure 8-40, select either the titm0 or titm 1 pin as the capture trigger input pin and set the unused pins to ?no edge detection? by using the ttmioc1 register. figure 8-39. configuration in pulse width measurement mode ttmccr0 register (capture) ttmce bit ttmccr1 register (capture) edge detector note 1 count clock selection edge detector note 2 edge detector note 3 evttm pin (external event count input) titm0 pin (capture trigger input) titm1 pin (capture trigger input) internal count clock clear intttiovm signal inttteqcm0 signal inttteqcm1 signal 16-bit counter notes 1. set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. 2. set by the ttmioc1.ttmis1 and ttmioc1.ttmis0 bits. 3. set by the ttmioc1.ttmis3 and ttmioc1.ttmis2 bits. remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 503 figure 8-40. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h ttmce bit titma pin input ttmccra register inttteqcma signal intttiovm signal ttmovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1 when the ttmce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the titma pin is later detected, the count value of the 16- bit counter is stored in the ttmccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttteqcma) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the titma pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (intttiovm) is gen erated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (ttmopt0. ttmovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h ttmovf bit set (1) count + captured value) count clock cycle remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 504 figure 8-41. register setting in pu lse width measurement mode (1/2) (a) tmtm control register 0 (ttmctl0) 0/1 0 0 0 0 ttmctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 ttmcks2ttmcks1 ttmcks0 ttmce note setting is invalid when the ttmctl1.ttmeee bit = 1. (b) tmtm control register 1 (ttmctl1) 0 0 0/1 0 0 ttmctl1 110 ttmmd2 ttmmd1 ttmmd0 ttmeee ttmest ttmmd3 0, 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by ttmcks0 to ttmcks2 bits 1: count on external event count input signal (c) tmtm i/o control register 1 (ttmioc1) 0 0 0 0 0/1 ttmioc1 select valid edge of titm0 pin input select valid edge of titm1 pin input 0/1 0/1 0/1 ttmis2 ttmis1 ttmis0 ttmis3 (d) tmtm i/o control register 2 (ttmioc2) 0 0 0 0 0/1 ttmioc2 select valid edge of external event count input (evttm pin) 0/1 0 0 ttmees0 ttmets1 ttmets0 ttmees1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 505 figure 8-41. register setting in pu lse width measurement mode (2/2) (e) tmtm option register 0 (ttmopt0) 00000 ttmopt0 overflow flag 0 0 0/1 ttmccs0 ttmovf ttmccs1 (f) tmtm counter read buffer register (ttmcnt) the value of the 16-bit counter can be read by reading the ttmcnt register. (g) tmtm capture/compare regist ers 0 and 1 (ttmccr0 and ttmccr1) these registers store the count va lue of the 16-bit counter when the valid edge input to the titm0 and titm1 pins is detected. remarks 1. tmtm control register 2 (ttmctl2), tmtm i/o control register 0 (ttmioc0), tmtm i/o control register 3 (ttmioc3), tmtm option r egister 1 (ttmopt1), tmtm capture input select register (ttislm), and tmtm counter wr ite register (ttmtcw) are not used in the pulse width measurement mode. 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 506 (1) operation flow in pul se width measurement mode figure 8-42. software processing flow in pulse width measurement mode <1> <2> ttmce bit = 1 ttmce bit = 0 register initial setting ttmctl0 register (ttmcks0 to ttmcks2 bits), ttmctl1 register, ttmioc1 register, ttmioc2 register, ttmopt0 register initial setting of these registers is performed before setting the ttmce bit to 1. the ttmcks0 to ttmcks2 bits can be set at the same time as when counting starts (ttmce bit = 1). the counter is initialized and counting is stopped by clearing the ttmce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h ttmce bit titm0 pin input ttmccr0 register inttteqcm0 signal d 0 0000h 0000h d 1 d 2 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 507 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e ttmovf bit to 0 with the clr instruction after reading the ttmovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the ttmopt0 register after reading the ttmovf bit when it is 1.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 508 8.6.8 triangular-wave pwm output mode (ttmmd3 to ttmmd0 bits = 0111) in the triangular-wave pwm output mode, a triangular-wave pwm waveform is output from the totm1 pin when the ttmctl0.ttmce bit is set to 1. an inverted pwm waveform is output from the totm0 pin when the count value of the 16-bit counter matches the value of the ccr0 buffer register and when the 16-bit counter is set to 0000h. figure 8-43. configuration in triangular-wave pwm output mode ccr0 buffer register ttmce bit ttmccr0 register 16-bit counter ttmccr1 register ccr1 buffer register clear match signal match signal inttteqcm0 signal output controller (rs-ff) output controller totm1 pin inttteqcm1 signal totm0 pin count start control transfer transfer s r count clock selection evttm pin (external event count input) internal count clock edge detector note note set by the ttmioc2.ttme es1 and ttmioc2.ttmees0 bits. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 509 figure 8-44. basic timing in triangular-wave pwm output mode ffffh 16-bit counter 0000h ttmce bit ttmccr0 register ccr0 buffer register inttteqcm0 signal totm0 pin output ttmccr1 register ccr1 buffer register inttteqcm1 signal totm1 pin output intttiovm signal d 10 d 00 d 01 d 02 d 00 d 01 d 10 d 11 d 12 d 10 d 11 d 12 d 02 d 10 d 00 + 1 d 12 d 12 d 11 d 11 d 01 + 1 d 02 + 1 remarks 1. v850e/if3: m = 1 v850e/ig3: m = 0, 1 2. timing chart when ttmioc0 register = 05h. the 16-bit counter is cleared from ffffh and 0000h and st arts counting when the ttmce bit is set to 1. the triangular pwm waveform is output from the totm1 pin. in the triangular-wave pwm output mode, the counter coun ts up or down. when the 16-bit counter reaches 0000h while it is counting down, an overflow interrupt request signal (intttiovm) is generated. at this time, the ttmopt0.ttmovf bit is not set to 1. if the count value of the 16-bit counter matches the value of the ccr0 buffer register while the counter is counti ng up, a compare match interrupt request signal (inttteqcm0) is generated. the counting direction is changed from up to down when the value of the 16-bit counter matches that of the ccr0 buffer register, and from down to up when the counter is cleared to 0000h. the pwm waveform can be changed by rewriting the ttm ccra register during operation. to change the pwm waveform during operation, write the ttmccr1 register last. the cycle of the triangular pwm waveform is set by th e ttmccr0 register and its dut y factor is set by the ttmccr1 register. set a value to the ttmccr0 register in a range of ?0 ttmccr0 fffeh?. the rewritten value is reflected when the 16-bit counter re aches 0000h while it is counting down. even when changing only the cycle of the pwm waveform, first set a period to the ttmccr0 register, and then write the same value (value same as that set to the ttmccr1 register) to the ttmccr1 register. to transfer data from the ttmccra register to the ccra buffer register, the data must be written to the ttmccr1 register (a = 0, 1).
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 510 (1) pwm output of 0%/100% in the triangular-wave pwm output mode, 0% waveform output and 100% waveform output are available for pwm output. the 0% waveform is output by setting the ttmccr1 re gister to ?m + 1? when the ttmccr0 register = m. the 100% waveform is output by setting the ttmccr1 register to ?0000h?. the output level of totm0 and totm1 can be set in the ttmioc0 register. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 figure 8-45. 0% pwm output waveform (ttmioc0 register = 05h) i i 16-bit counter ttmccr0 register ttmccr1 register totm1 pin output totm0 pin output ccr1 buffer register i i m i i m+1 m+1 i i 0000h 0% output figure 8-46. 100% pwm output waveform (ttmioc0 register = 05h) 16-bit counter ttmccr0 register ttmccr1 register totm0 pin output ccr1 buffer register i i i m i i i i 0000h 0000h 0000h i totm1 pin output 100% output
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 511 8.6.9 encoder count function the encoder count function includes an encoder compare mode (see 8.6.10 encoder compare mode (ttmmd3 to ttmmd0 bits = 1000) ). mode ttmccr0 register ttmccr1 register encoder compare mode compare only compare only (1) count-up/-down control counting up or down by the 16-bit counter is contro lled by the phase of input encoder signals (tencm0 and tencm1) and setting of the ttmct l2.ttmuds1 and ttmctl2.ttmuds0 bits. when the encoder count function is used, the internal count clock and external event count input (evttm) cannot be used. set the ttmctl0.ttmcks2 to ttm ctl0.ttmcks0 bits to 000 and the ttmctl1.ttmeee bit to 0. (2) setting initial value of 16-bit counter the initial count value set to the ttmtcw register when the ttmctl2.ttmecc bit = 0 is transferred to the 16-bit counter immediately after the counter starts its operation (ttmctl0.ttmce bit = 0 1), and the counter starts the operation after it detects the valid edge of the encoder input signal (tencm0 or tencm1). (3) basic operation the ttmccra register generat es a compare match interrupt request signal (inttteqcma) when the count value of the 16-bit counter matches t he value of the ccra buffer register. (4) clear operation the 16-bit counter is cleared when the following condit ions are satisfied in the encoder compare mode. ? when the value of the 16-bit count er matches the value of the compar e register (the ttmctl2.ttmecm1 and ttmctl2.ttmecm0 bits are set) ? when the edge of the encoder clear input signa l (tecrm) is detected and cleared (the ttmecs1 and ttmecs0 bits are set when the ttmioc3.ttmsce bit = 0) ? when the clear level condition of the tencm0, tencm1, and tecrm pins is detected (the ttmzcl, ttmbcl, and ttmacl bits are set when the ttmsce bit = 1) remark v850e/if3: m = 1, a = 0, 1 v850e/ig3: m = 0, 1, a = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 512 (5) controlling bits of ttmctl2 register the setting of the ttmctl2 register in t he encoder compare mode is shown below. table 8-10. setting of ttmctl2 register mode ttmuds1, ttmuds0 bits (<1>) ttmecm1 bit (<2>) ttmecm0 bit (<2>) ttmlde bit (<3>) counter clear (target compare register) transfer to counter 0 ? 0 1 ? possible 0 ? 0 1 1 ttmccr0 possible note 0 invalid ttmccr1 ? encoder compare mode can be set to 00, 01, 10, or 11. 1 1 invalid ttmccr0, ttmccr1 ? note the counter can operate in a range from 000 0h to the set value of the ttmccr0 register. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 (a) outline of each bit <1> the ttmuds1 and ttmuds0 bits identify the counting direction (up or down) of the 16-bit counter by the phase input from the encoder input pin (tencm0 or tencm1). <2> the ttmecm1 and ttmecm0 bits control cleari ng of the 16-bit counter when its count value matches the value of the ccr0 or ccr1 buffer register. <3> the ttmlde bit controls a function to transfer the set value of the ttmccr0 register to the 16-bit counter when the co unter underflows. the ttmlde bit is valid only when the ttmecm1 and ttmecm0 bits are 00 or 01. it is invalid when these bits are set to any other value.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 513 (b) detailed explanation of each bit <1> ttmuds1 and ttmuds0 bits: count-up/-down selection whether the 16-bit counter is counting up or down is identified by the phase input from the tencm0 or tencm1 pin and depending on the setting of th e ttmuds1 and ttmuds0 bits. these bits are valid only in the encoder compare mode. ? when ttmuds1 and ttmuds0 bits = 00 tencm0 pin tencm1 pin count operation rising edge falling edge both edges high level count down rising edge falling edge both edges low level count up remark detecting the edge of the tencm0 pin is specified by the ttmioc3.ttmeis1 and ttmeis0 bits. figure 8-47. operation example (when valid edge of tencm0 pin is specified to be rising edge and no edge is specified as valid edge of tencm1 pin) 0007h tencm0 tencm1 16-bit counter 0006h count down count up 0005h 0004h 0005h 0006h 0007h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 514 ? when ttmuds1 and ttmuds0 bits = 01 tencm0 pin tencm1 pin count operation rising edge falling edge low level both edges rising edge falling edge high level both edges count down rising edge falling edge both edges high level rising edge falling edge both edges low level count up simultaneous input to tencm0 and tencm1 pins counter does not perform count operation but holds value immediately before. remark detecting the edge of the tencm0 pin is specified by the ttmioc3.ttmeis1 and ttmioc3.ttmeis0 bits. figure 8-48. operation example (when rising edge is specified as valid edge of tencm0 and tencm1 pins) 0006h tencm0 tencm1 16-bit counter 0007h 0008h count up value held count down 0007h 0006h 0005h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 515 ? when ttmuds1 and ttmuds0 bits = 10 tencm0 pin tencm1 pin count operation low level falling edge counter does not perform count operation but holds value immediately before. rising edge low level count down high level rising edge falling edge rising edge high level high level falling edge counter does not perform count operation but holds value immediately before. falling edge low level count up low level rising edge falling edge rising edge counter does not perform count operation but holds value immediately before. rising edge count down falling edge falling edge count up caution specification of the valid edge of the tencm0 and tencm1 pins is invalid. figure 8-49. operation exam ple (count operation when valid edges of tencm0 and tencm1 pins do not overlap) 0007h tencm0 tencm1 16-bit counter 0006h count down count up count down count up count down count up 0005h 0006h 0005h 0005h 0006h 0006h 0007h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 figure 8-50. operation example (count operation when valid edges of tencm0 and tencm1 pins overlap) 0007h tencm0 tencm1 16-bit counter 0006h count down value held count down count up 0005h 0006h 0007h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 516 ? when ttmuds1 and ttmuds0 bits = 11 tencm0 pin tencm1 pin count operation low level falling edge rising edge low level high level rising edge falling edge count down rising edge high level high level falling edge falling edge low level low level rising edge count up simultaneous input to tencm0 and tencm1 pins counter does not perform count operation but holds value immediately before. caution specification of the valid edge of the tencm0 and tencm1 pins is invalid. figure 8-51. operation exam ple (count operation when valid edges of tencm0 and tencm1 pins do not overlap) count up tencm0 tencm1 16-bit counter 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h count down remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 figure 8-52. operation example (count operation when valid edges of tencm0 and tencm1 pins overlap) count up count up count up value held value held tencm0 tencm1 16-bit counter 0004h 0003h 0005h 0008h 0007h 0006h 0007h 0006h 0006h 0005h count down remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 517 <2> ttmecm1 and ttmecm0 bits: timer/counter cl ear function upon match of the compare register the 16-bit counter performs its count operation in accordance with the set value of the ttmecm1 and ttmecm0 bits when the count value of the counter matches the value of the ccra buffer register. ? when ttmecm1 and ttmecm0 bits = 00 the 16-bit counter is not cleared when its c ount value matches the value of the ccra buffer register. ? when ttmecm1 and ttmecm0 bits = 01 the 16-bit counter performs a count operation un der the following condition when its count value matches the value of the ccr0 buffer register. next count operation description count up 16-bit counter is cleared to 0000h. count down count value of 16-bit counter is counted down. ? when ttmecm1 and ttmecm0 bits = 10 the 16-bit counter performs a count operation un der the following condition when its count value matches the value of the ccr1 buffer register. next count operation description count up count value of 16-bit counter is counted up. count down 16-bit counter is cleared to 0000h. ? when ttmecm1 and ttmecm0 bits = 11 the 16-bit counter performs a count operation un der the following condition when its count value matches the value of the ccr0 buffer register. next count operation description count up 16-bit counter is cleared to 0000h. count down count value of 16-bit counter is counted down. the 16-bit counter performs a count operation un der the following condition when its count value matches the value of the ccr1 buffer register. next count operation description count up count value of 16-bit counter is counted up. count down 16-bit counter is cleared to 0000h.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 518 <3> ttmlde bit: transfer function of the set value of the ttmccr0 register to the 16-bit counter when the counter underflows when the ttmlde bit = 1, the set value of the ttm ccr0 register can be transferred to the 16-bit counter when the counter underflows. the ttmlde bit is valid only in the encoder compare mode. ? count operation in range from 0000h to set value of the ttmccr0 register if the 16-bit counter performs a count operat ion when the ttmlde bit = 1 and ttmecm1 and ttmecm0 bits = 01, and when the count value of the counter matches the set value of the ccr0 buffer register when the ttmecm0 bit = 1, the 16-bi t counter is cleared to 0000h if the next count operation is counting up. if the 16-bit counter underflows when the ttmlde bi t = 1, the set value of the ttmccr0 register is transferred to the counter. therefore, the counter can oper ate in a range from 0000h to the set value of the ttmccr0 register in which the upper-limit count value is the set value of the ttmccr0 register and the lower-limit value is 0000h. figure 8-53. operation example (count operation in range from 0000h to set value of ttmccr0 register) 16-bit counter is cleared to 0000h. set value of ttmccr0 register is transferred to 16-bit counter. 16-bit counter underflows. count up count down count value of 16-bit counter matches value of ccr0 buffer register. 16-bit counter set value of ttmccr0 register (n) 0000h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 519 figure 8-54. operation timing (count operation in range from 0000h to set value of ttmccr0 register) peripheral clock ttmesf bit ttmcnt register ttmccr0 register inttteqcm0 signal ttmeof bit ttmeuf bit intttiovm signal count timing signal n 0002h h = down counting l 0001h 0000h n n ? 1 remarks 1. ttmesf bit: bit 0 of tmtm option register 1 (ttmopt1) ttmeof bit: bit 1 of tmtm option register 1 (ttmopt1) ttmeuf bit: bit 2 of tmtm option register 1 (ttmopt1) 2. v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 520 (6) clearing counter to 0000h by en coder clear signal (tecrm pin) the 16-bit counter can be cleared to 0000h by the i nput signal of the tecrm pin in two ways which are selected by the ttmioc3.ttmsce bit. the ttmsce bit also controls, depending its setting, the ttmioc3.ttmzcl, ttmioc3.ttmbcl, ttmioc3.ttm acl, ttmioc3.ttmesc1, and ttmioc3.ttmecs0 bits. the counter can be cleared by the methods descr ibed below only in the encoder compare mode. table 8-11. relationship between ttmsce bit and ttm zcl, ttmbcl, ttmacl, ttmecs1, and ttmecs0 bits clearing method ttmsce bit ttmzcl bit ttmbc l bit ttmacl bit ttmecs1, ttmecs0 bits <1> 0 invalid invalid invalid valid <2> 1 valid valid valid invalid (a) clearing method <1>: by detecting edge of en coder clear signal (tecrm pin) (ttmsce bit = 0) when the ttmsce bit = 0, the 16-bit counter is clear ed to 0000h in synchronization with the peripheral clock if the valid edge of the tecrm pin specified by the ttmecs1 and ttmecs0 bits is detected. at this time, an encoder clear interrupt request signal (inttiecm) is generated. when the ttmsce bit = 0, setting of the ttmzcl, ttmbcl, and ttmacl bits is invalid. figure 8-55. operation example (when ttmsce bit = 0, ttmecs1 and ttmecs0 bits = 01, and ttmuds1 and ttmuds0 bits = 11) peripheral clock ttmcnt register inttiecm encoder input (tencm0 pin input) encoder input (tencm1 pin input) encoder clear input (tecrm pin input) count timing signal n + 1 n counter clear 0000h 0001h 0002h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 521 (b) clearing method <2>: by detecting clear level condition of the tencm0, tencm1, and tecrm pins (ttmsce bit = 1) when the ttmsce bit = 1, the 16-bit counter is clear ed to 0000h if the clear level condition of the tecrm, tencm0, or tencm1 pin specified by the ttmzc l, ttmbcl, and ttmacl bits is detected. at this time, the encoder clear interrupt request signal (inttiecm) is not generated. setting of the ttmecs1 and ttmecs0 bits is invalid when the ttmsce bit = 1. table 8-12. 16-bit counter clear ing condition when ttmsce bit = 1 clear level condition setting input level of encoder pin ttmzcl bit ttmbcl bit ttmacl bit tecrm pin tencm1 pin tencm0 pin 0 0 0 l l l 0 0 1 l l h 0 1 0 l h l 0 1 1 l h h 1 0 0 h l l 1 0 1 h l h 1 1 0 h h l 1 1 1 h h h caution the 16-bit counter is cleared to 0000h when the clear level condition of the ttmzcl, ttmbcl, and ttmacl bits match the input level of the tecrm, tencm1, or tencm0 pin. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 522 figure 8-56. operation example (when ttmsce bit = 1, ttmzcl bit = 1, ttmbcl bit = 0, ttmacl bit = 1, ttmuds1 and ttmuds0 bits = 11, tecrm = high level, tencm1 = low level, and tencm0 = high level) (1/3) (i) if inputting the high level to the tecrm pin lags behind inputting the low level to the tencm1 pin while the counter is counting up, the co unter is cleared after it counts up. peripheral clock clear signal ttmcnt register ttmccr0 register inttteqcm0 signal ttmccr1 register inttteqcm1 signal ttmccr0 register inttteqcm0 signal encoder input (tencm0 pin input) encoder input (tencm1 pin input) encoder clear input (tecrm pin input) count timing signal n + 1 n compare match interrupt request signal is not generated. h l h 0000h n + 1 (when ttmccr0 register is set to n + 1) n (when ttmccr0 register is set to n) 0000h (when ttmccr1 register is set to 0000h) remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 523 figure 8-56. operation example (when ttmsce bit = 1, ttmzcl bit = 1, ttmbcl bit = 0, ttmacl bit = 1, ttmuds1 and ttmuds0 bits = 11, tecrm = high level, tencm1 = low level, and tencm0 = high level) (2/3) (ii) if the high level is input to the tecrm pin at the same time as the low level is input to the tecnm1 pin while the counter is counting up, th e counter is cleared without counting up. peripheral clock clear signal ttmcnt register encoder input (tencm0 pin input) encoder input (tencm1 pin input) encoder clear input (tecrm pin input) count timing signal 0000h n h l h (iii) if the high level is input to the tecrm pin earlie r than the low level is input to the tencm1 pin while the counter is counting up, the count er is cleared without counting up. peripheral clock clear signal ttmcnt register encoder input (tencm0 pin input) encoder input (tencm1 pin input) encoder clear input (tecrm pin input) count timing signal 0000h n h l h remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 524 figure 8-56. operation example (when ttmsce bit = 1, ttmzcl bit = 1, ttmbcl bit = 0, ttmacl bit = 1, ttmuds1 and ttmuds0 bits = 11, tecrm = high level, tencm1 = low level, and tencm0 = high level) (3/3) (iv) if the high level is input to the tecrm pin late r than the low level is input to the tencm1 pin while the counter is counting up, the count er is cleared after it counts up. peripheral clock clear signal ttmcnt register ttmccr0 register inttteqcm0 signal ttmccr1 register inttteqcm1 signal ttmccr0 register inttteqcm0 signal encoder input (tencm0 pin input) encoder input (tencm1 pin input) encoder clear input (tecrm pin input) count timing signal n ? 1 n compare match interrupt request signal is not generated. h l h 0000h n ? 1 (when ttmccr0 register is set to n ? 1) n (when ttmccr0 register is set to n) 0000h (when ttmccr1 register is set to 0000h) remark v850e/if3: m = 1 v850e/ig3: m = 0, 1 if the counter is cleared in this way, a miscount do es not occur even if inputting the signal to the tecrm pin is late, because the clear level condition of the tecrm, tencm1, and tencm0 pins is set and the 16- bit counter is cleared to 0000h when the clear level condition is detected.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 525 (7) notes on using encoder count function (a) if compare match interrupt is not gene rated immediately after operation is started if a value which is the same as that of the ttmtcw register is set to the ttmccr0 or ttmccr1 register and the counter operation is started when the ttmctl2.ttmecc bit = 0, and if the count value (ttmtcw) of the 16-bit counter matches the value of th e ccra buffer register immediately after the start of the operation, t he match is masked and the co mpare match interrupt reques t signal (inttteqcma) is not generated (a = 0, 1). in addition, the 16-bi t counter is not cleared to 0000h by setting the ttmctl2.ttmecm1 and ttmctl2.ttmecm0 bits. ttmcnt register ttmccr1 register inttteqcm1 signal count clock ttmce bit peripheral clock count timing signal count up/down signal ttmtcw ? 1 ffffh h = count down ttmtcw ttmtcw match does not occur. 16-bit counter is not cleared. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 526 (b) if overflow does not occur i mmediately after start of operation if the count operation is resumed when the ttmct l2.ttmecc bit = 1, the 16-bit counter does not overflow if its count value that has been held is ffffh and if the next count operation is counting up. after the counter starts operating and counts up from a count value (value of ttmtcw register = ffffh), the counter overflows from ffffh to 0000h. however, de tection of the overflow is masked, the overflow flag (ttmeof) is not set, and the overflow interr upt request signal (inttti ovm) is not generated. ttmecc bit ttmcnt register ttmtcw register intttiovm signal ttmeof bit count clock ttmce bit peripheral clock count timing signal count up/down signal 0000h ffffh l = count up hold h ttmtcw = ffffh ffffh overflow does not occur. remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 527 8.6.10 encoder compare mode ( ttmmd3 to ttmmd0 bits = 1000) in the encoder compare mode, the encoder is controll ed by using both the ttmccr0 and ttmccr1 registers as compare registers and the input pins for encoder count function (tencm0, tencm1, and tecrm). in this mode, the 16-bit counter can be cleared to 0000h in three ways: when the count value of the counter matches the value of the ccra buffer register (compare match interrupt req uest signal (inttteqcma) is generated), when the edge of the encoder clear inpu t (tecrm pin) is detected and cleared, and when the clear level condition of tencm0, tencm1, and tecrm pi ns is detected and cleared. when the 16-bit counter underflows, the set value of the ttmccr0 register can be transferred to the counter. (1) encoder compare mode operation flow figure 8-57. encoder compare mode operation flow ttmce bit = 1 ttmce bit = 0 encoder compare mode operation processing register initial setting ttmctl1 register (ttmmd3 to ttmmd0 bits), ttmctl2 register (ttmlde, ttmecm1, ttmecm0, ttmuds1, ttmuds0 bits), ttmioc3 register (ttmsce, ttmzcl, ttmacl, ttmbcl, ttmecs1, ttmecs0, ttmeis1, ttmeis0 bits), ttmccr0, ttmccr1 registers, ttmtcw register start end operation end? yes no : see figure 8-58 encoder compare mode operation processing . remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 528 figure 8-58. encoder compar e mode operation processing count up 16-bit counter cleared and started. inttteqcm0 signal generated. 16-bit counter cleared and started. 16-bit counter cleared and started. inttiecm signal generated. ttmecm0 = 1? (ttmctl2) yes no tecrm edge detected? yes no clear level condition of tencm0, tencm1, and tecrm pins detected? yes a a no ttmsce = 1? (ttmioc3) yes no count value matches ccr0 register value? yes no no 16-bit counter cleared and started. inttteqcm1 signal generated. ttmccr0 set value transferred to 16-bit counter. inttteqcm0 signal generated. valid edge of tencm0, tencm1 detected? yes no which count operation? count down ttmecm1 = 1? (ttmctl2) yes no yes ttmlde = 1? (ttmctl2) yes no underflow? yes no count value matches ccr1 register value? remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 529 (2) encoder compare mode operation timing (a) basic timing 1 [register setting conditions] ? ttmctl2.ttmecm1 and ttmctl2.ttmecm0 bits = 01 the 16-bit counter is cleared to 0000h when its count value matches the value of the ccr0 buffer register. ? ttmctl2.ttmlde bit = 1 the set value of the ttmccr0 register is transfe rred to the 16-bit counter when it overflows. ? ttmioc3.ttmsce bit = 0, and ttmioc3.ttmecs1 and ttmioc3.ttmecs0 bits = 00 specification of the edge of encoder clear input signal (tecrm pi n) to be detected and cleared (no edge specified) cm 00 cm 00 ttmccr0 register ccr0 buffer register inttteqcm0 signal ttmccr1 register ccr1 buffer register inttteqcm1 signal ttmesf bit intttiovm signal ttmeof bit ttmeuf bit 0000h ffffh ttmcnt register clear clear clear transfer cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 l cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 03 cm 03 cm 03 cm 03 cm 11 cm 02 cm 12 cm 01 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 530 when the 16-bit counter starts operating (ttmce bit = 0 1), the set value of the ttmtcw register is transferred to the counter and the 16-bit counter starts operating. when the count value of the counter matches the val ue of the ccr0 buffer register, the compare match interrupt request signal (i nttteqcm0) is generated. because the ttmecm0 bit = 1, the 16-bit counter is cleared to 0000h if the next count operation is counting up. when the count value of the 16-bit counter matches t he value of the ccr1 buffer register, the compare match interrupt request signal (inttteqcm1) is gener ated. because the ttmecm1 bit = 0, the 16-bit counter is not cleared to 0000h when its valu e matches that of the ccr1 buffer register. when the ttmlde bit = 1 and ttmecm0 bit = 1, the counter can operate in a range from 0000h to the set value of the ttmccr0 register.
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 531 (b) basic timing 2 [register setting condition] ? ttmctl2.ttmecm1 and ttmctl2.ttmecm0 bits = 00 the 16-bit counter is not cleared even when its co unt value matches the value of the ccra buffer register (a = 0, 1). ? ttmctl2.ttmlde bit = 0 the set value of the ttmccr0 register is not tran sferred to the 16-bit counter after the counter underflows. ? ttmioc3.ttmsce bit = 0, and ttmioc3.ttmecs1 and ttmioc3.ttmecs0 bits = 00 specification of the edge of the encoder clear input signal (te crm pin) to be detected and cleared (no edge specified) cm 10 cm 00 cm 00 ttmccr0 register ccr0 buffer register inttteqcm0 signal ttmccr1 register ccr1 buffer register inttteqcm1 signal ttmesf bit intttiovm signal ttmeof bit ttmeuf bit 0000h ffffh ttmcnt register underflow overflow cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 11 cm 02 cm 12 cm 01 cm 01 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 532 when the 16-bit counter starts operating (ttmce bit = 0 1), the set value of the ttmtcw register is transferred to the 16-bit counter and the counter starts operating. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttteqcm0) is generated. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttteqcm1) is generated. the 16-bit counter is not cleared to 0000h even when its count value matches the value of the ccra buffer register because the ttmecm1 and ttmecm0 bits = 00 (a = 0, 1).
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 533 (c) basic timing 3 [register setting condition] ? ttmctl2.ttmecm1 and ttmctl2.ttmecm0 bits = 11 the count value of the 16- bit counter is cleared to 0000h when it s value matches the value of the ccr0 buffer register. the count value of the 16- bit counter is cleared to 0000h when it s value matches the value of the ccr1 buffer register. ? setting of the ttmctl2.ttmlde bit is invalid. ? ttmioc3.ttmsce bit = 0, and ttmioc3.ttmecs1 and ttmioc3.ttmecs0 bits = 00 specification of the edge of the encoder clear input signal (te crm pin) to be detected and cleared (no edge specified) cm 00 cm 01 cm 01 cm 11 cm 10 ttmccr0 register ccr0 buffer register inttteqcm0 signal ttmccr1 register ccr1 buffer register inttteqcm1 signal ttmesf bit intttiovm signal ttmeof bit ttmeuf bit 0000h ffffh ttmcnt register clear clear clear clear underflow underflow underflow overflow cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 12 cm 12 cm 02 remark v850e/if3: m = 1 v850e/ig3: m = 0, 1
chapter 8 16-bit timer/event counter t (tmt) user?s manual u18279ej3v0ud 534 when the 16-bit counter starts operating (ttmce bit = 0 1), the set value of the ttmtcw register is transferred to the 16-bit counter and the counter starts operating. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttte qcm0) is generated. at this time , the 16-bit counter is cleared to 0000h if the next count operation is counting up. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttte qcm1) is generated. at this time , the 16-bit counter is cleared to 0000h if the next count operation is counting down.
user?s manual u18279ej3v0ud 535 chapter 9 16-bit interval timer m (tmm) timer m (tmm) is a 16-bit interval timer. the v850e/if3 and v850e/ig3 in corporate tmm0 to tmm3. 9.1 overview an outline of tmmn is shown below (n = 0 to 3). ? interval function ? 8 clocks selectable ? 16-bit counter 1 (the 16-bit counter cannot be read during timer count operation.) ? compare register 1 (the compare register cannot be wr itten during timer count operation.) ? compare match interrupt 1 timer m supports only the clear & start mode. the free-running timer mode is not supported.
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 536 9.2 configuration tmmn includes the following hardware (n = 0 to 3). table 9-1. configuration of tmmn item configuration timer register 16-bit counter 1 register tmmn compare register 0 (tmncmp0) control register tmmn control register 0 (tmnctl0) remark n = 0 to 3 figure 9-1. block diagram of tmmn tmnctl0 internal bus f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 controller 16-bit counter match clear inttmneq0 tmncmp0 tmnce tmncks2 tmncks1 tmncks0 selector remarks 1. f xx : peripheral clock frequency 2. n = 0 to 3 (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmmn compare register 0 (tmncmp0) the tmncmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset sets this register to 0000h. the same value can always be written to the tmncmp0 register by software. rewriting the tmncmp0 register is prohibited during tmmn operation (tmnctl0.tmnce bit = 1). tmncmp0 (n = 0 to 3) 12108642 after reset: 0000h r/w address: tm0cmp0 fffff544h, tm1cmp0 fffff554h, tm2cmp0 fffff564h, tm3cmp0 fffff574h 14 0 13119753 15 1
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 537 9.3 control register (1) tmmn control register 0 (tmnctl0) the tmnctl0 register is an 8-bit regist er that controls the tmmn operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tmnctl0 register by software. tmnce tmmn operation disabled (16-bit counter reset asynchronously) tmnce 0 1 internal clock operation enable/disable specification tmnctl0 (n = 0 to 3) 0 0 0 0 tmncks2 tmncks1 tmncks0 654321 after reset: 00h r/w address: tm0ctl0 fffff540h, tm1ctl0 fffff550h, tm2ctl0 fffff560h, tm3ctl0 fffff570h the internal clock control and internal circuit reset for tmmn are performed asynchronously with the tmnce bit. when the tmnce bit is cleared to 0, the internal clock of tmmn is stopped (fixed to low level) and 16-bit counter is reset asynchronously. <7> 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /1024 f xx /2048 tmncks2 0 0 0 0 1 1 1 1 count clock selection tmncks1 0 0 1 1 0 0 1 1 tmncks0 0 1 0 1 0 1 0 1 tmmn operation enabled. start operation clock supply. start tmmn operation. cautions 1. set the tmncks2 to tmncks0 bits when the tmnce bit = 0. however, when changing the value of the tmnc e bit from 0 to 1, it is impossible to set the value of the tmncks2 to tm ncks0 bits simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : peripheral clock frequency
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 538 9.4 operation 9.4.1 interval timer mode in the interval timer mode, an interrupt request signal (inttmneq0) is generated at the interval set by the tmncmp0 register if the tmnctl0.tmnce bit is set to 1. figure 9-2. configuration of interval timer 16-bit counter tmncmp0 register tmnce bit count clock selection clear match signal inttmneq0 signal figure 9-3. basic timing of operation in interval timer mode d 0 d 0 d 0 d 0 d 0 ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal interval (d 0 + 2) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1)
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 539 when the tmnce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the c ounter starts counting. when the count value of the 16-bit counter matches the value of the tmncmp0 register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttmneq0) is generated. the interval can be calculated by the following expression. interval = (set value of tmncmp0 register + 1) count clock cycle figure 9-4. register setting for interval timer mode operation (a) tmmn control register 0 (tmnctl0) 0/1 0 0 0 0 tmnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tmncks2 tmncks1 tmncks0 tmnce (b) tmmn compare register 0 (tmncmp0) if the tmncmp0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 540 (1) interval timer mode operation flow figure 9-5. software processing flow in interval timer mode tmnce bit = 1 tmnce bit = 0 register initial setting tmnctl0 register (tmncks0 to tmncks2 bits) tmncmp0 register initial setting of these registers is performed before setting the tmnce bit to 1. the tmncks0 to tmncks2 bits cannot be set at the same time as when counting starts (tmnce bit = 1). the counter is initialized and counting is stopped by clearing the tmnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal <2> <1>
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 541 (2) interval timer mode operation timing (a) operation if tmncmp0 register is set to 0000h if the tmncmp0 register is set to 0000h, the inttm neq0 signal is generated at each count clock. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tmnce bit tmncmp0 register inttmneq0 signal 0000h interval time count clock cycle 2 interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h (b) operation if tmncmp0 register is set to ffffh if the tmncmp0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttmneq0 signal is generated. ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal ffffh interval time 10001h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle
chapter 9 16-bit interval timer m (tmm) user?s manual u18279ej3v0ud 542 9.5 cautions (1) error on starting timer it takes one clock to generate the first compare matc h interrupt request signal (inttmneq0) after the tmnctl0.tmnce bit is set to 1 and tmmn is started. this is because the value of the 16-bit counter is ffffh when the tmnce bit = 0 and tmmn is started asynchronously to the count clock. count clock 16-bit counter ffffh 0000h 0001h 0002h tmnce bit (2) rewriting the tmncmp0 and tmnctl0 regist ers is prohibited while tmmn is operating. if these registers are rewritten while the tmnctl0.tm nce bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tmnce bit to 0, and re-set the registers.
user?s manual u18279ej3v0ud 543 chapter 10 motor control function 10.1 functional overview timer abn (tabn) and the tmqn option (tmqopn) can be used as an inverter function that controls a motor. it performs a tuning operation with timer aan (taan) and a/d conversion of a/d converters 0 and 1 can be started when the value of tabn matches the value of taan. the follo wing operations can be performed as motor control functions. ? 6-phase pwm output function with 16-bit accura cy (with dead-timer, for upper and lower arms) ? timer tuning operation function (tunable with taan) ? period setting function (period can be changed during operation of crest or valley interrupt) ? compare register rewriting: anytim e rewrite, batch write, or intermittent rewrite (selectable during tabn operation) ? interrupt and transfer culling functions ? dead-time setting function ? a/d trigger timing function of a/d converters 0 and 1 (four types of timing can be generated) ? 0% output and 100% output available ? 0% output and 100% output selectable by crest interrupt and valley interrupt ? forced output stop function ? at valid edge detection by external pin input (tobnoff, toamoff) ? at overvoltage detection by com parator function of a/d converter ? at main clock oscillation stop detection by clock monitor function remark v850e/if3: n = 0, 1, m = 2 v850e/ig3: n = 0, 1, m = 2, 3
chapter 10 motor control function user?s manual u18279ej3v0ud 544 10.2 configuration the motor control function consists of the following hardware. item configuration timer register dead-time counter m compare register tabn dead-time compare register (tabndtc register) control registers tabn option register 0 (tabnopt0) tabn option register 1 (tabnopt1) tabn option register 2 (tabnopt2) tabn option register 3 (tabnopt3) tabn i/o control register 3 (tabnioc3) high-impedance output control re gisters 0, 1 (hzayctla) remark v850e/if3: m = 0 to 3, n = 0, 1, y = 0, 2, 3, a = 0 when y = 1, a = 0, 1 v850e/ig3: m = 0 to 3, n = 0, 1, y = 0 to 3, a = 0, 1 ? 6-phase pwm output can be produced with dead time by using the output of tabn (tobn1, tobn2, tobn3) ? the output level of the 6-phase pwm output can be set individually. ? the 16-bit timer/counter of tabn counts up/down triang ular waves. when the timer/counter underflows and when a period match occurs, an interrupt is generated. interrupt generation, however, can be suppressed up to 31 times. ? taan can execute counting at the same time as tabn (tim er tuning operation function). taan can be set in four ways as it can generate two types of a/d trigger s ources (inttancc0 and inttancc1), and two types of interrupts: on underflow interrupt of tabn (in ttbnov) and period match interrupt (inttbncc0).
chapter 10 motor control function user?s manual u18279ej3v0ud 545 figure 10-1. block diagram of motor control ? carrier ? 3-phase pwm generation tabn ? generation of 6-phase pwm with dead time from 3-phase pwm ? culling control ? a/d trigger selection tmqn option ? a/d trigger timing generation in tuning operation with tabn taan ? pwm generation ? see figure 10-4 . taam ? interrupt control intc high-impedance output controller tobnt1 tobnb1 tobnt2 tobnb2 tobnt3 tobnb3 toam1 tobnoff a/d trigger of a/d converters 0 and 1 valley interrupt (inttbnov) crest interrupt ( inttbncc0) edge detection edge detection noise elimination toamoff noise elimination tobn0 remark v850e/if3: n = 0, 1, m = 2 v850e/ig3: n = 0, 1, m = 2, 3
chapter 10 motor control function user?s manual u18279ej3v0ud 546 figure 10-2. tmqn option tobnt1 high-impedance output controller tobnb1 tabndtc (10-bit dead-time value) tobn1 note (internal signal) tobn0 tobn2 note (internal signal) tobn3 note (internal signal) tabn channel 2 dead-time counter 1 (10 bits) edge detection channel 1 positive phase f/f active setting clear negative phase f/f active setting tobn0 level control output control level control output control counter mask count buffer interrupt culling circuit a/d trigger generator 1 number of masks crest/valley interrupt selection culling enable mask control internal bus tobnt2 tobnb2 channel 3 inttancc0 inttancc1 taan inttbnov inttbncc0 intc a/d trigger source switch circuit (see figure12-6 ) a/d converter n tobnt3 tobnb3 tabtadtn0 tabticcn0 tabtiovn inttbnov_base a/d trigger generator 2 a/d trigger selection ( tabnopt3 register) tabtadtn1 up/down selection a/d trigger selection ( tabnopt2 register) up/down selection note tobn1, tobn2, and tobn3 function alternately as output pins. remark v850e/if3: n = 0, 1, m = 2 v850e/ig3: n = 0, 1, m = 2, 3
chapter 10 motor control function user?s manual u18279ej3v0ud 547 (1) tabn dead-time comp are register (tabndtc) the tabndtc register is a 10-bit compare re gister that specifies a dead-time value. rewriting this register is prohibit ed when the tabnctl0.tabnce bit = 1. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution to generate a dead time period, set a value of 1 or greater to the tabndtc register. while the operation is stopped (tabnctl0.tabn ce bit = 0), the dead time period is not generated and the output levels of the tobnt1 to tobnt3 and tobnb1 to tobnb3 pins are in the initial status. to protect the system, theref ore, allow the tobnt1 to tobnt3 and tobnb1 to tobnb3 pins to go into a high-impedan ce state or select the port mode with setting the output levels of the pins, before stopping the operation. if the dead time period is not necess ary, set the tabndtc register to 0. tabndtc (n = 0, 1) 000000 tabndtc9 to tabndtc0 10 9 after reset: 0000h r/w address: tab0dtc fffff604h, tab1dtc fffff644h 15 0 (2) dead-time counters 1 to 3 the dead-time counters are 10-bit counters that count dead time. these counters are cleared or count up at the rising or falling edge of the tobnm output signal by tabn, and are cleared and stopped when their count value matches the value of the tabndtc register. the count clock of these counters is the same as that set by the tabnctl0.tabncks2 to tabnct l0.tabncks0 bits of tabn. remarks 1. the operation differs when the tabnopt2.tabndtm bit = 1. for details, see 10.4.2 (4) automatic dead-time width narrowi ng function (tabnopt2.tabndtm bit = 1) . 2. n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 548 10.3 control registers (1) tabn option register 0 (tabnopt0) the tabnopt0 register is an 8-bit register that controls the timer qn option function. this register can be read or written in 8-bit or 1- bit units. however, the tabncuf bit is read-only. reset sets this register to 00h. caution the tabncms and tabncuf bits can be set only in the 6-phase pwm output mode. be sure to clear these bits to 0 wh en tabn is used alone. tabnccs3 note 1 tabnopt0 tabnccs2 note 1 tabnccs1 note 1 tabnccs0 note 1 0 tabncms tabncuf tabnovf note 2 <6> <5> <4> 3 <2> <1> after reset: 00h r/w address: tab0opt0 fffff5e5h, tab1opt0 fffff625h tabncms 0 1 compare register rewrite mode selection ? the tabncms bit is valid only when the 6-phase pwm output mode is set (when the tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 111). clear the tabncms bit to 0 in any other mode. ? the tabncms bit can be rewritten while the timer is operating (when the tabnctl0.tabnce bit = 1). ? the following compare registers are rewritten in the batch write mode. tabnccr0 to tabnccr3, tanccr0, tanccr1, tabnopt1, and tabndtc registers batch write mode (transfer operation) anytime write mode tabncuf 0 1 up-count/down-count flag of timer abn the tabncuf bit is valid only when the 6-phase pwm output mode is set (when the tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 111). timer abn is counting up. timer abn is counting down. <7> <0> (n = 0, 1) notes 1. be sure to clear the tabnccs3 to tabnccs0 bits to 0 in the 6-phase pwm output mode. 2. for details of the tabnovf bit, see chapter 7 16-bit timer/event counter ab (tab) .
chapter 10 motor control function user?s manual u18279ej3v0ud 549 (2) tabn option register 1 (tabnopt1) the tabnopt1 register is an 8-bit register that controls the interrupt request signal generated by the timer qn option function. the tabnopt1 register generates the signals output to the interrupt culling circuit, a/d trigger generator 1, and a/d trigger generator 2 shown in figure 10-2. this register can be rewritten when the tabnctl0.tabnce bit is 1. two rewriting modes (batch write mode and anytime wr ite mode) can be selected, depending on the setting of the tabnopt0.tabncms bit. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnice tabnice 0 1 crest interrupt (inttbncc0 signal) enable note do not use inttbncc0 signal (do not use it as count signal for interrupt culling). use inttbncc0 signal (use it as count signal for interrupt culling). tabnopt1 (n = 0, 1) tabnioe 0 tabnid4 tabnid3 tabnid2 tabnid1 tabnid0 <6>54 32 1 tabnioe 0 1 valley interrupt (inttbnov signal) enable note do not use inttbnov signal (do not use it as count signal for interrupt culling). use inttbnov signal (use it as count signal for interrupt culling). after reset: 00h r/w address: tab0opt1 fffff600h, tab1opt1 fffff640h <7> 0 not culled (all interrupts are output) 1 masked (one of two interrupts is output) 2 masked (one of three interrupts is output) 3 masked (one of four interrupts is output) : 28 masked (one of 29 interrupts is output) 29 masked (one of 30 interrupts is output) 30 masked (one of 31 interrupts is output) 31 masked (one of 32 interrupts is output) tabnid4 0 0 0 0 : 1 1 1 1 number of times of interrupt tabnid3 0 0 0 0 : 1 1 1 1 tabnid2 0 0 0 0 : 1 1 1 1 tabnid1 0 0 1 1 : 0 0 1 1 tabnid0 0 1 0 1 : 0 1 0 1 note when using the crest interrupt (inttbncc0 signal) and the valley interrupt (inttbnov signal) as the count signal for interrupt culling or as the a/d trigger signal, set the signal to be used to 1. an a/d trigger is generated at the culled interrupt timing.
chapter 10 motor control function user?s manual u18279ej3v0ud 550 (3) tabn option register 2 (tabnopt2) the tabnopt2 register is an 8-bit register that controls the timer qn option function. this register can be rewritten when the tabnctl0.tabnce bit is 1. however, rewriting the tabndtm bit is prohibited when the tabnce bit is 1. the same value can be rewritten. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) tabnrde tabnopt2 tabndtm tabnatm3 tabnatm2 tabnat3 tabnat2 tabnat1 tabnat0 <6> <5> <4> <3> <2> <1> rewriting the tabndtm bit is disabled during timer operation. if it is rewritten by mistake, stop the timer operation by clearing the tabnce bit to 0, and re-set the tabndtm bit. tabndtm 0 1 dead-time counter operation mode selection dead-time counter counts up normally and, if tobnm output of tabn is at a narrow interval (tobnm output width < dead-time width), the dead- time counter is cleared and counts up again. dead-time counter counts up normally and, if tobnm output of tabn is at a narrow interval (tobnm output width < dead-time width), the dead- time counter counts down and the dead-time control width is automatically narrowed. after reset: 00h r/w address: tab0opt2 fffff601h, tab1opt2 fffff641h <7> <0> n = 0, 1 m = 1 to 3 tabnrde 0 1 transfer culling enable do not cull transfer (transfer timing is generated every time at crest and valley). cull transfer at the same interval as interrupt culling set by the tabnopt1 register. cautions 1. when using interrupt culling (the tabn opt1.tabnid4 to tabnopt1.t abnid0 bits are set to other than 00000), be sure to set the tabnrde bit to 1. therefore, the interrupt and transfer are ge nerated at the same timing. the interrupt and transfer cannot be set separately. if the interrupt and transfer are set separately (tabnrde bit = 0), transfer is not performed normally. 2. to generate a dead time period, set a value 1 or greater to the tabndtc register. while the operation is stopped (tabnctl0.tabnce bit = 0), the dead time period is not generated and the output levels of the tobnt1 to tobnt3 and tobnb1 to tobnb3 pins are in the initial status. to protect the system , therefore, allow the tobnt1 to tobnt3 and tobnb1 to tobnb3 pins go into a high-imp edance state or select the port mode with setting the output levels of the pins, before stopping the operation. if the dead time period is not necess ary, set the tabndtc register to 0.
chapter 10 motor control function user?s manual u18279ej3v0ud 551 (2/2) tabnat3 note 0 1 a/d trigger output control 3 disable output of a/d trigger signal (tabtadtn0) for inttancc1 interrupt. enable output of a/d trigger signal (tabtadtn0) for inttancc1 interrupt. tabnat2 note 0 1 a/d trigger output control 2 disable output of a/d trigger signal (tabtadtn0) for inttancc0 interrupt. enable output of a/d trigger signal (tabtadtn0) for inttancc0 interrupt. tabnat1 note 0 1 a/d trigger output control 1 disable output of a/d trigger signal (tabtadtn0) for inttbncc0 (crest interrupt). enable output of a/d trigger signal (tabtadtn0) for inttbncc0 (crest interrupt). tabnat0 note 0 1 a/d trigger output control 0 disable output of a/d trigger signal (tabtadtn0) for inttbnov (valley interrupt). enable output of a/d trigger signal (tabtadtn0) for inttbnov (valley interrupt). tabnatm3 0 1 tabnatm3 mode selection output a/d trigger signal (tabtadtn0) for inttancc1 interrupt while 16-bit counter is counting up. output a/d trigger signal (tabtadtn0) for inttancc1 interrupt while 16-bit counter is counting down. tabnatm2 0 1 tabnatm2 mode selection output a/d trigger signal (tabtadtn0) for inttancc0 interrupt while 16-bit counter is counting up. output a/d trigger signal (tabtadtn0) for inttancc0 interrupt while 16-bit counter is counting down. note for the setting of the tabnat3 to tabnat0 bits, see chapter 12 a/d converters 0 and 1 .
chapter 10 motor control function user?s manual u18279ej3v0ud 552 (4) tabn option register 3 (tabnopt3) the tabnopt3 register is an 8-bit register that controls the timer qn option function. this register can be rewritten when the tabnctl0.tabnce bit is 1. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tabnopt3 (n = 0, 1) 0 tabnatm7 tabnatm6 tabnat7 tabnat6 tabnat5 tabnat4 tabnatm7 0 1 tabnatm7 mode selection output a/d trigger signal (tabtadtn1) of inttancc1 interrupt while dead-time counter is counting up. output a/d trigger signal (tabtadtn1) of inttancc1 interrupt while dead-time counter is counting down. tabnatm6 0 1 tabnatm6 mode selection output a/d trigger signal (tabtadtn1) of inttancc0 interrupt while dead-time counter is counting up. output a/d trigger signal (tabtadtn1) of inttancc0 interrupt while dead-time counter is counting down. after reset: 00h r/w address: tab0opt3 fffff603h, tab1opt3 fffff643h tabnat7 note 0 1 a/d trigger output control 3 disable output of a/d trigger signal (tabtadtn1) for inttancc1 interrupt. enable output of a/d trigger signal (tabtadtn1) for inttancc1 interrupt. tabnat6 note 0 1 a/d trigger output control 2 disable output of a/d trigger signal (tabtadtn1) for inttancc0 interrupt. enable output of a/d trigger signal (tabtadtn1) for inttancc0 interrupt. tabnat5 note 0 1 a/d trigger output control 1 disable output of a/d trigger signal (tabtadtn1) for inttbncc0 interrupt (crest interrupt). enable output of a/d trigger signal (tabtadtn1) for inttbncc0 interrupt (crest interrupt). tabnat4 note 0 1 a/d trigger output control 0 disable output of a/d trigger signal (tabtadtn1) for inttbnov interrupt (valley interrupt). enable output of a/d trigger signal (tabtadtn1) for inttbnov interrupt (valley interrupt). 6 <5> <4> <3> <2> <1> 7 <0> note for the setting of the tabnat7 to tabnat4 bits, see chapter 12 a/d converters 0 and 1 .
chapter 10 motor control function user?s manual u18279ej3v0ud 553 (5) tabn i/o control register 3 (tabnioc3) the tabnioc3 register is an 8-bit register that c ontrols the output of the timer qn option function. to output from the tobntm pin, set the tabnioc0.t abnoem bit to 1 and then set the tabnioc3 register. the tabnioc3 register can be rewritten on ly when the tabnctl0.tabnce bit is 0. rewriting each bit of the tabnioc3 register is prohi bited when the tabnctl0.tabnce bit is 1; however the same value can be rewritten to each bit of the tabn ioc3 register when the tabnctl0.tabnce bit is 1. this register can be read or written in 8-bit or 1-bit units. reset sets this register to a8h. caution set the tabnioc3 register to the default va lue (a8h) when the timer is used in a mode other than the 6-phase pwm output mode. remark set the output level of the tobntm pin by the tabnioc0 register. tabnolb3 tabnioc3 tabnoeb3 tabnolb2 tabnoeb2 tabnolb1tabnoeb1 00 <6> <5> <4> <3> <2> 1 tabnolbm 0 1 setting of tobnbm pin output level disable inversion of output of tobnbm pin enable inversion of output of tobnbm pin tabnoebm 0 1 setting of tobnbm pin output disable tobnbm pin output. ? when tabnolbm bit = 0, low level is output from tobnbm pin. ? when tabnolbm bit = 1, high level is output from tobnbm pin. enable tobnbm pin output. after reset: a8h r/w address: tab0ioc3 fffff602h, tab1ioc3 fffff642h <7> 0 n = 0, 1 m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 554 (a) output from tob ntm and tobnbm pins the tobntm pin output is controlled by the tabnioc0.tabnolm and tabnioc0.tabnoem bits. the tobnbm pin output is controlled by the tabnioc3.tabnolbm and tabnioc3.tabnoebm bits. a timer output with each setting in the 6-phase pwm output mode is shown below. figure 10-3. tobntm and tobnbm pin output control (without dead time) 16-bit counter fixed to low-level output fixed to high-level output tobntm pin output tabnoem bit = 0, tabnolm bit = 0 (status after reset) tabnoebm bit = 0, tabnolbm bit = 1 (status after reset) tabnoem bit = 1, tabnolm bit = 0 (positive-phase output) tabnoebm bit = 1, tabnolbm bit = 1 (negative-phase output) tabnoem bit = 1, tabnolm bit = 0 (positive-phase output) tabnoebm bit = 1, tabnolbm bit = 0 (positive-phase output) tabnoem bit = 1, tabnolm bit = 1 (negative-phase output) tabnoebm bit = 1, tabnolbm bit = 1 (negative-phase output) tobnbm pin output tobntm pin output tobnbm pin output tobntm pin output tobnbm pin output tobntm pin output tobnbm pin output remark n = 0, 1 m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 555 table 10-1. tobntm pin output tabnolm bit tabnoem bit tabnce bit tobntm pin output 0 x low-level output 0 low-level output 0 1 1 tobntm positive-phase output 0 x high-level output 0 high-level output 1 1 1 tobntm negative-phase output remark n = 0, 1 m = 1 to 3 table 10-2. tobnbm pin output tabnolbm bit tabnoebm bit tabnce bit tobnbm pin output 0 x low-level output 0 low-level output 0 1 1 tobnbm positive-phase output 0 x high-level output 0 high-level output 1 1 1 tobnbm negative-phase output remark n = 0, 1 m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 556 (6) high-impedance output control registers 00, 01, 10, 11, 20, 21, 30, 31 (hzayctl0, hzayctl1) the hzayctl0 and hzayctl1 re gisters are 8-bit registers that contro l the high-impedance state of the output buffer. these registers can be read or written in 8-bit or 1-bit units. however, the hzaydcfn bit is a read-only bit and cannot be written. 16-bit access is not possible. reset sets these registers to 00h. the same value can be always rewritten to the hzayctln register by software. the relationship between detection factor an d the control registers is shown below. high-impedance control factor pins subject to high-impedance control external pin a/d unit (comparator) control register tob0off ? hza0ctl0 ? when low range reference voltage of ani00/ani05 input is exceeded (rising edge) or not attained (falling edge) hza2ctl0 when tob0t1 to tob0t3 are output when tob0b1 to tob0b3 are output ? when full range reference voltage of ani00/ani05 input is exceeded (rising edge) or not attained (falling edge) hza2ctl1 when toa21 is output toa2off ? hza0ctl1 tob1off ? hza1ctl0 note ? when low range reference voltage of ani10 to ani12 and ani15 to ani17 inputs is exceeded (rising edge) or not attained (falling edge) hza3ctl0 when tob1t1 to tob1t3 are output when tob1b1 to tob1b3 are output ? when full range reference voltage of ani10 to ani12 and ani15 to ani17 inputs is exceeded (rising edge) or not attained (falling edge) hza3ctl1 when toa31 note is output toa3off note ? hza1ctl1 note note v850e/ig3 only caution high-impedance control is pe rformed only when a port pin is set to function as indicated in the above table.
chapter 10 motor control function user?s manual u18279ej3v0ud 557 (1/3) hzaydcen hzaydcen 0 1 high-impedance output control disable high-impedance output control operation. pins can function as output pins. enable high-impedance output control operation. hzayctln hzaydcmn hzaydcnn hzaydcpn hzaydctn hzaydccn 0 hzaydcfn <6> 5 4 <3> <2> 1 hzaydcmn 0 1 condition of clearing high-impedance state by hzaydccn bit setting of the hzaydccn bit is valid regardless of the external pin note 2 input. setting of the hzaydccn bit is invalid while the external pin note 2 input holds a level detected as abnormal (active level). after reset: 00h r/w address: hza0ctl0 fffff610h, hza0ctl1 fffff611h, hza1ctl0 fffff618h, hza1ctl1 fffff619h note 1 , hza2ctl0 fffff650h, hza2ctl1 fffff651h, hza3ctl0 fffff658h, hza3ctl1 fffff659h <7> <0> rewrite the hzaydcmn bit when the hzaydcen bit = 0. v850e/if3 n = 0, 1 y = 0, 2, 3 n = 0 when y = 1 v850e/ig3 n = 0, 1 y = 0 to 3 notes 1. v850e/ig3 only 2. ? v850e/if3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins ? v850e/ig3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza1ctl1: toa3off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins
chapter 10 motor control function user?s manual u18279ej3v0ud 558 (2/3) hzaydcnn 0 0 1 1 hzaydcpn 0 1 0 1 external pin note 1 input edge specification no valid edge (setting the hzaydcfn bit by external pin note 1 input is prohibited). rising edge of the external pin note 1 input is valid (abnormality is detected by rising edge input) note 2 . falling edge of the external pin note 1 input is valid (abnormality is detected by falling edge input) note 2 . setting prohibited ? rewrite the hzaydcnn and hzaydcpn bits when the hzaydcen bit is 0. ? for the edge specification of the intp00, intp02, intp08, and intp10 pins, see 20.4.2 (1) external interrupt rising edge specification register 0 (intr0), external interrupt falling edge specification register 0 (intf0) and (2) external interrupt rising edge specification register 1 (intr1), external interrupt falling edge specification register 1 (intf1) . ? the edge of the external pins must be specified starting from the tob0off, tob1off, toa2off, and toa3off note 3 pins. then the edge of the external pins other than the tob0off, tob1off, toa2off, and toa3off note 3 pins must be specified. otherwise, the undefined edge may be detected when the edges of the tob0off, tob1off, toa2off, and toa3off note 3 pins are specified. ? high-impedance output control is performed when the valid edge is input after the operation is enabled (by setting hzaydcen bit to 1). if the external pin note 1 is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. notes 1. ? v850e/if3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins ? v850e/ig3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza1ctl1: toa3off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins 2. for detecting the voltage of a com parator exceeding the reference voltage, set the rising edge input. for detecting the voltage of a comparator which has not attained the reference voltage, set the falling edge input. 3. v850e/ig3 only
chapter 10 motor control function user?s manual u18279ej3v0ud 559 (3/3) hzaydccn 0 1 high-impedance output control clear bit no operation pins that have gone into a high-impedance state are output-enabled by software and the hzaydcfn bit is cleared to 0. ? pins can function as output pins when the hzaydcm bit = 0, regardless of the status of the external pin note . ? if an edge indicating abnormality is input to the external pin note (which is set by the hzaydcnn and hzaydcpn bits) when the hzaydcm bit = 1, the hzaydccn bit is invalid even if it is set to 1. ? the hzaydccn bit is always 0 when it is read. ? the hzaydccn bit is invalid even if it is set to 1 when the hzaydcen bit = 0. ? simultaneously setting the hzaydctn and hzaydccn bits to 1 is prohibited. hzaydcfn high-impedance output status flag indicates that output of the pin is enabled. ? this bit is cleared to 0 when the hzaydcen bit = 0. ? this bit is cleared to 0 when the hzaydccn bit = 1. indicates that the pin goes into a high-impedance state. ? this bit is set to 1 when the hzaydctn bit = 1. ? this bit is set to 1 when an edge indicating abnormality is input to the external pin note (which is detected according to the setting of the hzaydcnn and hzaydcpn bits). 0 1 hzaydctn 0 1 high-impedance output trigger bit no operation pins are made to go into a high-impedance state by software and the hzaydcfn bit is set to 1. ? if an edge indicating abnormality is input to the external pin note 2 (which is detected according to the setting of the hzaydcnn and hzaydcpn bits), the hzaydctn bit is invalid even if it is set to 1. ? the hzaydctn bit is always 0 when it is read because it is a software-triggered bit. ? the hzaydctn bit is invalid even if it is set to 1 when the hzaydcen bit = 0. ? simultaneously setting the hzaydctn and hzaydccn bits to 1 is prohibited. note ? v850e/if3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins ? v850e/ig3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza1ctl1: toa3off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins
chapter 10 motor control function user?s manual u18279ej3v0ud 560 figure 10-4. high-impedance output controller configuration taa2 tmqop0 toa21 tob0b1 tob0t1 tob0b2 tob0t2 tob0b3 tob0t3 tob1b1 tob1t1 tob1b2 tob1t2 tob1b3 tob1t3 hza0ctl1 hza0ctl0 clock monitor circuit main oscillator internal oscillator analog filter edge detection edge detection intp00/ toa2off intp08/ tob0off intp02 note / toa3off note intp10/ tob1off analog filter taa3 tmqop1 toa31 note x1 x2 intp08 intp00 pll hza1ctl1 note hza1ctl0 analog filter edge detection edge detection analog filter intp10 intp02 l side f side ani00/ ani05 noise elimination selector cmp0nfen bit hza2ctl0 digital filter edge detection intcmp0l noise elimination hza2ctl1 digital filter edge detection intcmp0f l side f side ani11/ ani16 noise elimination ani12/ ani17 ani10/ ani15 hza3ctl0 digital filter edge detection intcmp1l noise elimination hza3ctl1 digital filter edge detection intcmp1f selector cmp0nfen bit selector cmp1nfen bit selector cmp1nfen bit note note v850e/ig3 only remark when referring to figure 10-4 , also refer to figures 12-3 and 12-4 .
chapter 10 motor control function user?s manual u18279ej3v0ud 561 (a) setting procedure (i) setting of high-impedance control operation <1> set the hzaydcmn, hzaydcnn, and hzaydcpn bits. <2> set the hzaydcen bit to 1 (enable high-impedance control). (ii) changing setting after enablin g high-impedance control operation <1> clear the hzaydcen bit to 0 (to stop the high-impedance control operation). <2> change the setting of the hzay dcmn, hzaydcnn, and hzaydcpn bits. <3> set the hzaydcen bit to 1 (to enable t he high-impedance control operation again). (iii) resuming output when pins are in high-impedance state if the hzaydcmn bit is 1, set the hzaydccn bit to 1 to clear the high-impedance state after the valid edge of the external pin note is detected. however, the high-im pedance state cannot be cleared unless this bit is set while the input level of the external pin note is inactive. <1> set the hzaydccn bit to 1 (command si gnal to clear the high-impedance state). <2> read the hzaydcfn bit and check the flag status. <3> return to <1> if the hzaydcfn bit is 1. the input level of the external pin note must be checked. the pin can function as an output pin if the hzaydcfn bit is 0. (iv) to make the pin to go into a high-impedance state by software the hzaydctn bit must be set to 1 by software to make the pin to go into a high-impedance state while the input level of the external pin note is inactive. the following procedure is an example in which the setting is not dependent upon the setting of the hzaydcmn bit. <1> set the hzaydctn bit to 1 (high-impedance output command). <2> read the hzaydcfn bit to check the flag status. <3> return to <1> if the hzaydcfn bit is 0. the input level of the external pin note must be checked. the pin is in a high-impedance state if the hzaydcfn bit is 1. however, if the external pin note is not used with the hzaydcpn bit and hzaydcnn bit cleared to 0, the pin goes into a high-impedance state when the hzaydctn bit is set to 1. note ? v850e/if3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins ? v850e/ig3 hza0ctl0: tob0off pin, hza0ctl1: toa2off pin, hza1ctl0: tob1off pin, hza1ctl1: toa3off pin, hza2ctl0: ani00/ani05 pin, hza2ctl1: ani00/ani05 pin, hza3ctl0: ani10 to ani12, ani15 to ani17 pins, hza3ctl1: ani10 to ani12, ani15 to ani17 pins
chapter 10 motor control function user?s manual u18279ej3v0ud 562 10.4 operation 10.4.1 system outline (1) outline of 6-phase pwm output the 6-phase pwm output mode is used to generate a 6-ph ase pwm output waveform, by using tabn and the tabn option in combination. the 6-phase pwm output mode is enabled by setting th e tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits of tabn to ?111?. one 16-bit counter and four 16-bit compare registers of tabn are used to generate a basic 3-phase wave. the functions of the compar e registers are as follows. taan can perform a tuning operation with tabn to start a conversion trigger source for a/d converters 0 and 1. remark n = 0, 1 compare register function settable range tabnccr0 register setting of cycle 0002h m fffeh tabnccr1 register specifying output width of phase u 0000h i m + 1 tabnccr2 register specifying output width of phase v 0000h j m + 1 tabnccr3 register specifying output width of phase w 0000h k m + 1 remark m = set value of tabnccr0 register i = set value of tabnccr1 register j = set value of tabnccr2 register k = set value of tabnccr3 register a dead-time interval is generated from the basic 3-ph ase wave generated by using three 10-bit dead-time counters and one compare register to create a wave with a reverse phase to that of the basic 3-phase wave. then a 6-phase pwm output waveform (u, u, v, v, w, and w) is generated. the 16-bit counter for generating the basic 3-phase wave counts up or down. after the operation has been started, this counter counts up. when its count va lue matches the cycle set to the tabnccr0 register, the counter starts counting down. w hen the count value matches 0001h, the counter counts up again. this means that a value two times higher than the value set to the tabnccr0 register +1 is the carrier cycle. 10-bit dead-time counters 1 to 3 that generate the dead-time interval count up . therefore, the value set to the tabn dead-time compare register (tabndtc) is used as a dead-time value as is. because three counters are used, dead time can be generated independently in phases u, v, and w. however, because there is only one register that specifies a dead-time value (tabndtc), t he same dead-time value is used in the three phases.
chapter 10 motor control function user?s manual u18279ej3v0ud 563 figure 10-5. outline of 6-phase pwm output mode tot1 tobnt1 pin output (u) tob1 tobnb1 pin output (u) tobnt2 pin output (v) tobnb2 pin output (v) tobnt3 pin output (w) tobnb3 pin output (w) tot2 tob2 tot3 tob3 16-bit counter up/down selection tabnccr0 register (carrier period) tobn1 (internal signal) note 0001h tobn2 (internal signal) note tobn3 (internal signal) note tabnccr1 register (phase u output data) tabnccr2 register (phase v output data) tabnccr3 register (phase w output data) dead-time counter 1 dead-time counter 2 dead-time counter 3 tabndtc register (dead-time value) inttbnov signal (valley interrupt) inttbncc0 signal (crest interrupt) tobn0 pin output interrupt culling circuit a/d trigger generator inttbnov_base note tobn1, tobn2, and tobn3 function alternately as output pins. remark n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 564 figure 10-6. timing chart of 6-phase pwm output mode 16-bit counter m (carrier data) tabnccr0 register tobn1 signal (internal signal) tobn2 signal (internal signal) tobn3 signal (internal signal) tabndtc register tobnt1 pin output (u) tobnb1 pin output (u) dead-time counter 1 dead-time counter 2 dead-time counter 3 tabnccr1 register tabnccr2 register tabnccr3 register n (dead-time value) i (phase u data) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 tobn0 pin output basic phase u output width = (m + 1 ? i) 2 basic phase v output width = (m + 1 ? j) 2 basic phase w output width = (m + 1 ? k) 2 phase u output width = (m + 1 ? i) 2 ? n phase v output width = (m + 1 ? j) 2 ? n phase w output width = (m + 1 ? k) 2 ? n dead-time width = n phase u output width = (m + 1 ? i) 2 + n carrier cycle = (m + 1) 2 tobnt2 pin output (v) tobnb2 pin output (v) tobnt3 pin output (w) tobnb3 pin output (w) phase v output width = (m + 1 ? j) 2 + n phase w output width = (m + 1 ? k) 2 + n 0000h cautions 1. set the value ?m? of th e tabnccr0 register in a range of 0002h m fffeh in the 6-phase pwm output mode. 2. only a value of up to ?m + 1? can be set to the tabnccr1, tabnccr2, and tabnccr3 registers. 3. the output is 100% if ?0000h? is set to the tabnccr1, tabnccr2, and tabnccr3 registers. the output is 0% if ?m + 1? is set to the tabnccr1, tabnccr2, and tabnccr3 registers. the output (duty 50%) rises at the crest (m + 1) of the 16-bit counter and falls at the valley (0000h) if ?m + 2? or higher is set to th e tabnccr1, tabnccr2, a nd tabnccr3 registers. 4. if the value calculated using an equation for the output width of th e positive phase side of the u, v, or w phase (such as ((m + 1 ? i) 2 ? n)) is 0 or less, the output converges at 0 (0%). if the range of the calculated value is from ((m + 1) 2 ? n) to ((m + 1) 2), the output converges at ((m + 1) 2) (100%). remark n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 565 (2) interrupt requests two types of interrupt requests are available: the in ttbncc0 (crest interrupt) signal and inttbnov (valley interrupt) signal. the inttbncc0 and inttbnov signals can be culled by using the tabnopt1 register. for details of culling interrupts, see 10.4.3 interrupt culling function . ? inttbncc0 (crest interrupt) signal: interrupt signal indicating matching between the value of the 16-bit counter that counts up and the va lue of the tabnccr0 register ? inttbnov (valley interrupt) signal: interrupt signal indicating matching between the value of the 16-bit counter that counts do wn and the value 0001h (3) rewriting registers during timer operation the following registers have a buffer register and can be rewritten in the anytime rewriting mode, batch rewrite mode, or intermittent batch rewrite mode. related unit register timer aan taan capture/compare register 0 (taanccr0) taan capture/compare register 1 (taanccr1) timer abn tabn capture/compare register 0 (tabnccr0) tabn capture/compare register 1 (tabnccr1) tabn capture/compare register 2 (tabnccr2) tabn capture/compare register 3 (tabnccr3) timer qn option tabn option register 1 (tabnopt1) remark n = 0, 1 for details of the transfer function of the compare register, see 10.4.4 operation to rewrite register with transfer function . (4) counting-up/-down operation of 16-bit counter the operation status of the 16-bit co unter can be checked by using the t abncuf bit of tabn option register 0 (tabnopt0). status of tabncuf bit status of 16-bit counter range of 16-bit counter value tabncuf bit = 0 counting up 0000h ? m tabncuf bit = 1 counting down (m+1) ? 0001h remarks 1. m = set value of tabnccr0 register 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 566 figure 10-7. interrupt and up/down flag 16-bit counter m (carrier data) tabnccr0 register tobnt1 pin output (u) tobnb1 pin output (u) tabnccr1 register tabnccr2 register tabnccr3 register i (phase u data) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 tobnt2 pin output (v) tobnb2 pin output (v) inttbncc0 (crest interrupt) inttbnov (valley interrupt) tabncuf (up/down flag) tobnt3 pin output (w) tobnb3 pin output (w) 0000h tobn0 pin output remark n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 567 10.4.2 dead-time control (generat ion of negative-phase wave signal) (1) dead-time control mechanism in the 6-phase pwm output mode, compare registers 1 to 3 (tabnccr1, tabnccr2, and tabnccr3) are used to set the duty factor, and compare register 0 (tabnc cr0) is used to set the cycle. by setting these four registers and by starting the operation of tab, three types of pwm output waves (basic 3-phase waves) with a variable duty factor are generated. these three pwm output waves are input to the timer qn option unit (tmqopn) and their inverted signal with dead-time is created to generate three sets of (six) pwm waves. the tmqopn unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with the count clock of tabn, and a tabn dead-time comp are register (tabndtc) that specifies dead time. if ?a? is set to the tabndtc register, the dead-time value is ?a?, and interval ?a? is created between a positive- phase wave and a negative-phase wave. figure 10-8. pwm output waveform with dead time (1) (a) when dead time is in serted (tabndtc register = a) a a 16-bit counter tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output (b) no dead time (t abndtc register = 000h) 0 0 0000h 16-bit counter tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output remark n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 568 (2) pwm output of 0%/100% the v850e/if3 and v850e/ig3 are c apable of 0% waveform output an d 100% waveform output for pwm output. a low level is continuously output from tobntm pin as the 0% waveform output. a high level is continuously output from tobntm pin as the 100% waveform output. the 0% waveform is output by setting the tabnccrm regi ster to ?m + 1? when the tabnccr0 register = m. the 100% waveform is output by setting the tabnccrm register to ?0000h?. rewriting the tabnccrm register is enabled while the timer is operating, and 0% waveform output or 100% waveform output can be selected at the point of t he crest interrupt (inttbncc0) and valley interrupt (inttbnov). remark n = 0, 1, m = 1 to 3 figure 10-9. 0% pwm output waveform (with dead time) i i 16-bit counter 0% output tabnccr0 register tabnccr1 register tobnt1 pin output tobnb1 pin output ccr1 buffer register i i i i i m i i i m + 1 m + 1 m + 1 m + 1 i i <4> <3> <2> <1> forced timing of timer output 0000h 0% output <1> 0% output is selected by the valley in terrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers t he timer output. this produces the 0% output. <2> 0% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 0% output. <3> 0% output is selected by the crest inte rrupt (with a match with the 16-bit counter). the crest interrupt forcibly raises the timer outpu t, but lowering the timer output takes precedence when the value of the tabnccrm register matches the value of the 16-bit counter. as a result, the 0% wave is output. <4> 0% output is canceled by the valley inte rrupt (without a match wit h the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 0% output. remark means forced raising and means forced lowering.
chapter 10 motor control function user?s manual u18279ej3v0ud 569 figure 10-10. 100% pwm output waveform (with dead time) i i i i i i m i i i i i 0000h 0000h 0000h 0000h 0000h i 100% output 100% output <1> <2> <3> <4> 16-bit counter tabnccr0 register tabnccr1 register tobnt1 pin output tobnb1 pin output ccr1 buffer register forced timing of timer output <1> 100% output is selected by the valley in terrupt (with a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when the value of the tabnccrm register matches the value of the 16-bit counter. as a result, the 100% output is produced. <2> 100% output is canceled by the valley inte rrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 100% output. <3> 100% output is selected by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this produces the 100% output. <4> 100% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 100% output. remark means forced raising and means forced lowering.
chapter 10 motor control function user?s manual u18279ej3v0ud 570 figure 10-11. pwm output waveform from 0% to 100% and from 100% to 0% (with dead time) 0% output 0% output m 0000h 0000h 0000h 0000h 0000h 0000h m + 1 m + 1 m + 1 m + 1 0000h 100% output 100% output <1> <1> <2> <2> <1> 16-bit counter tabnccr0 register tabnccr1 register tobnt1 pin output tobnb1 pin output ccr1 buffer register forced timing of timer output 100% output <1> the valley interrupt selects 100% 0% or 0% 100% output. output can be selected from 100% 0% or 0% 100% immediately after the timer has been started. <2> the crest interrupt selects 100% 0% output. the crest interrupt selects 100% 0% output by using the timer output forced raising function and by a match between the 16-bit counter value and the tabnccr0 register value. (3) output wave in vicinity of 0% and 100% output if an interrupt is generated because the value of the 16-bi t counter matches the value of the compare register while dead time is being counted, the dead-time counter is cleared and starts its count operation again. the output waveform of dead-time control in the vicinity of 0% and 100% output is shown below.
chapter 10 motor control function user?s manual u18279ej3v0ud 571 figure 10-12. pwm output waveform with dead time (2) (a) 0% output (tabnccrm register = m + 1, t abnccr0 register = m, tabndtc register = a) 16-bit counter 000h (dead-time counter m does not count.) h l l 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output (b) in vicinity of 0% ou tput (tabnccrm register = i m + 1 ? a/2, tabnccr0 register = m, tabndtc register = a) dead-time counter is cleared and counts again. negative-phase output width: (m + 1 ? i) 2 + a (e.g., output width is 2 + a where tabnccrm register = m.) l 16-bit counter 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output 000h (c) in vicinity of 100% output (tabnccrm register = i a/2, tabnccr0 register = m, tabndtc register = a) counter is cleared and counts again. positive-phase output width: (m + 1 ? i) 2 ? a (e.g., output width is 2 ? a where tabnccrm register = 0001h.) 16-bit counter 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output 000h (d) 100% output (tabnccrm register = 0000h, tabn ccr0 register = m, tabndtc register = a) 000h (dead-time counter m does not count.) 16-bit counter 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output remark n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 572 (4) automatic dead-time width narro wing function (tabnopt2.tabndtm bit = 1) the dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the tabnopt2.tabndtm bit to 1. by setting the tabndtm bit to 1, the dead-time counter is not cleared, but starts down counting if the tobnm (internal signal) output of timer ab changes during dead-time counting. the following timing chart shows the operation of the dea d-time counter when the tabndtm bit is set to 1. figure 10-13. operation of dead-time counter m (1) (a) in vicinity of 0% output (tabnccrm register = i m + 1 ? a/2, tabnccr0 register = m, tabndtc register = a) dead-time counter m starts counting down. negative-phase wave output width: (m + 1 ? i) 4 (e.g., output width is 4 where tabnccrm = m). 16-bit counter 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output 000h (b) in vicinity of 100% output (tabnccrm register = i a/2, tabnccr0 register = m, tabndtc register = a) dead-time counter m starts counting down. positive-phase wave output width: (m + 1 ? i) 2 ? (i 2) (e.g., output width is m 2 ? 2 where tabnccrm = 0001h.) note 16-bit counter 0000h tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output 000h note the output width of the first wave differs from t hat of the second and subsequent waves immediately after the tabnctl0.tabnce bit has been set. the first wave is shorter than the second wave because the dead time is fully counted. remark n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 573 (5) dead-time control in case of incorrect setting usually, the tobnm (internal signal) output of tabn c hanges only once during dead-time counting, only in the vicinity of 0% and 100% output. this section shows an example where t he tabnccr0 register (carrier cycle) and tabndtc register (dead-time value) are incorrectly set. if these registers are incorrectly set, the tobnm (internal signal) output of tabn c hanges more than once during dead-time counting. the following flowchart shows the 6-phase pwm output waveform in this case. figure 10-14. operation of dead-time counter m (2) (a) when tabnopt2.tabndtm bit = 0, tabnccr0 register = 0006h, tabndtc register = 000fh, tabnccrm register = 0004h counter cleared counter is not cleared but continues counting. 000h 001h 002h 003h 004h 005h 006h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 000h 001h 16-bit counter tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output (b) when tabnopt2.tabndtm bit = 1, tabnccr0 register = 0006h, tabndtc register = 000fh, tabnccrm register = 0002h starts counting down. output does not change and dead-time counter m continues counting down. 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 009h 008h 007h 006h 005h 004h 003h 002h 001h 001h 002h 003h 004h 003h 002h 001h 000h 000h 16-bit counter tobnm signal (internal signal) dead-time counter m tobntm pin output tobnbm pin output remark n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 574 10.4.3 interrupt culling function ? the interrupts to be culled are inttbncc0 (c rest interrupt) and inttbnov (valley interrupt). ? the tabnopt1.tabnice bit is used to enable output of the inttbncc0 interrupt and specify the count signal for interrupt culling. ? the tabnopt1.tabnioe bit is used to enable output of the inttbnov interrupt and specify the count signal for interrupt culling. ? the tabnopt1.tabnid4 to tabnopt1.tabnid0 bits are used to specify the number of interrupts to be culled, specified for the count signals for interrupt culling. the interrupts are masked for the spec ified number of culling counts and an in terrupt occurs at the next interrupt timing. ? the tabnopt2.tabnrde bit is used to specify whether transfer is to be culled or not. if it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling. if it is specified that transfer is not to be cu lled, transfer is executed at the transfer timing after the tabnccr1 register has been written. ? the tabnopt0.tabncms bit is used to specify whether th e registers with a transfer f unction are batch rewritten or anytime rewritten. the values of the registers are updated in synchronization with transferring when the tabncms bit is 0. when the tabncms bit is 1, the values of the registers are immediately updated when a new value is written to the registers. transfer is performed from the tabnccrm register to the ccrm buffer register in synchronization with interrupt culling timing. cautions 1. when using the interrupt culling func tion in the batch rewrite mode (transfer mode), execute the function in the intermittent ba tch rewrite mode (tran sfer culling mode). 2. an interrupt is generate d at the timing after culling.
chapter 10 motor control function user?s manual u18279ej3v0ud 575 (1) interrupt culling operation figure 10-15. interrupt culling operation when t abnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 1, tabnopt2.tabnrde bit = 1 (crest/valley interrupt output) 16-bit counter tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00000 (not culled) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001 (1 mask) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00010 (2 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00011 (3 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00100 (4 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00101 (5 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00110 (6 masks) inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal remarks 1. : culled interrupt 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 576 figure 10-16. interrupt culling operation when t abnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 0, tabnopt2.tabnrde bit = 1 (crest interrupt output) 16-bit counter tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00000 (not culled) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001 (1 mask) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00010 (2 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00011 (3 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00100 (4 masks) inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal remarks 1. : culled interrupt 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 577 figure 10-17. interrupt culling operation when t abnopt1.tabnice bit = 0, tabnopt1.tabnioe bit = 1, tabnopt2.tabnrde bit = 1 (valley interrupt output) 16-bit counter tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00000 (not culled) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001 (1 mask) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00010 (2 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00011 (3 masks) tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00100 (4 masks) inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbncc0 signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal inttbnov signal remarks 1. : culled interrupt 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 578 (2) to alternately output crest interrupt (inttbncc0) and valley interrupt (inttbnov) to alternately output the crest and valley in terrupts, set both the tabnopt1.tabnice and tabnopt1.tabnioe bits to 1. figure 10-18. crest/valley interrupt output (a) tabnopt0.tabncms bit = 0, tabnopt2.tabnrde bit = 1 (with transfer culling control) 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal 00010 00010 00100 transfer timing of rewriting transfer culling count from 2 to 4 00100 inttbncc0 signal remarks 1. transfer is performed when the culled interrupt is output. the other transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1 (b) tabncms bit = 1, tabnrde bit = 0 or 1 (without transfer control) 00010 00010 00100 reflected immediately 00100 timing of rewriting transfer culling count from 2 to 4 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal inttbncc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 579 (3) to output only crest interrupt (inttbncc0) set the tabnopt1.tabnice bit to 1 and set the tabnopt1.tabnioe bit to 0. figure 10-19. crest interrupt output (a) tabnopt0.tabncms bit = 0, tabnopt2.tabnrde bit = 1 (with transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal inttbncc0 signal remarks 1. transfer is performed when the culled interrupt is output. the other transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1 (b) tabnopt0.tabncms bit = 1, tabnopt0.tabnrde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal inttbncc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 580 (4) to output only valley interrupt (inttbnov) set the tabnopt1.tabnice bit to 0 and set the tabnopt1.tabnioe bit to 1. figure 10-20. valley interrupt output (a) tabnopt0.tabncms bit = 0, tabnopt2.tabnrde bit = 1 (with transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal inttbncc0 signal remarks 1. transfer is performed when the culled interrupt is output. the other transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1 (b) tabnopt0.tabncms bit = 1, tabnopt0.tabnrde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tabnid4 to tabnid0 bits tabnid4 to tabnid0 bits (slave bit) inttbnov signal inttbncc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt 3. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 581 10.4.4 operation to rewrite re gister with transfer function the following seven registers are provided with a transfer f unction and used to control a motor. each of registers has a buffer register. ? tabnccr0: register that specifies the cycle of the 16-bit counter (tab) ? tabnccr1: register that specifies the duty factor of tobnt1 (u) and tobnb1 (u) ? tabnccr2: register that specifies the duty factor of tobnt2 (v) and tobnb2 (v) ? tabnccr3: register that specifies the duty factor of tobnt3 (w) and tobnb3 (w) ? tabnopt1: register that specifies the culling of interrupts ? taanccr0: register that specifies the a/d conversion start trigger generation timing (taan during tuning operation) ? taanccr1: register that specifies the a/d conversion start trigger generation timing (taan during tuning operation) the following three rewrite modes are provided in the registers with a transfer function. ? anytime rewriting mode this mode is specified by setting the tabnopt0.tabncms bit to 1. the setting of the tabnopt2.tabnrde bit is ignored. in this mode, each compare register is updated independe ntly, and the value of the compare register is updated as soon as a new value is written to it. ? batch rewrite mode (transfer mode) this mode is specified by setting the tabnopt0 .tabncms bit to 0, the tabnopt1.tabnid4 to tabnopt1.tabnid0 bits to 00000, and the tabnopt2.tabnrde bit to 0. when data is written to the tabnccr1 register, the seven r egisters are transferred to the buffer register all at once at the next transfer timing. unless the tabnccr1 register is rewritten, the transfer operation is not performed even if the other six registers are rewritten. the transfer timing is the timing of each crest (match between the 16-bit counter value and tabnccr0 register value) and valley (match between the 16-bit count er value and 0001h) regardless of the interrupt. ? intermittent batch rewrite mode (transfer culling mode) this mode is specified by setting the tabnopt0.tabn cms bit to 0 and the tabnopt2.tabnrde bit to 1. when data is written to the tabnccr1 register, the seven r egisters are transferred to the buffer register all at once at the next transfer timing. unless the tabnccr1 register is rewritten, the transfer operation is not performed even if the other six registers are rewritten. if interrupt culling is specified by the tabnopt1 register , the transfer timing is also culled as the interrupts are culled, and the seven registers are transferred all at once at the culled timing of crest interrupt (match between the 16-bit counter value and tabnccr0 register value) or valley interrupt (match between the 16-bit counter value and 0001h). for details of the interrupt culling function, see 10.4.3 interrupt culling function .
chapter 10 motor control function user?s manual u18279ej3v0ud 582 (1) anytime rewriting mode this mode is specified by setting the tabnopt0.tabncms bit is 1. the setting of the tabnopt2.tabnrde bit is ignored. in this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the count value. if a regi ster with transfer function is rewritten in this mode after the count value of the 16-bit counter matches the value of the tabn ccrm register, the rewritten value is not reflected because the next match is ignored after the first match has occurred. if the register is rewritten during up counting, the new register value becomes valid after the counter has started counting down. figure 10-21. timing of reflecting rewritten value operating clock (f xx /2) tabnccr0 register ba ccr0 buffer register ba note note after writing to a register (tabnccr0, tabn ccr2, tabnccr3, tabnopt1, taanccr0, or taanccr1), the value is transferred to the internal buffer regist er during the fourth cycle of the operating clock. however, the value of only the tabnccr1 register is transferred after 5 more clocks. (a) rewriting tabnccr0 register even if the tabnccr0 register is rewritten in the anytime rewriting mode, the new value may not be reflected in some cases. figure 10-22. example of rewriting tabnccr0 register 16-bit counter <1> <2> <1> <2> rewriting during period <1> (rewriting during up counting) if the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will match the value of the 16-bit counter. if the new value is less than the value of the 16-bit counter, it will not match the value of the counter. as a result, the 16- bit counter overflows and continues counting up from 0000h until it matches the register value again , and the correct pwm waveform is not output. rewriting during period <2> (r ewriting during down counting) a match with the value of the 16-bit c ounter is ignored during counting down . therefore, the rewritten period value is reflected starting from counting up in the next cycle as a match point.
chapter 10 motor control function user?s manual u18279ej3v0ud 583 (b) rewriting tabnccrm register figure 10-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the tabnccrm register (<1> in figure 10-23), and figure 10-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of th e tabnccrm register (<2> in figure 10-23). figure 10-23. basic operation of 16-bit counter and tabnccrm register (a) basic figure 16-bit counter tabnccrm register <1> <2> <1> <2> <1> <2> <1> <2> i ii ii remarks 1. i = set value of tabnccrm register 2. n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 584 figure 10-24. example of rewriting tabnccr1 to t abnccr3 registers (rewriting before match occurs) (a) if the tabnccrm register is rewritten before its value ma tches the value of the 16-bit counter, the register value will match the value of the 16-b it counter after the register has been rewritten. consequently, the new register value is immediately reflected. 16-bit counter ccrm buffer register tabnccrm register tobntm pin output i k k i k k ik (b) if a value less than the value of the 16-bit counter (great er if the counter is counting down) is written to the tabnccrm register, the output waveform is as follows because the register value do es not match the counter value. i i r r r r ir 16-bit counter ccrm buffer register tabnccrm register tobntm pin output if the register value does not match the counter value, the tobntm pin output does not change. even if the value of the 16-bit counter does not match the value of the tabnccrm register, the tobntm pin output always changes to the high level if the crest interrupt occurs and to the low level if the valley interrupt occurs. this is a function provided for 0% output and 100% output. for details, see 10.4.2 (2) pwm output of 0%/100% . remarks 1. i, r, k = set values of tabnccrm register 2. n = 0, 1, m = 1 to 3
chapter 10 motor control function user?s manual u18279ej3v0ud 585 figure 10-25. example of rewriting tabnccr1 to tabnccr3 registers (rewriting after match occurs) ccrm buffer register 16-bit counter tabnccrm register inttbnccm signal tobntm pin output i k k i i k k ik <1> <3> <2> <1> matching of the count value of the 16-bit counter and the value of t he tabnccrm register as a result of rewriting the register is ignored after a match signal has been generated, and the pwm output does not change. <2> even if the pwm output does not change, the interrupt generated upon a match between the 16-bit counter value and the tabnccrm regi ster value (inttbnccm) is output. <3> the next match between the 16-bit counter and tabnccrm register is valid after the counter has changed its counting direction to up or down, and the pwm output changes. if the tabnccrm register is rewritten after its value matc hes the value of the 16-bit counter, the next match is ignored after the first match occurs and the rewritten va lue is not reflected to the tobntm pin output. if the register is rewritten while the counter is counting down, the match that occurs after the counter starts counting down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten while the counter is counting up). remarks 1. i, r, k = set value of tabnccrm register 2. n = 0, 1, m = 1 to 3 (c) rewriting tabnopt1 register the interrupt culling counter is cleared when the tabnopt1 register is written. when the interrupt culling counter has been cleared, the measur ed number of times the interrupt has occurred is discarded. consequently, the interrupt generation interval is temporarily extended. to avoid this operation, rewrite the tabnopt1 regist er in the intermittent bat ch rewriting mode (transfer culling mode). for details of rewriting the tabnopt1 register, see 10.4.3 interrupt culling function .
chapter 10 motor control function user?s manual u18279ej3v0ud 586 (2) batch rewrite mode (transfer mode) this mode is specified by setting the tabnopt0 .tabncms bit to 0, the tabnopt1.tabnid4 to tabnopt1.tabnid0 bits to 00000, and the tabnopt2.tabnrde bit to 0. in this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the count value. (a) rewriting procedure if data is written to the tabnccr1 register, the val ues set to the tabnccr0 to tabnccr3, tabnopt1, taanccr0, and taanccr1 registers are transferred all at once to the internal buffer register at the next transfer timing. therefore, write to the tabnccr1 regist er last. writing to the register is prohibited after the tabnccr1 register has been written and before the transfer timing is generated (until the crest (match between the 16-bit counter value and tabnccr0 regist er value) or the valley (match between the 16-bit counter value and 0001h)). the op eration procedure is as follows. <1> rewriting the tabnccr0, tabnccr2, tabnccr3, tabnopt1, taanccr0, and taanccr1 registers. do not rewrite registers that do not have to be rewritten. <2> rewriting the tabnccr1 register. rewrite the same value to the register even when it is not necessary to rewrite the tabnccr1 register. <3> holding the next rewriting pending until the transfer timing is generated. rewrite the register next time after the in ttbnov or inttbncc0 in terrupt has occurred. <4> return to <1>.
chapter 10 motor control function user?s manual u18279ej3v0ud 587 figure 10-26. basic operation in batch mode inttbnov signal inttbncc0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tabnccr2 register tabnccr3 register tabnopt1 register 16-bit counter (tabn) transfer timing tabnccr0 register tabnccr1 register ccr0 buffer register ccr1 buffer register & 16-bit counter (taan) transfer timing taanccr0 register taanccr1 register ccr0 buffer register ccr1 buffer register [operation of tabn] write the tabnccr1 register the target timing is the first transfer timing after a write to the tabnccr1 register. the values are transferred all at once at the transfer timing. [operation of taan] write the tabnccr1 register the target timing is the first transfer timing after a write to the tabnccr1 register. the values are transferred all at once at the transfer timing.
chapter 10 motor control function user?s manual u18279ej3v0ud 588 (b) rewriting tabnccr0 register when rewriting the tabnccr0 register in the batch re write mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and tabnccr0 register value) or at the valley (match between the 16-bit counter value and 0001h). usually, it is recommended to rewrite the tabnccr0 register while the 16-bit counter is counting down, and transfer the register value at the transfer timing of the crest timing. figure 10-28 shows an example of rewriting the tabnccr0 register while the 16-bit counter is counting up (during period <1> in figure 10-27). figure 10-29 sh ows an example of rewriting the tabnccr0 register while the counter is counting down (during period <2> in figure 10-27). figure 10-27. basic operation of 16-bit counter <1> <2> <1> <2> 16-bit counter the transfer timing in figure 10-28 is at the point wher e the crest timing occurs. while the 16-bit counter is counting down, the cycle changes and an asymmetrical triangular wave is output. because the cycle changes, rewrite the duty factor (voltage data value).
chapter 10 motor control function user?s manual u18279ej3v0ud 589 figure 10-28. example of rewriting t abnccr0 register (dur ing up counting) (a) m > n 16-bit counter transfer timing ccr0 buffer register tabnccr0 register tabnccr1 register ccr1 buffer register tobnt1 pin output inttbncc0 signal inttbnov signal kk k k i k k n + 1 n + 1 n n m m 0000h 0000h m i i k k (b) m < n 16-bit counter transfer timing ccr0 buffer register tabnccr0 register tabnccr1 register ccr1 buffer register tobnt1 pin output inttbncc0 signal inttbnov signal kk i n + 1 n + 1 n n m m 0000h 0000h m i i k k remarks 1. if transfer (match between the value of the 16- bit counter and the value of the ccr0 buffer register) occurs in the 6-phase pwm output mode, the value of t he tabnccr0 register plus 1 is loaded to the 16-bit counter. in this way, t he expected wave can be output even if the cycle value is changed at the transfer timing of the cres t (match between the 16-bit counter value and the tabnccr0 register value) timing. 2. m: value of ccr0 buffer register before rewriting n: value of ccr0 buffer register after rewriting
chapter 10 motor control function user?s manual u18279ej3v0ud 590 figure 10-29. example of rewriting tabn ccr0 register (duri ng down counting) 16-bit counter transfer timing tabnccr0 register tabnccr1 register ccr1 buffer register ccr0 buffer register tobnt1 pin output inttbncc0 signal inttbnov signal k kk k ii n n m m + 1 n + 1 0000h 0000h m i i k k because the next transfer timing is at the point of the valley (match between the 16-bit counter value and 0001h), the cycle value changes from the next cycle and output of a symmetrical triangular wave is maintained. because the cycle changes, rewrite the duty value (voltage data value) as required.
chapter 10 motor control function user?s manual u18279ej3v0ud 591 (c) rewriting tabnccrm register figure 10-30. example of rewriting tabnccrm register transfer timing tabnccrm register 16-bit counter ccrm buffer register tobntm pin output inttbnccm signal k k k i i rr r r i 0000h <1> <2> <1> <2> rewriting during period <1> (rewriting during counting up) because the tabnccrm register value is transferred at the transfer timing of the crest (match between the 16-bit counter value and tabnccr0 register value), an asymmetrical triangular wave is output. rewriting during period <2> (rewriting during counting down) because the tabnccrm register value is transferred at the transfer timing of the valley (match between the 16-bit counter value and 0001h), a symmetrical triangular wave is output. remark m = 1 to 3 (d) transferring tabnopt1 register value do not set the tabnopt1.tabnid4 to tabnopt1.tabnid0 bits to other than 00000. when using the interrupt culling function, rewrite the tabnopt1 regist er in the intermittent bat ch rewrite mode (transfer culling mode). for details of rewriting the tabnopt1 register, see 10.4.3 interrupt culling function .
chapter 10 motor control function user?s manual u18279ej3v0ud 592 (3) intermittent batch rewriti ng mode (transfer culling mode) this mode is specified by setting the tabnopt0.tabncms bit is 0 and the tabnopt2.tabnrde bit is 1. in this mode, the values written to each compare register are transferred to the internal buffer register all at once at the culled transfer timing and compared with the count value. the transfer timing is the timing at which an interr upt is generated (inttbncc0, inttbnov) by interrupt culling. for details of the interrupt culling function, see 10.4.3 interrupt culling function . (a) rewriting procedure if data is written to the tabnccr1 register, the tabnccr0 to tabnccr3, tabnopt1, taanccr0, and taanccr1 registers are transferred all at once to the inte rnal buffer register at the next transfer timing. therefore, write to the tabnccr1 register last. writ ing to the register is prohibited after the tabnccr1 register has been written until the transfer ti ming is generated (until the inttbnov or inttbncc0 interrupt occurs). the operation procedure is as follows. <1> rewrite the tabnccr0, tabnccr2, tabnccr3, tabnopt1, taanccr0, and taanccr1 registers. do not rewrite registers that do not have to be rewritten. <2> rewrite the tabnccr1 register. rewrite the same value to the register even when it is not necessary to rewrite the tabnccr1 register. <3> hold the next rewriting pending until the transfer timing is generated. perform the next rewrite after the inttbnov or inttbncc0 interrupt has occurred. <4> return to <1>.
chapter 10 motor control function user?s manual u18279ej3v0ud 593 figure 10-31. basic operation in intermittent batch rewriting mode inttbnov signal inttbncc0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tabnccr2 register tabnccr3 register tabnopt1 register 16-bit counter (tabn) transfer timing tabnccr0 register tabnccr1 register ccr0 buffer register ccr1 buffer register & 16-bit counter (taan) transfer timing taanccr0 register taanccr1 register ccr0 buffer register ccr1 buffer register [tabn operation] write the tabnccr1 register. rewrite the register at t he transfer timing that is generated after the tabnccr1 register has been rewritten. the registers are transferred all at once at the transfer timing. the transfer timing is also culled as the interrupts are culled. [taan operation] write the tabnccr1 register. rewrite the register at the transfer timing t hat is generated after the tabnccr1 register has been rewritten. the registers are transferred all at once at the transfer timing. the transfer timing is also culled as the interrupts are culled. remark this is an example of the operation when the tabnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001.
chapter 10 motor control function user?s manual u18279ej3v0ud 594 (b) rewriting tabnccr0 register when rewriting the tabnccr0 register in the inte rmittent batch mode, the output waveform differs depending on where the occurrence of the crest or valle y interrupt is specified by the interrupt culling setting. the following figure illustrates the change of the output waveform when interrupts are culled. figure 10-32. rewriting tabnccr0 regi ster (when crest interrupt is set) 16-bit counter transfer timing tabnccr0 register tabnccr1 register ccr0 buffer register ccr1 buffer register inttbncc0 signal tobnt1 pin output inttbnov signal i l i m m 0000h 0000h m n n k k k k kk n + 1 i i i the transfer timing is generated when the crest interr upt occurs, the period of up counting and down counting changes, and an asymmetrical triangular wave is output. remarks 1. this is an example of the operation when the tabnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 0, tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001. 2. : culled interrupt 3. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 595 figure 10-33. rewriting tabnccr0 regi ster (when valley interrupt is set) i l i i m 0000h 0000h m n n k k kk m + 1 m + 1 n + 1 i i i 16-bit counter transfer timing tabnccr0 register tabnccr1 register ccr0 buffer register ccr1 buffer register inttbncc0 signal tobnt1 pin output inttbnov signal the transfer timing is generated when the valley interr upt occurs, the cycle of up counting and down counting becomes identical, and a symmetrical triangular wave is output. remarks 1. this is an example of the operation when the tabnopt1.tabnice bit = 0, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnopt1.tabnid0 bits = 00001. 2. : culled interrupt 3. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 596 (c) rewriting tabnccr1 to tabnccr3 registers ? transfer at crest when crest interrupt is set because the register is transferred at the transfer ti ming of the crest interrupt, an asymmetrical triangular wave is output. figure 10-34. rewriting tabnccr1 register (tabnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 0, tabnopt1.tabnid4 to tabnopt1.tabnid0 = 00001) 16-bit counter transfer timing tabnccr1 register ccr1 buffer register tobnt1 pin output i i i r ik transfer at crest interrupt k k i inttbncc0 signal inttbnov signal remarks 1. : culled interrupt 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 597 ? transfer at valley when valley interrupt is set because the register is transferred at the transfer timi ng of the valley interrupt, a symmetrical triangular wave is output. figure 10-35. rewriting tabnccr1 register (tabnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnopt1.tabnid0 = 00001) 16-bit counter transfer timing tabnccr1 register ccr1 buffer register tobnt1 pin output i i r ik transfer at valley interrupt transfer at valley interrupt r k k k i inttbncc0 signal inttbnov signal remarks 1. : culled interrupt 2. n = 0, 1 (d) rewriting tabnopt1 register because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval. for details of rewriting the tabnopt1 register, see 10.4.3 interrupt culling function .
chapter 10 motor control function user?s manual u18279ej3v0ud 598 (4) rewriting tabnopt0.tabncms bit the tabncms bit can select the anytime rewrite mode and batch rewrite mode. this bit can be rewritten during timer operation (when tabnctl0.tabnce bit = 1) . however, the operation and caution illustrated in figure 10-36 are necessary. if the tabnccr1 register is written when the tabncms bit is set to 0, a transfer request signal (internal signal) is set. when the transfer request signal is set, the register is tr ansferred at the next transfer timing, and the transfer request signal is cleared. this transfer request signal is also cleared when the tabncms bit is set to 1. figure 10-36. rewriting tabncms bit <1> <2> <3> <4> <5> <6> 0000h clear clear ir rs s k i 16-bit counter transfer request signal transfer timing tabnccr1 register ccr1 buffer register write signal of tabnccr1 tabncms bit <1> if the tabnccr1 register is rewritten when the tabncms bit is 0, the transfer request signal is set. if the tabncms bit is set to 1 in this st atus, the transfer request signal is cleared. <2> the register is not transferred because the tabncm s bit is set to 1 and the transfer request signal is cleared. <3> the transfer request signal is not set even if the t abnccr1 register is written when the tabncms bit is 1. <4> the transfer request signal is not set even if the t abnccr1 register is written when the tabncms bit is 1, so even if the tabncms bit is set to 0, transfe r does not occur at the subsequent transfer timing. <5> the transfer request signal is set if the tabnccr1 register is written when the tabncms bit is 0. transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> once transfer has been performed, the transfer re quest signal is cleared. therefore, transfer is not performed at the next transfer timing. remark n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 599 10.4.5 taan tuning operation for a/d c onversion start trigger signal output this section explains the tuning operation of taan and tabn in the 6-phase pwm output mode. in the 6-phase pwm output mode, the t uning operation is performed with tabn serving as the master and taan as a slave. the conversion start trigger signal of a/d converte rs 0 and 1 can be set as the a/d conversion start trigger source by the inttancc0 and inttancc1 signals of taan and the inttbnov and inttbncc0 signals of tabn. remark n = 0, 1 (1) tuning operation starting procedure the taan and tabn registers should be set using the following procedure to perform the tuning operation. (a) setting of taan register (stop the operations of tabn and taan (by setting the tabnctl0.tabnce bit and taanctl0.taance bit to 0)) ? set the taanctl1 register to 85h (set the tuni ng operation slave mode and free-running timer mode). ? set the taanopt0 register to 00h (select the compare register). ? set an appropriate value to the taanccr0 and ta anccr1 registers (set the default value for comparison for starting the operation). (b) setting of tabn register ? set the tabnctl1 register to 07h (set t he master mode and 6-phase pwm output mode). ? set an appropriate value to the tabnioc0 register (set the output mode of tobnt1 to tobnt3). however, set the tabnol0 bit to 0 and the tabnoe0 bit to 1 (enable positive phase output). unless this setting is made, the crest interrupt (inttbncc0 ) and valley interrupt (inttbnov) do not occur. consequently, the conversion start trigger signal of a/d converters 0 and 1 is not correctly generated. ? clear the tabnioc1 and tabnioc2 registers to 00h (the tibn0 to tibn3, evtbn, and trgbn pins of tabn are not used). ? clear the tabnopt0 register to 00h (select the compare register). ? set an appropriate value to the tabnccr0 to tabnccr3 registers (set the default value for comparison for starting the operation). ? set the tabnctl0 register to 0xh (set the tabn ce bit to 0 and the operating clock of tabn). the operating clock of tabn set by the tabnctl0 register is also supplied to taan, and the count operation is performed at the same timing. the oper ating clock of taan set by the taanctl0 register is ignored. (c) setting of tmqopn (tmqn option) register ? set an appropriate value to the tabnopt1 and tabnopt2 registers. ? set an appropriate value to the tabnioc3 register (set tobnb1 to tobnb3 in the output mode). ? set an appropriate value to the tabndtc register (s et the default value for comparison for starting the operation). (d) setting of alternate function ? select the alternate function of the port by setting the port to the port control mode.
chapter 10 motor control function user?s manual u18279ej3v0ud 600 (e) set the taance bit to 1 and set the tabnce bit to 1 immediately after that to start the 6-phase pwm output operation. rewriting the tabnctl0, tabnctl1, tabnioc1, t abnioc2, taanctl0, and taanctl1 registers is prohibited during operation. the operation and the pw m output waveform are not guaranteed if any of these registers is rewritten during operation. however, rewriting the tabnctl0.tabnce bit to clear it is permitted. manipulating (reading/writing) the other tabn, taan, and tmqn option registers is prohibited until the taanctl0.taance bit is set to 1 and then the tabnce bit is set to 1. (2) tuning operation clearing procedure to clear the tuning operation and exit the 6-phase pwm out put mode, set the taan and tabn registers using the following procedure. <1> clear the tabnctl0.tabnce bit to 0 and stop the timer operation. <2> clear the taanctl0.taance bit to 0 so that taan can be separated. <3> stop the timer output by using the tabnioc0 register. <4> clear the taanctl1.taansye bit to 0 to clear the tuning operation. caution manipulating (reading/writing) the other t abn, taan, and tmqn option registers is prohibited until the tabnce bit is set to 0 and then the taance bi t is set to 0. (3) when not tuning taan when the match interrupt signal of taan is not necessary as the conversion trigger source that starts a/d converters 0 and 1, taan can be used independently as a separate timer without being tuned. in this case, the match interrupt signal of taan cannot be used as a trig ger source to start a/d conversion in the 6-phase pwm output mode. therefore, fix the tabnopt2.tabn at2, tabnopt2.tabnat3, tabnopt3.tabnat6, and tabnopt3.tabnat7 bits to 0. the other control bits can be used in t he same manner as when taan is tuned. if taan is not tuned, the compare registers (taanccr0 and taanccr1) of taan are not affected by the settings of the tabnopt0.tabncms and tabnopt2.tabn rde bits. for the initialization procedure when taan is not tuned, see (b) to (e) in 10.4.5 (1) tuning operation starting procedure . (a) is not necessary because it is a step used to set taan for the tuning operation. (4) basic operation of taan during tuning operation the 16-bit counter of taan only counts up. the 16-bi t counter is cleared by the set cycle value of the tabnccr0 register and starts counting from 0000h again. the count value of this counter is the same as the value of the 16-bit counter of taan wh en it counts up. however, it is not the same when the 16-bit counter of tabn counts down. ? when tabn counts up (same value) 16-bit counter of tabn: 0000h m (up counting) 16-bit counter of taan: 0000h m (up counting) ? when tabn counts down (not same value) 16-bit counter of tabn: m + 1 0001h (down counting) 16-bit counter of taan: 0000h m (up counting)
chapter 10 motor control function user?s manual u18279ej3v0ud 601 figure 10-37. taan during tuning operation r s r s r s r s 16-bit counter of tabn 16-bit counter of taan m (carrier data) tabnccr0 register tobnt1 pin output (u) tobnb1 pin output (u) tabnccr1 register taanccr0 register taanccr1 register inttancc0 signal inttancc1 signal tabnccr2 register tabnccr3 register i (phase u data) s (a/d conversion start trigger timing 2) r (a/d conversion start trigger timing 3) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 tobnt2 pin output (v) tobnb2 pin output (v) tobnt3 pin output (w) tabtadtna signal tobnb3 pin output (w) note note m m m note the tabtadtn0 signal is masked by the tabnopt2.tabnatm2 and tabnopt2.tabnatm3 bits. the tabtadtn1 signal is masked by the tabn opt3.tabnatm6 and tabnopt3.tabnatm7 bits. remark n = 0, 1 a = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 602 10.4.6 a/d conversion start trigger output function the v850e/if3 and v8 50e/ig3 have a function to select four trigger sources (inttbnov, inttbncc0, inttancc0, inttancc1) to generate the a/d conversion start trigger signal (tabtadtn0, tabtadtn1) of a/d converters 0 and 1. the trigger sources are specified by the tabnopt2.t abnat0 to tabnopt2.tabnat3 and tabnopt3.tabnat4 to tabnopt3.tabnat7 bits. ? tabnat0, tabnat4 bits = 1: a/d conversion start trigger signal generated when inttbnov (counter underflow) occurs. ? tabnat1, tabnat5 bits = 1: a/d conversion start trigger signal gener ated when inttbncc0 (cycle match) occurs. ? tabnat2, tabnat6 bits = 1: a/d conversion start trigger signal generated when inttancc0 (match of taanccr0 register of taan during tuning operation) occurs. ? tabnat3, tabnat7 bits = 1: a/d conversion start trigger signal generated when inttancc1 (match of taanccr1 register of taan during tuning operation) occurs. the a/d conversion start trigger signals selected by the tabnat0 to tabnat3 and tabnat4 to tabnat7 bits are ored and output. therefore, two or more trig ger sources can be specified at the same time. the inttbnov and inttbncc0 signals selected by the tabnat0, tabnat1, tabnat4, and tabnat5 bits are culled interrupt signals. therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (tabnopt1.tabnice, tabnopt1.tabnioe bits), the a/d conversion start trigger is not output. the trigger sources (inttancc0 and inttancc1) from taan have a function to mask the a/d conversion start trigger signal depending on the status of the up-count/dow n-count of the 16-bit counter, if so set by the tabnat2, tabnat3, tabnat6, and tabnat7 bits. ? tabnatm2, tabnatm6 bits: correspond to the tabnat2 and tabnat6 bits and c ontrol inttancc0 (match interrupt signal) of taan. ? tabnatm2, tabnatm6 bits = 0 the a/d conversion start trigger signal is output wh en the 16-bit counter counts up (tabnopt0.tabncuf bit = 0), and the a/d conversion start trigger signal is not output when the 16-bit counter counts down (tabnopt0.tabncuf bit = 1). ? tabnatm2, tabnatm6 bits = 1 the a/d conversion start trigger signal is output when the 16-bit counter counts down (tabnopt0.tabncuf bit = 1), and the a/d conversion start trigger sig nal is not output when the 16-bit counter counts up (tabnopt0.tabncuf bit = 0). ? tabnatm3, tabnatm7 bits: correspond to the tabnat3 and tabnat7 bits and c ontrol inttancc1 (match interrupt signal) of taan. ? tabnatm3, tabnatm7 bits = 0 the a/d conversion start trigger signal is output wh en the 16-bit counter counts up (tabncuf bit = 0), and the a/d conversion start trigger signal is not output when the 16-bit counter counts down (tabncuf bit = 1). ? tabnatm3, tabnatm7 bits = 1 the a/d conversion start trigger signal is output when the 16-bit counter counts down (tabncuf bit = 1), and the a/d conversion start trigger signal is not output when the 16-bit counter counts up (tabncuf bit = 0).
chapter 10 motor control function user?s manual u18279ej3v0ud 603 the tabnatm3, tabnatm2, tabnat3 to tabnat0, tabnat m7, tabnatm6, and tabnat7 to tabnat4 bits can be rewritten while the timer is operating. if the bit that sets the a/d conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected on the output status of the a/d conversion start trigger. these control bits do not have a transfer function an d can be used only in the anytime rewriting mode. cautions 1. the a/d conversion start trigger signal out put that is set by the tabnat2, tabnat3, tabnat6, and tabnat7 bits can be used only when taan is performing a tuning operation as the slave timer of tabn. if tabn and taan are not perf orming a tuning operation, or if a mode other than the 6-phase pwm output mode is u sed, the output cannot be guaranteed. 2. the tobn0 signal output is internally used to identify whether the 16 -bit counter is counting up or down. therefore, enable tobn0 pin out put by setting the tabnioc0.tabnol0 bit to 0 and the tabnioc0.tabnoe0 bit to 1.
chapter 10 motor control function user?s manual u18279ej3v0ud 604 figure 10-38. example of a/d conversion start trigge r (tabtadtn0) signal output (tabnopt1.tabnice bit = 1, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnop t1.tabnid0 bits = 00000: wi thout interrupt culling) 16 -bit counter inttbnov signal inttancc0 signal inttancc1 signal tabncuf bit tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabtadtn0 signal tabnat3 to tabnat0 bits = 0001 (inttbnov signal output) tabnat3 to tabnat0 bits = 0010 (inttbncc0 signal output) tabnat3 to tabnat0 bits = 0100, tabnatm2 bit = 0 (inttancc0 signal output during counting up) tabnat3 to tabnat0 bits = 0100, tabnatm2 bit = 1 (inttancc0 signal output during counting down) tabnat3 to tabnat0 bits = 1000, tabnatm3 bit = 1 (inttancc1 signal output during counting down) tabnat3 to tabnat0 bits = 0011 (setting to output a/d conversion start trigger signal when both crest and valley interrupts occur) tabnat3 to tabnat0 bits = 1100, tabnatm3 bit = 1, tabnatm2 bit = 0 (inttancc0 and inttancc1 signals ored for output. setting to output a/d conversion start trigger signal when match interrupt of taan occurs when counter is counting up or down) tabnat3 to tabnat0 bits = 1000, tabnatm3 bit = 0 (inttancc1 signal output during counting up) inttbncc0 signal remark n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 605 figure 10-39. example of a/d conversion start trigge r (tabtadtn0) signal output (tabnopt1.tabnice bit = 0, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnop t1.tabnid0 bits = 00010: with interrupt culling) (1) 16 -bit counter inttbnov signal tabtadtn0 signal tabnat3 to tabnat0 bits = 0011 (both inttbncc0 and inttbnov signals are selected but crest interrupt (inttbncc0) is not output because interrupt culling is specified.) inttbncc0 signal l remarks 1. : culled interrupt 2. n = 0, 1 figure 10-40. example of a/d conversion start trigge r (tabtadtn0) signal output (tabnopt1.tabnice bit = 0, tabnopt1.tabnioe bit = 1, tabnopt1.tabnid4 to tabnop t1.tabnid0 bits = 00010: with interrupt culling) (2) 16 -bit counter inttbnov signal tabtadtn0 signal tabnat3 to tabnat0 bits = 0101, tabnatm2 bit = 1 tabncuf bit inttancc1 signal inttancc0 signal inttbncc0 signal l caution the inttbncc0 si gnal is culled but the inttancc0 signal is not. remarks 1. : culled interrupt 2. n = 0, 1
chapter 10 motor control function user?s manual u18279ej3v0ud 606 (1) operation under boundary condition (operation when 16-bit counter matches inttancc0 signal) table 10-3. operation when tabnccr0 register = m, t abnat2 bit = 1, tabnat6 bit = 1, tabnatm2 bit = 0, tabnatm6 bit = 0 (up counting period selected) value of taanccr0 register value of 16-bit counter of tabn value of 16-bit counter of taan status of 16-bit counter of tabn output of inttancc0 signal from tabtadtna signal 0000h 0000h 0000h ? output 0000h m + 1 0000h ? not output 0001h 0001h 0001h up count output 0001h m 0001h down count not output m m m up count output m 0001h m down count not output table 10-4. operation when tabnccr0 register = m, t abnat2 bit = 1, tabnat6 bit = 1, tabnatm2 bit = 1, tabnatm6 bit = 1 (down counting period selected) value of taanccr0 register value of 16-bit counter of tabn value of 16-bit counter of taan status of 16-bit counter of tabn output of inttancc0 signal from tabtadtna signal 0000h 0000h 0000h ? not output 0000h m + 1 0000h ? output 0001h 0001h 0001h up count not output 0001h m 0001h down count output m m m up count not output m 0001h m down count output caution the taanccra register enables setting of ?0 ? to ?m? when the tabnccr0 register = m. setting of a value of ?m + 1? or higher is prohibited. if a value higher than ?m + 1? is set, the 16-bit counter of taan is cleared by ?m?. therefore, the tabtadtna signal is not output. remark n = 0, 1 a = 0, 1
user?s manual u18279ej3v0ud 607 chapter 11 watchdog timer functions 11.1 functions the watchdog timer has the following functions. ? reset mode: reset operation upon overflow of the watchdog timer (generation of wdtres signal) ? non-maskable interrupt request mode: non-maskable interrupt operation upon overflow of the watchdog timer (generation of intwdt signal) caution the watchdog timer is st opped after reset is released. it starts operating when ?ach? is written to the wdte regist er. also, write to the wdtm register for verification purposes only once, even if the default settings (reset mode, interval time: 2 26 /f xx ) do not need to be changed. 11.2 configuration the block diagram of the watchdog timer is shown below. figure 11-1. block diag ram of watchdog timer f xx /2 10 output controller wdtres (internal reset signal) wdcs2 internal bus intwdt wdcs1 wdcs0 0 0 0 wdm1 wdm0 selector 16-bit counter f xx /2 19 to f xx /2 26 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 2 clear remark f xx /2 10 : watchdog timer clock f xx : peripheral clock intwdt: non-maskable interrupt request signal upon overflow of watchdog timer wdtres: reset signal upon overflow of watchdog timer the watchdog timer consists of the following hardware. table 11-1. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte)
chapter 11 watchdog timer functions user?s manual u18279ej3v0ud 608 11.3 control registers (1) watchdog timer mode register (wdtm) the wdtm register sets the overflow time and operation clock of the watchdog timer. this register can be read or written in 8-bit units. this register can be read any number of times, but can be written only once following reset release; it c annot then be written a second or subsequent time. reset sets this register to 67h. 0 wdtm wdm1 wdm0 0 0 wdcs2 wdcs1 wdcs0 after reset: 67h r/w address: fffff6d0h stop operation non-maskable interrupt request mode (generation of intwdt signal) reset mode (generation of wdtres signal) wdm1 0 0 1 wdm0 0 1 selection of operation mode of watchdog timer cautions 1. for details of the wdcs2 to wdcs0 bits, see table 11-2 overflow time. 2. if the wdtm register is rewritten while the watchdog timer is counting, the counter of the watchdog timer is cleared to 0000h. 3. be sure to clear bits 3, 4, and 7 to ?0?. table 11-2. overflow time wdcs2 wdcs1 wdcs0 overflow time f xx = 64 mhz f xx = 32 mhz 0 0 0 2 19 /f xx 8.2 ms 16.4 ms 0 0 1 2 20 /f xx 16.4 ms 32.8 ms 0 1 0 2 21 /f xx 32.8 ms 65.5 ms 0 1 1 2 22 /f xx 65.5 ms 131.1 ms 1 0 0 2 23 /f xx 131.1 ms 262.1 ms 1 0 1 2 24 /f xx 262.1 ms 524.3 ms 1 1 0 2 25 /f xx 524.3 ms 1,048.5 ms 1 1 1 2 26 /f xx 1,048.5 ms 2,097.1 ms
chapter 11 watchdog timer functions user?s manual u18279ej3v0ud 609 (2) watchdog timer enable register (wdte) the counter of the watchdog timer is cleared and counting restarted by writing ?ach? to the wdte register. this register can be read or written in 8-bit units. reset sets this register to 1ah. wdte after reset: 1ah r/w address: fffff6d1h cautions 1. if ?ach? is written to the wdte regi ster to enable the watchdog timer operation and then a value other than ?ach? is written to the wd te register, a non-maskable interrupt request signal (intwdt) or a reset signal (wdtres) is generated due to watchdog timer overflow, depending on the specification of the wdtm.wdm1 and wdtm.wdm0 bits. 2. when the wdte register is read or written in 1-bit units, an internal reset signal is output. 3. the read value of the wdte register is ?1ah? before the watc hdog timer operates, and ?9ah? after it operates. the value read from th is register is different from the written value (ach). 11.4 operation the watchdog timer is stopped after reset is released. the wdtm register can be written only once after reset is released. to use the watchdog timer, write the operat ion mode and the interval time to the wdtm register in 8-bit units. after this, the operation of the watchdog timer cannot be stopped. to not use the watchdog timer, write 00h to the wdtm register. 11.5 caution the cycle of the non-maskable interrupt request signal (int wdt) that is generated due to watchdog timer overflow can be calculated from ?interval time set to wdtm register + 2 7 peripheral clock pulse width?, if intwdt occurs successively without the watchdog timer being cleared. note that the pulse width until generat ion of the first interrupt request signal after the watchdog timer has been started is not included.
user?s manual u18279ej3v0ud 610 chapter 12 a/d converters 0 and 1 12.1 features ? two 12-bit resolution a/d converter circuits (a/d converters 0 and 1) simultaneous sampling of two circuits possible ? analog input ? when comparator is not used total of 10 channels in two circuits a/d converter 0: ani00/ani05, ani01 to ani04 (5 channels) a/d converter 1: ani10/ani15, ani11/ani16, ani12/ani17, ani13, ani14 (5 channels) ? when comparator is used total of 6/8 channels in two circuits [6 channels (when comparators of low-range and full-range are used)] a/d converter 0: ani00/ani05, ani01, ani02 (3 channels) a/d converter 1: ani10/ani15, ani 11/ani16, ani12/ani17 (3 channels) [8 channels (when comparator of low-range or full-range is used)] a/d converter 0: ani00/ani05, ani01, ani02, ani03 or ani04 (4 channels) a/d converter 1: ani10/ani15, ani11/ani16, ani12/ani17, ani13 or ani14 (4 channels) ? a/d conversion result registers 12 bits 16 + 12 bits 16 a/d converter 0: ad0cr0 to ad0cr15 a/d converter 1: ad1cr0 to ad1cr15 ? a/d conversion result extension registers can be used only in the extension buffer mode 12 bits 5 + 12 bits 5 a/d converter 0: ad0ecr0 to ad0ecr4 a/d converter 1: ad1ecr0 to ad1ecr4 ? operation modes ? normal operation modes a/d trigger mode a/d trigger polling mode hardware trigger mode ? extension operation modes conversion channel specification mode extension buffer mode ? operational amplifiers for input level amplification ( 2.5 to 10) these channels can be used only when the operational amplifier for input level amplification is used. total of 4 units in two circuits a/d converter 0: ani05 (1 unit) a/d converter 1: ani15 to ani17 (3 units)
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 611 ? overvoltage detection comparator ? these channels can be used only when the overvoltage detection comparator is used. ? total of 4 units in two circuits a/d converter 0: 1 unit a/d converter 1: 3 units ? reference voltage input voltage range from cref0l, cref1l pins (low-range side) = 0.02av dd + 0.1 to 0.5av dd ? 0.1 v input voltage range from cref0f, cre f1f pins (full-range side) = 0.02av dd + 0.1 to 0.92av dd ? 0.1 v ? an interrupt occurs when an overvoltage is detect ed. interrupt requests ar e output by two overvoltage detection signal pins ani00/ani05 (full-range side an d low-range side) and as the logical sum (or) of the overvoltage detection signals of three channels, ani10/ ani15, ani11/ani16, and an i12/ani17, or two output signals (full-range side and low-range side) of a logical product (and). ? the output of a timer for motor control can be set to a high-impedance state when an overvoltage is detected. ? successive approximation method ? operating voltage range ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av dd0 = av dd1 = av refp0 = av refp1 = 4.0 to 5.5 v
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 612 12.2 configuration the block diagram is shown below. figure 12-1. block diag ram of a/d converter 0 ani00/ani05 ani02 ani03/cref0l ani04/cref0f ani01 cmpref intcmp0l to high-impedance controller of timer output for motor control to high-impedance controller of timer output for motor control intcmp0f intad0 input circuit (see figure 12-3 ) internal bus selector ad0ctl0 ad0tsel ad0ch1 ad0ch2 ad0ctc tabtadt00 tabtadt01 trigger source selector in hardware trigger mode (see figure 12-6 ) adtrg0/intadt0 edge detection/ noise eliminator f xx /3 f xx /4 f ad01 f xx /2 ad0scm0 ad0chen buffer register 0 buffer register 1 buffer register 2 buffer register 3 buffer register 4 ad0ecr0 ad0ecr1 ad0ecr2 ad0ecr3 ad0ecr4 ad0cr0 ad0cr1 ad0cr2 ad0cr3 ad0cr5 : ad0cr15 ad0cr4 tabtadt10 controller av refp0 av ss0 sample & hold circuit voltage comparator array av dd0 selector selector successive approximation register (sar) remark f xx : peripheral clock f ad01 : basic clock buffer registers 0 to 4: a/d0 conversion result extension buffer registers 0 to 4
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 613 figure 12-2. block diag ram of a/d converter 1 ani10/ani15 ani12/ani17 ani13/cref1l ani14/cref1f ani11/ani16 cmpref intad1 input circuit (see figure 12-4 ) internal bus successive approximation register (sar) ad1ctl0 ad1tsel ad1ch1 ad1ch2 ad1ctc tabtadt10 tabtadt11 trigger source selector in hardware trigger mode (see figure 12-6 ) adtrg1/intadt1 edge detection/ noise eliminator f xx /3 f xx /4 f xx /2 f ad01 ad1scm0 ad1chen ad1cr0 ad1cr1 ad1cr2 ad1cr3 ad1cr5 : ad1cr15 ad1cr4 tabtadt01 controller intcmp1l to high-impedance controller of timer output for motor control to high-impedance controller of timer output for motor control intcmp1f av refp1 av ss1 sample & hold circuit voltage comparator array av dd1 buffer register 0 buffer register 1 buffer register 2 buffer register 3 buffer register 4 ad1ecr0 ad1ecr1 ad1ecr2 ad1ecr3 ad1ecr4 selector selector selector remark f xx : peripheral clock f ad01 : basic clock buffer registers 0 to 4: a/d1 conversion result extension buffer registers 0 to 4 cautions 1. if there is noise at the analog input pins (ani00 to ani05, ani10 to ani17) or at the a/d converter reference voltage input pins (av refp0 , av refp1 ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions con secutively and use tho se results, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judg ed to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 2. do not apply a voltage outside the av ssn to av refpn range to the pins that are used as input pins of a/d converters 0 and 1 (n = 0, 1).
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 614 figure 12-3. block diagram of operational amplifier for input level amplification and overvoltag e detection comparator in a/d converter 0 operational amplifier 0 comparator 0 through mode full range low range amplification mode before amplification after amplification cmp0fen bit ? + cmp0len bit + ? ani00/ani05 op0en bit + ? ani01 ani02 cmp0ctl3 note intcmp0f noise elimination to high-impedance controller of timer output for motor control full-range programmable digital filter edge detector intcmp0l noise elimination to high-impedance controller of timer output for motor control low-range programmable digital filter edge detector a/d converter 0 ani03/cref0l ani04/cref0f cmp0nfen bit cmp0nfen bit selector selector selector selector note for details, see figure 12-5 cmpnctl3 register selector circuit configuration .
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 615 figure 12-4. block diagram of op erational amplifier for input l evel amplification and overvoltag e detection comparator in a/d converter 1 cmp1ctl3 note operational amplifier 0 comparator 0 through mode full range low range amplification mode before amplification after amplification cmp10fen bit ? + cmp10len bit + ? ani10/ani15 op10en bit + ? operational amplifier 1 comparator 1 through mode full range low range amplification mode before amplification after amplification cmp11fen bit ? + cmp11len bit + ? ani11/ani16 op11en bit + ? operational amplifier 2 comparator 2 through mode full range low range amplification mode before amplification after amplification cmp12fen bit ? + cmp12len bit + ? ani12/ani17 op12en bit + ? ani13/cref1l ani14/cref1f intcmp1f noise elimination to high-impedance controller of timer output for motor control full-range programmable digital filter edge detector intcmp1l noise elimination to high-impedance controller of timer output for motor control low-range programmable digital filter edge detector a/d converter 1 cmp1nfen bit cmp1nfen bit selector selector selector selector note for details, see figure 12-5 cmpnctl3 register selector circuit configuration .
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 616 figure 12-5. cmpnctl3 register selector circuit configuration cmp12fen bit ani12 time voltage voltage voltage voltage ani11 ani10 cref1f (reference voltage) ani12 cmpnfds bit 1 0 1 0 selector cmpmfen bit cmpmfde bit cmp12fde bit intcmpnf cmp11fde bit cmpmfde bit cmp11fde bit cmp12fde bit or (detected when the input falls below the reference value) anin0 cmp11fen bit ani11 and (detected when the input exceeds the reference value) cmp1fds bit = 0 (and detection) cmp12fde to cmp10fde bits = 111 (edge detection enabled) (a) full range side (c) operation example (for the full range side of a/d converter 1) intcmp1f use the cmpor or cmpof register to specify any detection edge setting. time cmp12len bit ani12 time ani11 ani10 cref1f (reference voltage) ani12 cmpnlds bit cmpmlen bit cmpmlde bit cmp12lde bit intcmpnl cmp11lde bit cmpmlde bit cmp11lde bit cmp12lde bit or (detected when the input falls below the reference value) anin0 + _ cmp11len bit ani11 and (detected when the input exceeds the reference value) (b) low range side intcmp1f use the cmpor or cmpof register to specify any detection edge setting. time selector cmp1fds bit = 1 (or detection) cmp12fde to cmp10fde bits = 111 (edge detection enabled) + _ + _ + _ + _ + _ crefnf crefnl remarks 1. n = 0, 1 m = 0 when n = 0 m = 10 when n = 1 2. details about the noise eliminator have been omitted from the description.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 617 figure 12-6. block diagram of trigger s ource selector in hardware trigger mode p16/tob0off/intp08/ adtrg0/intadt0/a6 note a/d converter 0 edge detection/ noise eliminator tabtadt00 tabticc00 ldtrg1 itrg1 itrg2 ldtrg2 timer (tab0 + tmqop0 + taa0) p26/tob10/tob1off/intp10/ adtrg1/intadt1 a/d converter 1 edge detection/ noise eliminator itrg1 tabtadt01 tabtiov0 tabtadt10 tabticc10 timer (tab1 + tmqop1 + taa1) tabtadt11 tabtiov1 itrg3 itrg4 ldtrg1 itrg2 ldtrg2 itrg3 itrg4 selector selector note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 618 a/d converters 0 and 1 consis t of the following hardware. table 12-1. configuration of a/d converters 0 and 1 item configuration analog input when comparator is not used: ani00/ani05, ani01 to ani04, ani10/ani15 to ani12/ani17, ani13, ani14 (total of 10 channels in two circuits) when comparator is used (when comparators of low-range and full-range are used): ani00/ani05, ani01, ani02, ani10/ani15 to ani12/ani17 (total of 6 channels in two circuits) when comparator is used (when comparator of low-range or full-range is used): ani00/ani05, ani01, ani02, ani03 or ani04, ani10/ani15 to ani12/ani17, ani13 or ani14 (total of 8 channels in two circuits) registers successive appro ximation register (sar) a/dn conversion result registers 0 to 15 (adncr0 to adncr15) a/dn conversion result registers 0h to 15h (adncr0h to adncr15h) a/dn conversion result extension regi sters 0 to 4 (adnecr0 to adnecr4) (only in extension operation mode (extension buffer mode)) a/dn conversion result extension register s 0h to 4h (adnecr0h to adnecr4h) (only in extension operation mode (extension buffer mode)) control registers a/d converter n scan mode register (adnscm) a/d converter n scan mode register l (adnscml) a/d converter n scan mode register h (adnscmh) a/d converter n conversion time control register (adnctc) a/d converter n conversion channel specification register (adnchen) a/d converter n conversion channel sp ecification register l (adnchenl) a/d converter n conversion channel sp ecification register h (adnchenh) a/d converter n control register (adnctl0) a/d converter n trigger select register (adntsel) a/d converter n channel specification register 1 (adnch1) a/d converter n channel specification register 2 (adnch2) a/d converter n flag register (adnflg) a/d converter n flag buffer register (adnflgb) a/dldtrg1 input select register (adlts1) a/dldtrg2 input select register (adlts2) a/d converter n clock select register (adnocks) a/d trigger falling edge specification register (adtf) a/d trigger rising edge specification register (adtr) operational amplifier n control register 0 (opnctl0) comparator n control register 0 (cmpnctl0) comparator n control register 1 (cmpnctl1) comparator n control register 2 (cmpnctl2) comparator n control register 3 (cmpnctl3) comparator output digital noise e limination register nl (cmpnfcnl) comparator output digital noise elim ination register nf (cmpnfcnf) comparator output interrupt rising edge specification register (cmpor) comparator output interrupt falling edge specification register (cmpof) remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 619 (1) selector the selector selects the analog input pin according to the mode set by the adnscm, adnctc, adnchen, adnctl0, adntsel, adnch1, adnch2, adlts1, adlts2, and adnocks registers and sends the input to the sample & hold circuit (n = 0, 1). ani05, ani15 to ani17 are provid ed with an operational amplifier fo r input level amplification and an overvoltage detection comparator. the operational amp lifier and comparator of each analog input pin can be specified to be on or off. the amplific ation (gain) of the oper ational amplifier can be selected from 2.5 to 10 times for ani05, ani15 to ani17. (2) sample & hold circuit the sample & hold circuit samples each of the analog in put voltages sequentially sent from the input circuit, and sends them to the voltage comparat or. when the operational amplifier fo r input level amplification is used, the gain specified by the opnctl0 .opnga3 to opnctl0.opnga0 bits the input voltage is sampled. this circuit also holds the sampled analog input voltage during a/d conversion. (3) voltage comparator this comparator compares the volt age generated from the voltage tap of the array with the analog input voltage. if the analog input vo ltage is found to be greater t han the reference voltage (1/2 av refpn ) as a result of the comparison, the most significant bit (msb) of the successive approximation register (sar) is set. if the analog input voltage is less than the reference voltage (1/2 av refpn ), the msb of the sar is reset. after that, bit 10 of the sar is automatically set, and the next comparison is made. the voltage tap of the array is selected by the value of bit 11, to which the result has been already set. bit 11 = 0: (1/4 av refpn ) bit 11 = 1: (3/4 av refpn ) the voltage tap of the array and the analog input voltage are compared and bit 10 of the sar is manipulated according to the result of the comparison. analog input voltage voltage tap of array: bit 10 = 1 analog input voltage voltage tap of array: bit 10 = 0 comparison is continued like this to bit 0 of the sar. (4) array the array generates the comparison volt age input from an analog input pin. (5) successive approximation register (sar) the sar is a 12-bit register that se ts voltage tap data whose values from th e array match the voltage values of the analog input pins, 1 bit at a time star ting from the most significant bit (msb). if data is set in the sar all the way to the least signifi cant bit (lsb) (end of a/d c onversion), the contents of the sar (conversion results) are held in a/dn conversion result registers 0 to 15 (adncr0 to adncr15) (n = 0, 1). in the extension buffer mode, however, the conversion result is stored in a/dn conversion result extension buffer registers 0 to 4 and, when selection load trigger x is generated, shifted to and stored in the adnecr0 to adnecr4 registers (x = 1, 2). when all t he specified a/d conversion operations have ended, an a/dn conversion end interrupt requ est signal (intadn) is generated.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 620 (6) a/dn conversion result registers 0 to 15 (adncr0 to adncr15), a/dn conversion result registers 0h to 15h (adncr0h to adncr15h) (n = 0, 1) the adncr0 to adncr15 and adncr0h to adncr15h r egisters are registers that hold the a/d conversion results. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar) and stored in the hig her 12 bits of the adncr0 to adncr 15 registers. the lower 4 bits of these registers are always 0 when read. the higher 8 bits of the result of a/d conversion are read from the adncr0h to adncr15h registers. to read the result of a/d conversion in 16-bit units, s pecify the adncr0 to adncr15 registers. to read the higher 8 bits, specify the adncr0h to adncr15h registers. (7) a/dn conversion result extensi on registers 0 to 4 (adnecr0 to adnecr4), a/dn conversion result extension registers 0h to 4h (adn ecr0h to adnecr4h) (n = 0, 1) the adnecr0 to adnecr4 and adnecr0h to adnecr 4h registers are registers that hold the a/d conversion results. these register s can be used only in extension buf fer mode. when a/d conversion is completed, the a/d conversion result is stored in the a/dn conversion re sult extension buffer register. if selection load trigger 1 is generated a fter that, the a/d conversion result is shifted from a/dn conversion result extension buffer registers 0 to 2 to the higher 12 bits of the adnecr0 to adnecr2 registers for storage. bits 1 to 3 are always 0 when read. if selection load trigger 2 is generated, the a/d c onversion result is shifted from a/dn conversion result extension buffer regist ers 3 and 4 to the higher 12 bits of the adnecr3 and adnecr4 registers. bits 1 to 3 are always 0 when read. the higher 8 bits of the result of a/d conversion are read from the adnecr0h to adnecr4h registers. to read the result of a/d conversion in 16-bit units, s pecify the adnecr0 to adnecr4 registers. to read the higher 8 bits, specify the adne cr0h to adnecr4h registers. (8) ani00 to ani05, ani10 to ani17 pins (n = 0, 1) the ani00 to ani05 and ani10 to ani 17 pins are analog input pins for a/d converters 0 and 1. they input the analog signals to be a/d converted. caution make sure that the volt ages input to the ani00 to ani05 and ani10 to ani17 pins do not exceed the rated values. if a volt age higher than or equal to av refpn or lower than or equal to av ssn (even within the range of the absolute m aximum ratings) is input to a channel, the conversion value of the channe l is undefined, and the conversion values of the other channels may also be affected. (9) av refpn pin (n = 0, 1) this pin is used for inputting the reference voltage of a/ d converters 0 and 1. it converts signals input to the analog input pin to digital signals based on the voltage applied between av refpn and av ssn (n = 0, 1). always make the potential at this pin the same as that at the ev dd0 , ev dd1 , and ev dd2 (v850e/ig3 only) pins even when a/d converters 0 and 1 are not used. the operating voltag e range of the av refpn pin is ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av ddn = av refpn = 4.0 to 5.5 v. (10) av ssn pin (n = 0, 1) this is the ground pin of a/d converters 0 and 1. always make the potential at this pin the same as that at the ev ss0 , ev ss1 , and ev ss2 (v850e/ig3 only) pins even when a/ d converters 0 and 1 are not used.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 621 (11) av ddn pin (n = 0, 1) this pin is the analog power supply pi n of a/d converters 0 and 1. supply the same potential to the av dd0 and av dd1 pins. always make the potential at this pin the same as that at the ev dd0 , ev dd1 , and ev dd2 (v850e/ig3 only) pins even when a/d converters 0 and 1 are not used. the operating voltag e range of the av ddn pin is ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av refpn = av ddn = 4.0 to 5.5 v. (12) crefnl, crefnf pins (n = 0, 1) the crefnl pin supplies the low range of the referenc e voltage of the comparator for overvoltage detection, and the crefnf pin supplies the full range of the re ference voltage (input voltage range of cref0l and cref1l pins = 0.02av dd + 0.1 to 0.5av dd ? 0.1 v, input range of cref0f and cref1f pins = 0.02av dd + 0.1 to 0.92av dd ? 0.1 v).
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 622 12.3 control registers a/d converters 0 and 1 are contro lled by the following registers. ? a/d converter n scan mode register (adnscm) ? a/d converter n scan mode register l (adnscml) ? a/d converter n scan mode register h (adnscmh) ? a/d converter n conversion time control register (adnctc) ? a/d converter n conversion channel specification register (adnchen) ? a/d converter n conversion channel specification register l (adnchenl) ? a/d converter n conversion channel specification register h (adnchenh) ? a/d converter n control register (adnctl0) ? a/d converter n trigger select register (adntsel) ? a/d converter n channel specificat ion registers 1 and 2 (adnch1, adnch2) ? a/d converter n flag register (adnflg) ? a/d converter n flag buffer register (adnflgb) ? a/dldtrg1 input select register (adlts1) ? a/dldtrg2 input select register (adlts2) ? a/d converter n clock select register (adnocks) ? a/d trigger falling edge specification register (adtf) ? a/d trigger rising edge spec ification register (adtr) ? operational amplifier n c ontrol register 0 (opnctl0) ? comparator n control register s 0 to 3 (cmpnctl0 to cmpnctl3) ? comparator output digital noise eliminat ion registers nl, nf (cmpnfcnl, cmpnfcnf) ? comparator output interrupt rising edge specification register (cmpor) ? comparator output interrupt falling edge specification register (cmpof) the following registers are also used. ? a/dn conversion result registers 0 to 15 (adncr0 to adncr15) ? a/dn conversion result registers 0h to 15h (adncr0h to adncr15h) ? a/dn conversion result extension registers 0 to 4 (adnecr0 to adnecr4) ? a/dn conversion result extension registers 0h to 4h (adnecr0h to adnecr4h)
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 623 (1) a/d converter n scan mode register (adnscm) the adnscm register is a regist er that specifies the normal operat ion mode and controls conversion operations. this register can be read or written in 16-bit units. when the higher 8 bits of the adnscm register are used as the adnscmh register and the lower 8 bits, as the adnscml register, these registers can be read or written in 1-bit or 8-bit units. however, bit 14 is read-only. reset sets this register to 0000h. (1/2) adnce 0 1 stop conversion operation start conversion operation a/d conversion operation control adncs 0 1 a/d conversion stopped a/d conversion operating (remains ?1? even when the channel is changed during successive conversion) status of a/d converter n note 2 adnplm 0 0 1 adntrg1 0 0 0 a/d trigger mode hardware trigger mode note 3 a/d trigger polling mode setting prohibited other than above normal operation mode specification adntrg0 0 1 0 after reset: 0000h r/w address: ad0scm fffff220h, ad1scm fffff2a0h adnscm (n = 0, 1) adn ce adn cs 0 0 0 adn plm adn trg1 adn trg0 adn ps 0 00000 note 1 0 adnps 0 1 a/d power save mode a/d operational mode a/d power save mode specification <15> 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 note 1. when using a/d converters 1 and 0, be sure to set bit 1 to "1". this setting can be performed at the same time as other adnscm register bits. notes 2. the adncs bit is set to 1 five basic clocks (f ad01 ) after the adnce bit has been set to 1 and a/d conversion has been started. a/d conversion is started when a trigger signal, such as one from a timer, is input in the hardware trigger mode, conversion cha nnel specification mode, or extension buffer mode. in the a/d trigger mode and a/d trigger polling mode, it is started when the adnce bit is 1. 3. in the extended operation mode (conve rsion channel specification mode or extension buffer mode), be sure to set the hardware trigger mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 624 (2/2) cautions 1. in the a/d trigger mode or the a/d tr igger polling mode, conversi on is triggered when 1 is written to the adnce bit. in the hardware trigger mode, the c onversion channel specification mode, or the extension buffer mode, the trigger signal wait st ate starts when 1 is written to the adnce bit. the adnce bit is not cleared to 0 even after the a/dn c onversion end interrupt request signal (intadn) is generate d in all modes. to stop the a/d conversion operation, therefore, write 0 to the adnce bit. 2. if the adnscm register is written duri ng a/d conversion operation (adncs bit = 1), the operation is performed as follows in each mode. the corresponding conversion result register is undefined during a/d conversion operation. ? in a/d trigger mode, a/d trigger polling mode a/d conversion is stopped and executed again from the beginning. ? in hardware trigger mode , conversion channel specifi cation mode, extension buffer mode a/d conversion is stopped and the tri gger standby state is restored again. 3. make sure that time of at least five basic clocks (f ad01 ) passes before successively writing data to the adnscm register when the con version operation is enabled (adnce bit = 1). otherwise, the register may not be set correctly. the register can be successively written if the adnce bit is set to 1 after the adnscm register is written when adnce bit = 0. 4. the adncs bit remains set (1) when the conversion channel is changed during successive conversion. 5. it is recommended to set the a/d power save mode (adnps bit = 0) when the a/d converter is not used. 6. the setting procedure is as follows when an a/d conver sion operation is started (after reset release and after recovery from th e a/d power save mode (adnps bit = 0)). <1> select an input clock (f ad01 ) by using the adnocks regi ster and set the adnocksen bit to 1 (enable supplying the operating clock to a/d converter n). <2> set the a/d conversion time by us ing the adnctc.adnfr3 to adnfr0 bits. <3> set the adnps bit to 1 (a/d operation mode). <4> wait for 1 s or longer after <3>. <5> initialize a/d converters 0 and 1. <6> set the adnce bit to 1 (enable conversion operation). 7. the setting procedure is as follows when an a/d conversion operation is stopped. <1> set the adnce bit to 0 (stop conver sion operation) (retaining adnps bit = 1). <2> set the adnps bit to 0 (a/d power save mode). <3> set the adnocks.adnocksen bit to 0 (stop supplying the operating clock to a/d converter n). 8. it is recommended to set the a/d power save mode even in the id le and stop modes. follow the setting procedure in caution 6 above when rel easing the idle or stop mode by using the reset signal. 9. be sure to set bits 0, 2 to 6 and 11 to 13 to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 625 (2) a/d converter n conversion ti me control register (adnctc) the adnctc register is a register that specifies the number of a/d conversion clocks and a/d conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 adnctc (n = 0, 1) 0 00 adnfr3 adnfr2 adnfr1 adnfr0 after reset: 00h r/w address: ad0ctc fffff222h, ad1ctc fffff2a2h cautions 1. see table 12-2 number of a/d conver sion clocks and a/d con version time for the adnfr3 to adnfr0 bits. 2. set the adnfr3 to adnfr0 bits when the adnscm.adnce bit = 0 (conversion operation is stopped). 3. be sure to set bits 4 to 7 to ?0?. table 12-2. number of a/d conver sion clocks and a/d conversion time a/d conversion time ( s) note 2 adnfr3 adnfr2 adnfr1 adnfr0 number of a/d conversion clocks note 1 f ad01 = 16 mhz (f xx = 64 mhz) f ad01 = 12 mhz (f xx = 48 mhz) 0 0 0 0 89 5.56 7.42 0 0 0 1 88 5.50 7.33 0 0 1 0 57 3.56 4.75 0 0 1 1 56 3.50 4.67 0 1 0 0 41 2.56 3.42 0 1 0 1 40 2.50 3.33 0 1 1 0 35 2.19 2.92 0 1 1 1 34 2.13 2.83 1 0 0 0 34 2.13 2.83 1 0 0 1 33 2.06 2.75 1 0 1 0 33 2.06 2.75 1 0 1 1 32 2.00 2.67 1 1 0 0 32 2.00 2.67 1 1 0 1 31 setting prohibited 2.58 1 1 1 0 31 setting prohibited 2.58 1 1 1 1 30 setting prohibited 2.50 notes 1. the number of clocks (f ad01 ) from the start to the end of a/d conversion. the number of clocks (f ad01 ) per conversion during successive conversion (1-channel conversion (repeat), multiple channel conversion, or mult iple channel conversion (repeat)) is the same. 2. set the a/d conversion time in a range of 2 to 7.42 s. a/d conversion time = 1/f ad01 number of a/d conversion clocks
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 626 (3) a/d converter n conversion channe l specification register (adnchen) the adnchen register is a register that specifies the analog input pi n, number of conversion times, and conversion result register. this register is used to specify an analog input pin in th e a/d trigger mode, a/d trigger polling mode, and hardware trigger mode. the adncrm register correspon ds to an analog input pin on a one-to-one basis. use the bits (ad0chen00 to ad0chen05 and ad1chen00 to ad1chen07) corresponding to the ani00 to ani05 and ani10 to ani17 pins. if two or more analog in put pins are specified, they are sequentially selected, starting from the one with the lowest number, for conversion (when ad1chen register = 004dh: ani10 ani12 ani13 ani16). if an analog input pin that is not specified is skipped during successive conversion. in the conversion channel specificat ion mode, specify the number of time s of conversion and a conversion result register. specify an analog input pin by using the adnch1 register. a value set to the lower bits of the adnchen register, justified to the lo west bit, is the number of times of conversion. these bits correspond to the adncrm and adnchmh registers on a one-to-one basis. because the adnchen register is of master/slave c onfiguration, a new analog input pin can be set to the master register during a/d conversion operation. the set value of the master register is transferred to a slave register after completion of a/d conversion (after the a/ dn conversion end interrupt request signal (intadn) is generated). this register can be read or written in 16-bit units. when the higher 8 bits of the adnchen register are us ed as the adnchenh register and the lower 8 bits, as the adnchenl register, these registers can be read or written in 1-bit or 8-bit units. reset sets this register to 0000h. after reset: 0000h r/w address: ad0chen fffff224h, ad1chen fffff2a4h adnchen (n = 0, 1) adn chen 15 adn chen 14 adn chen 13 adn chen 12 adn chen 11 adn chen 10 adn chen 9 adn chen 8 adn chen 7 adn chen 6 adn chen 5 adn chen 4 adn chen 3 adn chen 2 adn chen 1 adn chen 0 remark see table 12-3 specifying analog input pin in a/ d trigger mode, a/d trigger polling mode, and hardware trigger mode for how to specify an analog input pin in the a/d trigger mode, a/d trigger polling mode, and hardware trigger mode. for how to specify the number of times of conversion and the a/d conversion re sult register in the conversion channel specification mode, see table 12-4 correspondence among set value of adnchen register, number of times of conversion, and a/d conversion result regist er in conversion channel specification mode . cautions 1. the a/d conver sion operation is prohibited when the adnchen register = 0000h. if the adnchen register = 0000h, the ope ration is the same as when the adnchen register = 0001h. 2. do not write the adnchen re gister when the adnsc m.adnps bit = 0. if it is written, the cpu deadlocks. 3. to change the setting of the adnchen regi ster when the adnscm. adnce bit = 1 in the hardware trigger mode, be sure to set the adnce bit to 0.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 627 table 12-3. specifying analog input pin in a/d trigger mode, a/d trigger polling mode, and hardware trigger mode adnchenm bit specification of analog input pin 0 specifying anink pin is prohibited. 1 specifying anink pin is enabled. remark a/d converter 0: n = 0, k = 0 to 5, m = 0 to 15 a/d converter 1: n = 1, k = 0 to 7, m = 0 to 15 table 12-4. correspondence among set value of adnche n register, number of times of conversion, and a/d conversion result register in conversion channel specification mode adnchen register value number of times of conversion a/d conversion result register 0001h 1 adncr0 adncr0h 0003h 2 adncr0, adncr1 adncr0h, adncr1h 0007h 3 adncr0 to adncr2 adncr0h to adncr2h 000fh 4 adncr0 to adncr3 adncr0h to adncr3h 001fh 5 adncr0 to adncr4 adncr0h to adncr4h 003fh 6 adncr0 to adncr5 adncr0h to adncr5h 007fh 7 adncr0 to adncr6 adncr0h to adncr6h 00ffh 8 adncr0 to adncr7 adncr0h to adncr7h 01ffh 9 adncr0 to adncr8 adncr0h to adncr8h 03ffh 10 adncr0 to adncr9 adncr0h to adncr9h 07ffh 11 adncr0 to adncr10 adncr0h to adncr10h 0fffh 12 adncr0 to adncr11 adncr0h to adncr11h 1fffh 13 adncr0 to adncr12 adncr0h to adncr12h 3fffh 14 adncr0 to adncr13 adncr0h to adncr13h 7fffh 15 adncr0 to adncr14 adncr0h to adncr14h ffffh 16 adncr0 to adncr15 adncr0h to adncr15h others setting prohibited caution an analog input pin is specified by the adnch1 register in the conversion channel specification mode. remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 628 (4) a/dn conversion result registers 0 to 15, 0h to 15h (adncr0 to adncr15, adncr0h to adncr15h) the adncrm and adncrmh registers are registers that hold the a/d conversion results in the a/d trigger mode, a/d trigger polling mode, hardw are trigger mode, or conversion cha nnel specification mode. sixteen of these registers are provided per circuit, and two circuits are available. each ti me a/d conversion ends, the conversion result is loaded from the successive approxim ation register (sar) and stored in the higher 12 bits of the adncrm register. the lower 4 bits of these registers are always 0 when read. the higher 8 bits of a/d conversion re sult are read to the adncrmh register. these registers can only be read in 16-bit or 8-bit unit s. when the a/d conversion results are read in 16-bit units, the adncrm register is spec ified, and when the higher 8 bits ar e read, the adncrmh register is specified. reset sets these registers to 0000h. remark while the result of a/d conver sion is stored in the adncrm r egister, a read access to the same register is held pending. the pending read access is executed after the a/d conversion result is stored. similarly, storing the resu lt of a/d conversion in the adncrm register is held pending while a read access to that register is made. the pending a/d conversi on result storing processing is executed after completion of the read access.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 629 after reset: 0000h r address: ad0cr0 fffff200h, ad0cr1 fffff202h, adncrm (n = 0, 1) (m = 0 to 15) adn crm 11 adn crm 10 adn crm 9 adn crm 8 adn crm 7 adn crm 6 adn crm 5 adn crm 4 adn crm 3 adn crm 2 adn crm 1 adn crm 0 0000 ad0cr2 fffff204h, ad0cr3 fffff206h, ad0cr4 fffff208h, ad0cr5 fffff20ah, ad0cr6 fffff20ch, ad0cr7 fffff20eh, after reset: 0000h r address: ad0cr0h fffff201h, ad0cr1h fffff203h, adncrm11 adncrmh (n = 0, 1) (m = 0 to 15) adncrm10 adncrm9 adncrm8 adncrm7 adncrm6 adncrm5 adncrm4 76 54 32 1 0 ad0cr8 fffff210h, ad0cr9 fffff212h, ad0cr10 fffff214h, ad0cr11 fffff216h, ad0cr12 fffff218h, ad0cr13 fffff21ah, ad0cr14 fffff21ch, ad0cr15 fffff21eh, ad1cr0 fffff280h, ad1cr1 fffff282h, ad1cr2 fffff284h, ad1cr3 fffff286h, ad1cr4 fffff288h, ad1cr5 fffff28ah, ad1cr6 fffff28ch, ad1cr7 fffff28eh, ad1cr8 fffff290h, ad1cr9 fffff292h, ad1cr10 fffff294h, ad1cr11 fffff296h, ad1cr12 fffff298h, ad1cr13 fffff29ah, ad1cr14 fffff29ch, ad1cr15 fffff29eh ad0cr2h fffff205h, ad0cr3h fffff207h, ad0cr4h fffff209h, ad0cr5h fffff20bh, ad0cr6h fffff20dh, ad0cr7h fffff20fh, ad0cr8h fffff211h, ad0cr9h fffff213h, ad0cr10h fffff215h, ad0cr11h fffff217h, ad0cr12h fffff219h, ad0cr13h fffff21bh, ad0cr14h fffff21dh, ad0cr15h fffff21fh, ad1cr0h fffff281h, ad1cr1h fffff283h, ad1cr2h fffff285h, ad1cr3h fffff287h, ad1cr4h fffff289h, ad1cr5h fffff28bh, ad1cr6h fffff28dh, ad1cr7h fffff28fh, ad1cr8h fffff291h, ad1cr9h fffff293h, ad1cr10h fffff295h, ad1cr11h fffff297h, ad1cr12h fffff299h, ad1cr13h fffff29bh, ad1cr14h fffff29dh, ad1cr15h fffff29fh
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 630 the correspondence between the analog input pins and the a/d conversion result regi sters in the a/d trigger mode, a/d trigger polling mode, hardw are trigger mode, and conversion chan nel specification mode is shown below. table 12-5. correspondence between analog input pi ns and a/d conversion result registers in a/d trigger mode, a/d trigger pollin g mode, hardware trigger mode a/d converter analog input pin a/d conversion result register ani00 ad0cr0, ad0cr0h ani01 ad0cr1, ad0cr1h ani02 ad0cr2, ad0cr2h ani03 ad0cr3, ad0cr3h ani04 ad0cr4, ad0cr4h a/d converter 0 ani05 ad0cr5, ad0cr5h ani10 ad1cr0, ad1cr0h ani11 ad1cr1, ad1cr1h ani12 ad1cr2, ad1cr2h ani13 ad1cr3, ad1cr3h ani14 ad1cr4, ad1cr4h ani15 ad1cr5, ad1cr5h ani16 ad1cr6, ad1cr6h a/d converter 1 ani17 ad1cr7, ad1cr7h
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 631 table 12-6. correspondence between analog input pi ns and a/d conversion result registers in conversion channel specification mode adnchen register set value analog input pin a/d conversion result register 0001h adncr0 adncr0h 0003h adncr0, adncr1 adncr0h, adncr1h 0007h adncr0 to adncr2 adncr0h to adncr2h 000fh adncr0 to adncr3 adncr0h to adncr3h 001fh adncr0 to adncr4 adncr0h to adncr4h 003fh adncr0 to adncr5 adncr0h to adncr5h 007fh adncr0 to adncr6 adncr0h to adncr6h 00ffh adncr0 to adncr7 adncr0h to adncr7h 01ffh adncr0 to adncr8 adncr0h to adncr8h 03ffh adncr0 to adncr9 adncr0h to adncr9h 07ffh adncr0 to adncr10 adncr0h to adncr10h 0fffh adncr0 to adncr11 adncr0h to adncr11h 1fffh adncr0 to adncr12 adncr0h to adncr12h 3fffh adncr0 to adncr13 adncr0h to adncr13h 7fffh adncr0 to adncr14 adncr0h to adncr14h ffffh set by adnch1.adntrgch12 to adnch1.adntrgch10 bits adncr0 to adncr15 adncr0h to adncr15h 0001h adncr0 adncr0h 0003h adncr0, adncr1 adncr0h, adncr1h 0007h adncr0 to adncr2 adncr0h to adncr2h 000fh adncr0 to adncr3 adncr0h to adncr3h 001fh adncr0 to adncr4 adncr0h to adncr4h 003fh adncr0 to adncr5 adncr0h to adncr5h 007fh adncr0 to adncr6 adncr0h to adncr6h 00ffh adncr0 to adncr7 adncr0h to adncr7h 01ffh adncr0 to adncr8 adncr0h to adncr8h 03ffh adncr0 to adncr9 adncr0h to adncr9h 07ffh adncr0 to adncr10 adncr0h to adncr10h 0fffh adncr0 to adncr11 adncr0h to adncr11h 1fffh adncr0 to adncr12 adncr0h to adncr12h 3fffh adncr0 to adncr13 adncr0h to adncr13h 7fffh adncr0 to adncr14 adncr0h to adncr14h ffffh set by adnch1.adntrgch16 to adnch1.adntrgch14 bits adncr0 to adncr15 adncr0h to adncr15h others setting prohibited remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 632 (5) a/d converter n control register (adnctl0) the adnctl0 register is a register t hat specifies the operation mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 adnctl0 (n = 0, 1) 0 0 0 0 0 adnmd1 adnmd0 adnmd1 0 0 1 1 adnmd0 0 1 0 1 normal operating mode setting prohibited conversion channel specification mode extension buffer mode extended operating mode specification after reset: 00h r/w address: ad0ctl0 fffff230h, ad1ctl0 fffff2b0h cautions 1. set the adnmd1 and adnmd0 bi ts when the adnscm.adn ce bit = 0 (conversion operation is stopped) (the same value can be written to these bits when the adnce bit = 1 (conversion operation is enabled)). 2. in the conversion channel specification mode and extension buffe r mode, start of a/d conversion is delayed up to 1.5 basic clocks (f ad01 ) as compared with the normal operating mode. 3. be sure to set the hardware trigger m ode in the conversion channel specification mode and extension buffer mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 633 (6) a/d converter n trigger select register (adntsel) the adntsel register is a register that specifies trigger in the hardwar e trigger mode and conversion channel specification mode, and trigger (selec tion trigger 1, selection trigger 2, selection load trigger 1, and selection load trigger 2) in the extension buffer mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. adn ldtsel2 adnldtsel2 0 1 ldtrg1 ldtrg2 specification of selection load trigger 2 for adnecr3, adnecr4 registers adntsel (n = 0, 1) 0 adn trgsel21 adn trgsel20 adn ldtsel1 0 adn trgsel11 adn trgsel10 adntrgsel21 0 0 1 1 adntrgsel20 0 1 0 1 itrg1 itrg2 itrg3 itrg4 specification of selection trigger 2 for adnecr3, adnecr4 registers after reset: 10h r/w address: ad0tsel fffff231h, ad1tsel fffff2b1h adnldtsel1 0 1 ldtrg1 ldtrg2 specification of selection load trigger 1 for adnecr0 to adnecr2 registers adntrgsel11 adntrgsel10 0 0 1 1 0 1 0 1 itrg1 itrg2 itrg3 itrg4 ? in hardware trigger mode or conversion channel specification mode: trigger specification ? in expansion buffer mode: specification of selection trigger 1 for adnecr0 to adnecr2 registers note note note note note note note note note be sure to set bits 3, 5, and 7 to ?0? and set bit 4 to ?1? in the hardware trigger mode and conversion channel specification mode. caution set the adntsel regist er when the adnscm.adnce bit = 0 (conversion operation is stopped) (the same value can be written to the register when the adnce bit = 1 (conversion operation is enabled)).
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 634 (7) a/d converter n channel speci fication register 1 (adnch1) the adnch1 register is a register t hat specifies the analog input pin for selection trigger 1 in the conversion channel specification mode and extension buffer mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 adnch1 (n = 0, 1) adn trgch16 adn trgch15 adn trgch14 0 adn trgch12 adn trgch11 adn trgch10 adntrgch16 0 0 0 0 1 1 1 1 adntrgch15 0 0 1 1 0 0 1 1 anin0 anin1 anin2 anin3 anin4 anin5 ani16 ani17 specification of analog input pin for selection trigger 1 adntrgch14 0 1 0 1 0 1 0 1 after reset: 00h r/w address: ad0ch1 fffff232h, ad1ch1 fffff2b2h adntrgch12 0 0 0 0 1 1 1 1 adntrgch11 0 0 1 1 0 0 1 1 anin0 anin1 anin2 anin3 anin4 anin5 ani16 ani17 specification of analog input pin for selection trigger 1 adntrgch10 0 1 0 1 0 1 0 1 cautions 1. set the adnch1 register when the adnscm.adnce bit = 0 (conversion operation is stopped) (the same value can be written to the register when the adnce bit = 1 (conversion operation is enabled)). 2. be sure to set bits 3 and 7 to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 635 setting the adnch1 register is enabled when a conver sion operation is enabled (adnscm.adnce bit = 1) in the conversion channel specification mode or extension buffer mode. when the first selection trigger 1 is generated after the conversion operatio n is enabled (adnce bit = 1), the analog input pin specified by the adntrgch12 to adntrgch10 bits is selected and a/d conversion is ex ecuted. when the next selection trigger 1 is later generated, the analog input pin specified by the adntrgch 16 to adntrgch14 bits is selected and a/d conversion is executed. after that, t he analog input pins are alternately selected for output each time selection trigger 1 is generated. figure 12-7. adnch1 register operation selection trigger 1 100 101 101 100 100 101 adntrgch16 to adntrgch14 bits adntrgch12 to adntrgch10 bits selection of analog input pin if an error occurs (when selection trigger 1 is generated during a/d conversion), the analog input pin specified by the adntrgch12 to adntrgch10 bits and the analog input pin s pecified by the adntrgch16 to adntrgch14 bits are alternately se lected, but the selected analog input pin is not changed because a/d conversion is in progress. figure 12-8. adnch1 register operation in case of error 100 101 101 100 101 100 selection trigger 1 a/d conversion status error occurs during a/d conversion during a/d conversion during a/d conversion during a/d conversion adntrgch16 to adntrgch14 bits adntrgch12 to adntrgch10 bits selection of analog input pin
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 636 (8) a/d converter n channel speci fication register 2 (adnch2) the adnch2 register is a register t hat specifies the analog input pin for selection trigger 2 in the extension buffer mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 adnch2 (n = 0, 1) adn trgch26 adn trgch25 adn trgch24 0 adn trgch22 adn trgch21 adn trgch20 adntrgch26 0 0 0 0 1 1 1 1 adntrgch25 0 0 1 1 0 0 1 1 anin0 anin1 anin2 anin3 anin4 anin5 ani16 ani17 specification of analog input pin for selection trigger 2 adntrgch24 0 1 0 1 0 1 0 1 after reset: 00h r/w address: ad0ch2 fffff233h, ad1ch2 fffff2b3h adntrgch22 0 0 0 0 1 1 1 1 adntrgch21 0 0 1 1 0 0 1 1 anin0 anin1 anin2 anin3 anin4 anin5 ani16 ani17 specification of analog input pin for selection trigger 2 adntrgch20 0 1 0 1 0 1 0 1 cautions 1. set the adnch2 register when the adnscm.adnce bit = 0 (conversion operation is stopped) (the same value can be written to the register when the adnce bit = 1 (conversion operation is enabled)). 2. the adnch2 register is val id only in the extension buffer mode; it is invalid in any other mode. 3. be sure to set bits 3 and 7 to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 637 setting the adnch2 register is enabled when a conver sion operation is enabled (adnscm.adnce bit = 1) in the extension buffer mode. when the first selection tr igger 2 is generated after the conversion operation is enabled (adnce bit = 1), the analog input pin s pecified by the adntrgch22 to adntrgch20 bits is selected and a/d conversion is ex ecuted. when the next selection tri gger 2 is later generated, the analog input pin specified by the adntrgch 26 to adntrgch24 bits is selected an d a/d conversion is executed. after that, the analog input pins are alternately selected for output each time selecti on trigger 2 is generated. figure 12-9. adnch2 register operation selection trigger 2 100 101 101 100 100 101 adntrgch26 to adntrgch24 bits adntrgch22 to adntrgch20 bits selection of analog input pin if an error occurs (when selection trigger 2 is generated during a/d conversion), the analog input pin specified by the adntrgch22 to adntrgch20 bits and the analog input pin s pecified by the adntrgch26 to adntrgch24 bits are alternately se lected, but the selected analog input pin is not changed because a/d conversion is in progress. figure 12-10. adnch2 register operation in case of error 100 101 101 100 101 100 selection trigger 2 a/d conversion status error occurs during a/d conversion during a/d conversion during a/d conversion during a/d conversion adntrgch26 to adntrgch24 bits adntrgch22 to adntrgch20 bits selection of analog input pin
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 638 (9) a/dn conversion resu lt extension registers 0 to 4, 0h to 4h (adnecr0 to adnecr4, adnecr0h to adnecr4h) the adnecra and adnecrah registers hold the result of a/d conversion in their higher 12 bits and indicate the status (information on the a/d conversion result of the analog input pin specified by the adnchx.adntrgchx2 to adntrgchx0 bits or adntrg chx6 to adntrgchx4 bits) of the a/d conversion result with the lower 1 bit in the ext ension buffer mode. five of these regi sters are provided per circuit and two circuits are available. when a/d conversion is comp leted, the a/d conversion re sult is stored in a/dn conversion result extension buffer register a. when selection load trigger 1 is later generated, the a/d conversion result is shifted from a/dn conversion result extension buffer register s 0 to 2 to the higher 12 bits of the adnecr0 to adnecr2 registers an d stored. bits 1 to 3 are always 0 when read. when selection load trigger 2 is generated, the a/d conversion result is sh ifted from the a/dn conversion result extension buffer registers 3 and 4 to the higher 12 bits of the adnecr3 and adnecr4 registers and stored. bits 1 to 3 are always 0 when read. the higher 8 bits of the a/d conversion re sult are read from the adnecrah register. these registers are read-only in 16-bit or 8-bit units. to read the a/d conversion result in 16-bit units, specify the adnecra register. specify the adnecrah register to read the higher 8 bits of the a/d conversion result. reset sets these registers to 0000h. remark while the result of a/d conversion is stored in the adnecra register, a read access to that register is held pending. the pending read access is executed when storing the a/ d conversion result is completed. similarly, storing t he a/d conversion result in the adnecra register is held pending while a read access is made to that register. t he pending a/d conversion re sult is stored in the register after the read access is completed.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 639 after reset: 0000h r address: ad0ecr0 fffff240h, ad0ecr1 fffff242h, adnecra (n = 0, 1) (a = 0 to 4) adn ecra 11 adn ecra 10 adn ecra 9 adn ecra 8 adn ecra 7 adn ecra 6 adn ecra 5 adn ecra 4 adn ecra 3 adn ecra 2 adn ecra 1 adn ecra 0 000 adn ch flga ad0ecr2 fffff244h, ad0ecr3 fffff246h, ad0ecr4 fffff248h, ad1ecr0 fffff2c0h, ad1ecr1 fffff2c2h, after reset: 00h r address: ad0ecr0h fffff241h, ad0ecr1h fffff243h, adnecra11 adnecrah (n = 0, 1) (a = 0 to 4) adnecra10 adnecra9 adnecra8 adnecra7 adnecra6 adnecra5 adnecra4 76 54 32 1 0 ad1ecr2 fffff2c4h, ad1ecr3 fffff2c6h, ad1ecr4 fffff2c8h ad0ecr2h fffff245h, ad0ecr3h fffff247h, ad0ecr4h fffff249h, ad1ecr0h fffff2c1h, ad1ecr1h fffff2c3h, ad1ecr2h fffff2c5h, ad1ecr3h fffff2c7h, ad1ecr4h fffff2c9h adnchflga 0 1 a/d conversion result for analog input pin set by adnchx.adntrgchx2 to adnchx.adntrgchx0 bits a/d conversion result for analog input pin set by adnchx.adntrgchx6 to adnchx.adntrgchx4 bits status of a/d conversion result (x = 1, 2) caution the adnecra and adnecrah registers are valid only in the extensi on buffer mode; they are invalid in any other mode. the correspondence between the analog input pins and t he a/dn conversion result extension registers is shown below. table 12-7. correspondence between analog input pins and a/d conversion result extension registers analog input pin a/dn conversion result register adnecr0, adnecr0h adnecr1, adnecr1h set with adnch1 register?s adntrgch12 to adntrgch10, adntrgch16 to adntrgch14 bits adnecr2, adnecr2h adnecr3, adnecr3h set with adnch2 register?s adntrgch22 to adntrgch20, adntrgch26 to adntrgch24 bits adnecr4, adnecr4h remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 640 (10) a/d converter n flag register (adnflg) the adnflg register indicates that an error has occurred when selection load trigger x is generated in the extension buffer mode (x = 1 or 2). the adnterr2 an d adnterr1 flags can only be read and cleared when the conversion operation is sto pped (adnscm.adnce bit = 0). this register is read-only in 8-bit units. reset sets this register to 00h. 0 adnterr2 note 0 1 occurrence timing error of selection load trigger 2 has not occurred occurrence timing error of selection load trigger 2 has occurred occurrence timing error flag of selection load trigger 2 adnflg (n = 0, 1) 0 0 0 0 0 adn terr2 note adn terr1 note after reset: 00h r address: ad0flg fffff254h, ad1flg fffff2d4h adnterr1 note 0 1 occurrence timing error of selection load trigger 1 has not occurred occurrence timing error of selection load trigger 1 has occurred occurrence timing error flag of selection load trigger 1 note the adnterr2 and adnterr1 flags are valid only in the extension buffer mode; they are fixed to 0 in any other mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 641 (11) a/d converter n flag buffer register (adnflgb) the adnflgb register indicates t hat an error has occurred when select ion trigger x is generated in the extension buffer mode (x = 1 or 2). the adnterrb2 and adnterrb 1 flags can only be read and cleared when the conversion operation is stopped (adnscm.adnce bit = 0). this register is read-only in 8-bit units. reset sets this register to 00h. 0 adnterrb2 note 0 1 occurrence timing error of selection trigger 2 has not occurred occurrence timing error of selection trigger 2 has occurred occurrence timing error flag of selection trigger 2 adnflgb (n = 0, 1) 00000 adn terrb2 note adn terrb1 note after reset: 00h r address: ad0flgb fffff255h, ad1flgb fffff2d5h adnterrb1 note 0 1 occurrence timing error of selection trigger 1 has not occurred occurrence timing error of selection trigger 1 has occurred occurrence timing error flag of selection trigger 1 note the adnterrb2 and adnterrb1 flags are valid only in the extension buffer mode; they are fixed to 0 in any other mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 642 (12) a/d ldtrg1 input select register (adlts1) the adlts1 register is a register t hat specifies the input signal for sele ction load trigger (ldtrg1) in the extension buffer mode. this register can be read or written in 8-bit units. reset sets this register to 00h. 0 adlts1 0 0 0 0 0 0 adlts10 after reset: 00h r/w address: fffff2f8h adlts10 0 1 tabtiov0 signal tabtiov1 signal specification of input signal for ldtrg1 note the adlts1 register is valid only in the extens ion buffer mode; it is invalid in any other mode. (13) a/d ldtrg2 input select register (adlts2) the adlts2 register is a register t hat specifies the input signal for sele ction load trigger (ldtrg2) in the extension buffer mode. this register can be read or written in 8-bit units. reset sets this register to 00h. 0 adlts2 0 0 0 0 0 0 adlts20 after reset: 00h r/w address: fffff2fah adlts20 0 1 tabticc00 signal tabticc10 signal specification of input signal for ldtrg2 note the adlts2 register is valid only in the extens ion buffer mode; it is invalid in any other mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 643 (14) a/d converter n clock select register (adnocks) the adnocks register is a regi ster that selects the clock (f ad01 ) to be input to the a/d converter n. this register can be read or written in 8-bit units. reset sets this register to 00h. 0 adnocksen 0 1 stop operation clock supply of a/d converter n enable operation clock supply of a/d converter n clock operation control adnocks (n = 0, 1) 00 adnocksen 00 adnocks1 adnocks0 after reset: 00h r/w address: ad0ocks fffff270h, ad1ocks fffff274h adnocks1 0 0 1 1 adnocks0 0 1 0 1 f xx /2 f xx /3 f xx /4 (when f xx = 64 mhz) setting prohibited input clock selection of a/d converter n (f ad01 ) cautions 1. set f ad01 to 16 mhz or lower. 2. when a/d converter n is used, be su re to set the adnocks register and set the adnscm.adnps bit to 1, as well as to read the a/d conversion result register. 3. be sure to set bits 2, 3, and 5 to 7 to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 644 (15) a/d trigger rising edge, falling edge specification registers (adtr, adtf) the adtr and adtf registers are registers that s pecify the trigger mode of the adtrg0/intadt0 and adtrg1/intadt1 pins and can specify the valid edge inde pendently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al trigger input of the a/ d converter n (alternate function)/external interrupt func tion (alternate func tion) to the port mode, an edge may be detected. therefore, be sure to set the ad tfn and adtrn bits to 00, and then set the port mode. 0 adtf 0 0 0 0 0 adtf1 adtf0 after reset: 00h r/w address: fffff2f0h 0 adtr 0 0 0 0 0 adtr1 adtr0 after reset: 00h r/w address: fffff2f2h remark for the valid edge specification, see table 12-8 . table 12-8. valid edge specification of adtrg0/intadt0 and adtrg1/intadt1 pins adtfn adtrn valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using these pins as the adtrgn/intadtn pins, be sure to set the adtfn and adtrn bits to 00. remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 645 (16) operational amplifier n control register 0 (opnctl0) the opnctl0 register is used to cont rol the operation of an operational amplif ier that amplifies the input level, and specify its gain. this register can be read or written in 8-bit units. reset sets this register to 00h. (1/2) op0en 0 1 operation disabled (not used) operation enabled (used) operation control of operational amplifier 0 for a/d converter 0 0 op0ctl0 0 0 op0en op0ga3 op0ga2 op0ga1 op0ga0 after reset: 00h r/w address: fffff260h op0ga3 0 0 0 0 0 0 0 0 1 1 1 1 1 op0ga2 0 0 0 0 1 1 1 1 0 0 0 0 1 2.500 2.667 2.857 3.077 3.333 3.636 4.000 4.444 5.000 5.714 6.667 8.000 10.00 setting prohibited gain specification of operational amplifier others op0ga1 0 0 1 1 0 0 1 1 0 0 1 1 0 op0ga0 0 1 0 1 0 1 0 1 0 1 0 1 0 cautions 1. be sure to set bits 5 to 7 of the op0ctl0 register to ?0?. 2. after enabling the operation of the ope rational amplifier, stabilization time of 10 s is required. if the op0ga3 to op0ga0 bit settings are changed, stabilization time of 5 s is required.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 646 (2/2) op12en 0 1 operation disabled (not used) operation enabled (used) operation control of operational amplifier 2 for a/d converter 1 op11en 0 1 operation disabled (not used) operation enabled (used) operation control of operational amplifier 1 for a/d converter 1 0 op1ctl0 op12en op11en op10en op1ga3 op1ga2 op1ga1 op1ga0 after reset: 00h r/w address: fffff2e0h op1ga3 0 0 0 0 0 0 0 0 1 1 1 1 1 op1ga2 0 0 0 0 1 1 1 1 0 0 0 0 1 2.500 2.667 2.857 3.077 3.333 3.636 4.000 4.444 5.000 5.714 6.667 8.000 10.00 setting prohibited gain specification of operational amplifier others op1ga1 0 0 1 1 0 0 1 1 0 0 1 1 0 op1ga0 0 1 0 1 0 1 0 1 0 1 0 1 0 op10en 0 1 operation disabled (not used) operation enabled (used) operation control of operational amplifier 0 for a/d converter 1 cautions 1. be sure to set bit 7 of the op1ctl0 register to ?0?. 2. after enabling the operation of the ope rational amplifier, stabilization time of 10 s is required. if the op1ga3 to op1ga0 bit settings are changed, stabilization time of 5 s is required.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 647 (17) comparator n contro l register 0 (cmpnctl0) the cmpnctl0 register is a register that controls the operation of the overvoltage detection comparator. this register can be read or written in 8-bit units. reset sets this register to 00h. (1/2) cmp12fen 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 2 (full range) for a/d converter 1 cmp11fen 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 1 (full range) for a/d converter 1 0 cmp1ctl0 cmp12fen cmp11fen cmp10fen 0 cmp12len cmp11len cmp10len after reset: 00h r/w address: fffff2e1h 0 cmp0ctl0 0 0 cmp0fen 00 0 cmp0len after reset: 00h r/w address: fffff261h cmp12len 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 2 (low range) for a/d converter 1 cmp11len 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 1 (low range) for a/d converter 1 cmp10fen 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 0 (full range) for a/d converter 1 cmp10len 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 0 (low range) for a/d converter 1 cmp0len 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 0 (low range) for a/d converter 0 cmp0fen 0 1 operation disabled (not used) operation enabled (used) operation control of comparator 0 (full range) for a/d converter 0
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 648 (2/2) cautions 1. be sure to set bits 1 to 3, 5 to 7 of the cmp0ctl0 regi ster and bits 3, 7 of the cmp1ctl0 register to ?0?. 2. after enabling the operation of the comparator, stabilization time of 10 s is required. 3. the input voltage range of the comparator is as follows, regard less of whether it is amplified by the operati onal amplifier or not. input voltage range of cref0l and cre f1l pins (low-range side): 0.02av dd + 0.1 to 0.5av dd ? 0.1 v input voltage range of cref0f and cre f1f pins (full-range side): 0.02av dd + 0.1 to 0.92av dd ? 0.1 v for details, see chapter 28 electrical specifications.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 649 (18) comparator n contro l register 1 (cmpnctl1) the cmpnctl1 register is a regist er that monitors the output of t he overvoltage detection comparator. this register is read-only in 8-bit units. reset sets this register to 00h. (1/2) cmp12fout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 2 (full range) for a/d converter 1 cmp11fout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 1 (full range) for a/d converter 1 cmp0fout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 0 (full range) for a/d converter 0 0 cmp1ctl1 cmp12fout cmp11foutcmp10fout 0 cmp12lout cmp11lout cmp10lout after reset: 00h r address: fffff2e2h 0 cmp0ctl1 0 0 cmp0fout 00 0 cmp0lout after reset: 00h r address: fffff262h cmp12lout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 2 (low range) for a/d converter 1 cmp11lout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 1 (low range) for a/d converter 1 cmp0lout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 0 (low range) for a/d converter 0 cmp10fout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 0 (full range) for a/d converter 1 cmp10lout 0 1 comparator output = 0 (without overvoltage detection) comparator output = 1 (with overvoltage detection) output level status of comparator 0 (low range) for a/d converter 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 650 (2/2) cautions 1. the cmp12fout, cmp11fout, cmp0fout, cmp10fout, cmp12lout, cmp11lout, cmp0lout, and cmp10lout bits are set to 0 wh en the input voltage falls to a level at which an overvoltage is not detected. 2. be sure to set bits 1 to 3, 5 to 7 of the cmp0ctl1 register and bits 3, 7 of the cmp1ctl1 register to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 651 (19) comparator n contro l register 2 (cmpnctl2) the cmpnctl2 register is a register that specifies the compare signal of the overvoltage detection comparator. this register can be read or written in 8-bit units. reset sets this register to 00h. cmp12sel 0 1 before operational amplifier 2 amplification after operational amplifier 2 amplification specification of compare signal of comparator 2 for a/d converter 1 cmp11sel 0 1 before operational amplifier 1 amplification after operational amplifier 1 amplification specification of compare signal of comparator 1 for a/d converter 1 cmp0sel 0 1 before operational amplifier 0 amplification after operational amplifier 0 amplification specification of compare signal of comparator 0 for a/d converter 0 0 cmp1ctl2 0 0 0 0 cmp12sel cmp11sel cmp10sel after reset: 00h r/w address: fffff2e3h 0 cmp0ctl2 0 0 0 0 0 0 cmp0sel after reset: 00h r/w address: fffff263h cmp10sel 0 1 before operational amplifier 0 amplification after operational amplifier 0 amplification specification of compare signal of comparator 0 for a/d converter 1 caution be sure to set bits 1 to 7 of the cmp0ctl2 register and bits 3 to 7 of the cmp1ctl2 register to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 652 (20) comparator n contro l register 3 (cmpnctl3) the cmpnctl3 register is a register that specifies the detection dire ction of the overvoltage detection comparator and selects the edge detection. this register can be read or written in 8-bit units. reset sets this register to 00h. (1/2) cmp0fds 0 1 logical product (and) detection (detects if input voltage is lower than reference value.) logical sum (or) detection (detects if input voltage is more than reference value.) specification of detection direction for comparator (full range) for a/d converter 0 cmp0fds cmp0ctl3 00 cmp0fde cmp0lds 00 cmp0lde after reset: 00h r/w address: fffff264h cmp0fde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 0 (full range) for a/d converter 0 cmp0lds 0 1 logical product (and) detection (detects if input voltage is lower than reference value.) logical sum (or) detection (detects if input voltage is more than reference value.) specification of detection direction for comparator (low range) for a/d converter 0 cmp0lde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 0 (low range) for a/d converter 0 remark the reference value means the reference vo ltage input to the cref0l and cref0f pins.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 653 (2/2) cmp11lde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 1 (low range) for a/d converter 1 cmp10lde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 0 (low range) for a/d converter 1 cmp12lde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 2 (low range) for a/d converter 1 cmp1fds 0 1 logical product (and) detection (detects if input voltage is lower than reference value.) logical sum (or) detection (detects if input voltage is more than reference value.) specification of detection direction for comparator (full range) for a/d converter 1 cmp12fde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 2 (full range) for a/d converter 1 cmp11fde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 1 (full range) for a/d converter 1 cmp1fds cmp1ctl3 cmp12fde cmp11fdecmp10fde cmp1lds cmp12lde cmp11lde cmp10lde cmp10fde 0 1 edge detection disabled (comparator not used) edge detection enabled (comparator used) selection of edge detection for comparator 0 (full range) for a/d converter 1 cmp1lds 0 1 logical product (and) detection (detects if input voltage is lower than reference value.) logical sum (or) detection (detects if input voltage is more than reference value.) specification of detection direction for comparator (low range) for a/d converter 1 after reset: 00h r/w address: fffff2e4h remark the reference value means the reference vo ltage input to the cref1l and cref1f pins.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 654 (21) comparator output digital noise eliminat ion register nl, nf (cmpnfcnl, cmpnfcnf) the cmpnfcnl and cmpnfcnf registers are control the digital noise elimi nation of the overvoltage detection comparator output. this register can be read or written in 8-bit units. reset sets this register to 00h. cmpnnfen cmpnnfen 0 1 note performs digital noise elimination setting of digital noise elimination cmpnfcnf (n = 0, 1) 0000 cmpnnfc2 cmpnnfc1 cmpnnfc0 after reset: 00h r/w address: cmpnfc0f fffff27ah, cmpnfc1f fffff27eh cmpnnfc2 0 0 0 0 1 1 cmpnnfc1 0 0 1 1 0 0 f xx /32 f xx /64 f xx /128 f xx /256 f xx /1024 f xx /4096 setting prohibited sampling clock selection others cmpnnfc0 0 1 0 1 0 1 cmpnnfen cmpnfcnl (n = 0, 1) 0000 cmpnnfc2 cmpnnfc1 cmpnnfc0 after reset: 00h r/w address: cmpnfc0l fffff278h, cmpnfc1l fffff27ch note when using the comparator output, be sure to set the cmpnnfen bit to 1 (digital noise eliminated). at the same time, a sampling clock must be selected. when not using the comparator out put, set the cmpnnfen bit to 0. caution be sure to set bits 3 to 6 to ?0?.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 655 (22) comparator output interrupt rising edge, fa lling edge specification registers (cmpor, cmpof) the cmpor and cmpof registers are registers that specify the trigger mode of the intcmp0l, intcmp0f, intcmp1l, and intcmp1f signals and can specify the valid edge independently for each interrupt request signal (rising edge, falling edge, or both rising and falling edges). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. 0 cmpof 0 0 0 cmpof1f cmpof1l cmpof0f cmpof0l after reset: 00h r/w address: fffff2f4h 0 cmpor 0 0 0 cmpor1fcmpor1l cmpor0f cmpor0l after reset: 00h r/w address: fffff2f6h remark for the valid edge specification, see tables 12-9 and 12-10 . table 12-9. valid edge specification of intcmp0f and intcmp1f signals cmpofnf cmpornf valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 0, 1 table 12-10. valid edge specification of intcmp0l and intcmp1l signals cmpofnl cmpornl valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 656 12.4 operation cautions 1. a/d converters 0 and 1 are capab le of simultaneous sampling of two circuits. 2. for details of operation setting, see 12.3 (1) a/d conver ter n scan mode register (adnscm). 12.4.1 basic operation a/d conversion is executed by the following procedure. (1) select an input clock (f ad01 ) by using the adnocks register and se t the adnocksen bit to 1 (enable supply of the operating clock to a/d converter n). (2) set adnscm.adnps bit = 1. (3) wait for 1 s or more after <2>. (4) select an analog input pin and operation mode, by using the adnscm note , adnctc, adnchen, adnctl0, adntsel, adnch1, adnch2, adlts1, and adlts2 registers (n = 0, 1). number of a/d c onversion clocks and a/d conversion time are determined by the specif ication of the adnctc.adnfr3 to adnctc.adnfr0 bits. note be sure to set bit 1 of the adnscm register to ?1?. this setting can be performed at the same time as other adnscm register bits. (5) in the a/d trigger mode and the a/d trigger pollin g mode, setting the adnscm.adnce bit to 1 starts a/d conversion (n = 0, 1). if the adnce bit is set to 1 in the hardware trigger mode, conversion channel specification mode, and extension buffer mode, t he a/d converter enters the trigger wait status. (6) when a/d conversion is started, the voltage input to the selected anal og input channel is sampled by the sample & hold circuit. when the operational amplifier for input level amplification is used, the gain specified by the opnctl0.opnga3 to opnctl0.opnga0 bits the input voltage is sampled. (7) when sampling has been performed for a specific ti me, the sample & hold circuit enters the hold status, and holds the input analog voltage until a/d conversion ends. (8) set bit 11 of the successive approximation register ( sar). the tap selector chan ges the level of the voltage tap of the array to the reference voltage (1/2av refpn ). (9) the voltage generated by the volt age tap of the array is compared with the analog input voltage by a comparator. if the analog input voltage is found to be greater than the reference voltage (1/2av refpn ) as a result of comparison, the most significant bit (msb) of the successive approximation register (sar) remains set. if the analog input voltage is less than the reference voltage (1/2av refpn ), the msb of the sar is reset.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 657 (10) next, bit 10 of the successive approximation register (sar) is automatically set, and the next comparison is started. the voltage tap of the array is selected according to the value of bit 11, to which the result has been already set. bit 11 = 0: (1/4av refpn ) bit 11 = 1: (3/4av refpn ) the voltage tap of the array and the analog input voltage are compared and bit 10 of the sar is manipulated according to the result of the comparison. analog input voltage voltage tap of array: bit 10 = 1 analog input voltage voltage tap of array: bit 10 = 0 comparison is continued like this to bit 0 of the sar. (11) when comparison of 12 bits has been completed, the va lid digital value result remains in the successive approximation register (sar). this value is transferred to a/dn conversion result register m (adncrm) and the conversion result is stored in this register in the a/d trigger mo de, a/d trigger polling mode, hardware trigger mode, and conversion channel specification mode (n = 0, 1, m = 0 to 15). the valid digital value is stored in the a/dn conversion result extension buffer register a in the ex tension buffer mode, and is shifted to a/dn conversion result extension regi ster a when selection load trigger x is generated and stored (x = 1, 2, a = 0 to 4). when a/d conversion has ended the specified number of times, an a/dn conversion end interrupt request signal (intadn) is generated.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 658 12.4.2 input voltage and conversion result the relationship between the analog voltage input to the analog input pin (anink ) and the a/d conversion result (of a/dn conversion result register m (adncrm) or a/dn c onversion result extension register a (adnecra)) is as follows: v in adcr = int ( av refp 4,096 + 0.5) or, av refp av refp (adcr ? 0.5) 4,096 v in < (adcr + 0.5) 4,096 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av refp : av refpn pin voltage adcr: value of a/dn conversion result register m (adncrm) or a/ dn conversion result extension register a (adnecra) the relationship between the analog input voltage a nd the a/d conversion result is shown below. remark a/d converter 0: n = 0, m = 0 to 15, k = 0 to 5, a = 0 to 4 a/d converter 1: n = 1, m = 0 to 15, k = 0 to 7, a = 0 to 4
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 659 figure 12-11. relationship between analog input voltage and a/d conversion results 4095 4094 4093 adcr adncrm, adnecra fff0h ffe0h ffd0h 0030h 0020h 0010h 0000h 3 2 1 0 input voltage/av refpn 1 8192 1 4096 3 8192 2 4096 5 8192 3 4096 8187 8192 4094 4096 8189 8192 4095 4096 8191 8192 1 a/d conversion results (adncrm, adnecra) remark a/d converter 0: n = 0, m = 0 to 15, k = 0 to 5, a = 0 to 4 a/d converter 1: n = 1, m = 0 to 15, k = 0 to 7, a = 0 to 4
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 660 12.4.3 operation mode various conversion operations can be specified for the a/ d converters 0 and 1 by spec ifying the operation mode. the operation mode is set by the adnscm, adnctc, ad nchen, adnctl0, adntsel, adnch1, adnch2, adlts1, adlts2, and adnocks registers. the following shows the relations hip between the operation modes. remark n = 0, 1 extension buffer mode normal operation mode a/d trigger mode extended operation mode conversion channel specification mode a/d trigger polling mode hardware trigger mode caution be sure to set the hardware trigger mode when the conversion chan nel specification mode or extension buffer mode is used. 12.4.4 operation setting start or stop the operation of a/d converters 0 and 1 in the following procedure. adnscm.adnce bit adnscm.adnps bit adnocks.adnocksen bit operation starts operation stops a/d initial setting 1 s or more
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 661 12.4.5 operation of 1-channel conversion the signal of one analog input pin (anink ) specified by the adnchen register is converted. the result of conversion is stored in the adncrk register corresponding to the anink pin. the anink pin and adncrk register correspond to each other on a one-to-one basis, and an a/dn conversion end interrupt request signal (intadn) is generated each time conversion has been completed. after completion of a/d conversion, the conversion oper ation is stopped in the a/d trigger mode or a/d trigger polling mode. in the hardware trigger mode , the a/d converter waits for a trigger. remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-12. operation of 1-channel conver sion (in a/d trigger mode): a/d converter 0 data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 5 (ani01) data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 5 (ani01) conversion start ad0ce bit set conversion start ad0ce bit set conversion end ad0ce bit clear conversion start ad0ce bit set conversion start ad0ce bit set conversion start ad0ce bit set conversion end ad0ce bit clear ad0cs bit ad0cr1 register a/d conversion ani01 (input) intad0 interrupt data 1 data 5 software processing data 2 data 3 data 4 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 ad0cr4 ad0cr5 a/d converter 0 ad0crn register analog input pin
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 662 12.4.6 operation of mult iple channel conversion the signals of two or more analog input pins (anink) sp ecified by the adnchen regi ster are converted. the signals are sequentially converted starti ng from the pin with the lowest number (i n the example in figure 12-13, ani00 ani02 ani03 ani05). an analog input pin that is not specified is skipped. t he result of conversion is stored in the adncrk register corresponding to the anink pin. the anink pin and adncrk register correspond to each other on a one-to-one basis. when conversi on of the signal of the s pecified analog input pins is completed, an a/dn conversion end interrupt request signal (intadn) is generated. after completion of a/d conversion, the conversion oper ation is stopped in the a/d trigger mode or a/d trigger polling mode. in the hardware trigger mode , the a/d converter waits for a trigger. remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 663 figure 12-13. operation of mult iple channel conversion (in a/d trigger mode): a/d converter 0 data 1 (ani00) data 2 (ani02) data 3 (ani03) data 4 (ani05) data 5 (ani00) data 1 (ani00) data 5 (ani00) data 6 (ani02) conversion start ad0ce bit set conversion start ad0ce bit set ad0cs bit ad0cr0 register a/d conversion ani00 (input) ani02 (input) ani03 (input) ani05 (input) intad0 interrupt data 2 (ani02) ad0cr2 register data 3 (ani03) ad0cr3 register data 4 (ani05) ad0cr5 register data 1 data 2 data 3 data 4 data 5 data 6 software processing ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 ad0cr4 ad0cr5 a/d converter 0 ad0crn register analog input pin
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 664 12.4.7 a/d trigger mode (normal operation mode) a/d conversion is started when the adnscm.adnce bit is set to 1. when conversion is started, the adnscm.adncs bit is set to 1 (conversion is in progress). if the adnscm register is written during a/d conversion, the conversion is stopped and start ed again from the beginning. (1) operation of 1-channel conversion the signal of one analog input pin (anink) is converted once and the result is stored in one adncrk register. the anink pin and adncrk register correspond to each other on a one-to-one basis. each time conversion has been completed, an a/dn c onversion end interrupt request signal (intadn) is generated. after a/d conversion is completed, the a/d converter st ops conversion operation with the adnscm.adnce bit remaining set to 1. the a/d conver sion can be restarted by setting the adnce bit to 1. this operation is suitable for an applic ation where the result of a/d co nversion should be read each time conversion has been completed once. analog input pin a/d conversion result register anink adncrk remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-14. example of 1-channel conversion operation (a/d trigger mode): a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0scm ad0cr4 ad0cr5 (1) ad0ce bit = 1 (enable) (4) ad0scm.ad0cs bit = 0 (2) signal of ani02 pin is a/d converted (5) intad0 interrupt request signal is generated (3) conversion result is stored in ad0cr2 register remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 000, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 0004h.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 665 (2) operation of mult iple channel conversion the signals of two or more analog input pins specifi ed by the adnchen register are converted sequentially starting from the pin with the lowest number. the result of conversion is stored in the adncrk register corresponding to the analog input pin. when conversion of the signals of all the s pecified analog input pins is completed, an a/dn conversion end interrupt request signal (intadn) is generated. after a/d conversion is completed, the a/d converter stops conversion operation with the adnscm.adnce bit remain ing set to 1. the a/d conversion can be restarted by setting the adnce bit to 1. this operation is suitable for an application where tw o or more analog input signals should be monitored. analog input pin a/d conversion result register anink note adncrk | | anink note adncrk note two or more can be specified by the adnchen register. however, a/d conversion is sequ entially executed starting from t he pin with the lowest number. remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-15. example of multiple channel conver sion operation (a/d trigger mode): a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0scm ad0cr4 ad0cr5 (1) ad0ce bit = 1 (enable) (6) signal of ani05 pin is a/d-converted (2) signal of ani01 pin is a/d-converted (7) conversion result is stored in ad0cr5 register (3) conversion result is stored in ad0cr1 register (8) ad0scm.ad0cs bit = 0 (4) signal of ani03 pin is a/d-converted (9) intad0 interrupt request signal is generated (5) conversion result is stored in ad0cr3 register remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 000, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 002ah.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 666 12.4.8 a/d trigger polling m ode (normal operation mode) a/d conversion is started when the adnscm.adnce bit is set to 1. when conversion is started, the adnscm.adncs bit is set to 1 (conversion is in progress). in the a/d trigger polling mode, it is not necessary to write 1 to the adnce bit to restart a/d conversion after the a/dn conversion end interrupt requ est signal (intadn) is generated. if the adnscm register is written during a/d conversion, the conversion is stopped and start ed again from the beginning. (1) operation of 1-channel conversion the signal of one analog input pin (anink) is converted once and the result is stored one adncrk register. the anink pin and adncrk register correspond to each other on a one-to-one basis. each time conversion has been completed, an a/dn c onversion end interrupt request signal (intadn) is generated. a/d conversion is repeated until the adnscm.adnce bit is set to 0. the conversion operation is stopped when the adnce bit is cleared to 0. it is not necessary to set the adnce bit to restart the conversion operation in the a/d trigger polling mode. this operation is suitable for an application w here the a/d conversion value is always read. analog input pin a/d conversion result register anink adncrk remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-16. example of 1-channel conversion oper ation (a/d trigger polling mode): a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0scm ad0cr4 ad0cr5 (1) ad0ce bit = 1 (enable) (5) intad0 interrupt request signal is generated (2) signal of ani02 pin is a/ d-converted (6) return to (2) (3) conversion result is stored in ad0cr2 r egister (7) set ad0ce bit to 0 to end (stop) (4) ad0scm.ad0cs bit = 0 remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 100, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 0004h.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 667 (2) operation of mult iple channel conversion the signals of two or more analog input pins specifi ed by the adnchen register are converted sequentially starting from the pin with the lowest number. the result of conversion is stored in the adncrk register corresponding to the analog input pin. when conversion of the signals of all the s pecified analog input pins is completed, an a/dn conversion end interrupt request signal (intadn) is generated. a/d conversion is repe ated until the adnscm.adnce bit is set to 0. the conversion operation is stop ped when the adnce bit is cleared to 0. it is not necessary to set the adnce bit to restart the conversion operation in the a/d trigger polling mode. this operation is suitable for an application w here the a/d conversion value is always read. analog input pin a/d conversion result register anink note adncrk | | anink note adncrk note two or more can be specified by the adnchen register. however, a/d conversion is sequ entially executed starting from t he pin with the lowest number. remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-17. example of multiple channel conversion operation (a/d trigger polling mode): a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0scm ad0cr4 ad0cr5 (1) ad0ce bit = 1 (enable) (7) conversion result is stored in ad0cr5 register (2) signal of ani01 pin is a/d-converted (8) ad0scm.ad0cs bit = 0 (3) conversion result is stored in ad0cr1 regist er (9) intad0 interrupt request signal is generated (4) signal of ani03 pin is a/d-converted (10) return to (2) (5) conversion result is stored in ad0cr3 register (11) set ad0ce bit to 0 to end (stop) (6) signal of ani05 pin is a/d-converted remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 100, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 002ah.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 668 12.4.9 hardware trigger m ode (normal operation mode) the a/d converter waits for a trigger when the adnscm.adn ce bit is set to 1, and starts a/d conversion when a trigger specified by the adntsel.adntrgse l11 and adntsel.adntrgsel10 bits is generated. when conversion is started, the adnscm.adncs bit is set to 1 (conversion is in progress). if the adnscm register is written duri ng a/d conversion, the conversion is st opped and becomes trigger wait status again. (1) operation of 1-channel conversion the signal of one analog input pin (anink) is co nverted once, using a signal specified by the adntsel.adntrgsel11 and adntsel.adntrgsel10 bits as a trigger, and the result of conversion is stored in one adncrk register. the anink pin and ad ncrk register correspond to each other on a one-to- one basis. each time conversion has been completed, an a/dn c onversion end interrupt request signal (intadn) is generated. after completing the conversion, the conver ter waits for the trigger with the adnscm.adnce bit set to 1. this operation is suitable for an applic ation where the result of a/d co nversion should be read each time conversion by one trigger has been completed. analog input pin a/d conversion result register anink adncrk remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-18. example of 1-channel conversion oper ation (hardware trigger mode): a/d converter 0 ani00 ani01 ani02 ani03 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 trigger specified by ad0tsel.ad0trgsel11 and ad0tsel.ad0trgsel10 bits ani04 ani05 ad0cr4 ad0cr5 (1) ad0ce bit = 1 (enable) (5) ad0scm.ad0cs bit = 0 (2) trigger specified by ad0tsel.ad0trgsel11 (6) intad0 interrupt request signal is generated and ad0tsel.ad0trgsel10 bits is generated (7) returns to (3) when the next trigger is input (3) signal of ani01 pin is a/d-converte d (8) set ad0ce bit to 0 to end (stop) (4) conversion result is stored in ad0cr1 register remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 001, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 0002h.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 669 (2) operation of mult iple channel conversion the signals of two or more analog input pins specifie d by the adnchen register are sequentially converted, starting from the pin with the lowe st number, using a signal specifi ed by the adntsel.adntrgsel11 and adntsel.adntrgsel10 bits as a trigger. the result of conversion is stored in the adncrk register corresponding to the analog input pin. when conversion of the signals of all the s pecified analog input pins is completed, an a/dn conversion end interrupt request signal (intadn) is generated. after comp letion of conversion, the a/d converter waits for the trigger with the adnscm.adnce bit remaining set to 1. this operation is suitable for an app lication where two or more analog in put signals should be monitored when the trigger is generated. analog input pin a/d conversion result register anink note adncrk | | anink note adncrk note two or more can be specified by the adnchen register. however, a/d conversion is sequ entially executed starting from t he pin with the lowest number. remark a/d converter 0: n = 0, k = 0 to 5 a/d converter 1: n = 1, k = 0 to 7 figure 12-19. example of multiple channel conversi on operation (hardware trigger mode): a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0cr4 ad0cr5 trigger specified by ad0tsel.ad0trgsel11 and ad0tsel.ad0trgsel10 bits (1) ad0ce bit = 1 (enable) (7) signal of ani05 pin is a/d-converted (2) trigger specified by ad0tsel.ad0trgsel11 (8) conversion result is stored in ad0cr5 register and ad0tsel.ad0trgsel10 bits is generated (9) ad0scm.ad0cs bit = 0 (3) signal of ani01 pin is a/d-converted (10) intad0 interrupt request signal is generated (4) conversion result is stored in ad0cr1 register (11) returns to (3) when the next trigger is input (5) signal of ani03 pin is a/d-converted (12) set ad0ce bit to 0 to end (stop) (6) conversion result is stored in ad0cr3 register remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 001, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 00, and ad0chen register = 002ah.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 670 12.4.10 conversion channel specificat ion mode (extension operation mode) when the adnscm.adnce bit is set to 1, the a/d converter waits for a trigger. when selection trigger 1 specified by the adntsel.adntrgsel11 and adntsel.adntrgsel10 bits is generated, the converter starts a/d conversion. when conversion is started, the adnscm.adncs bit is set to 1 (conversion is in progress). if the adnscm register is written during a/d conversion operat ion, the conversion is stopped and the converter waits for the trigger again. the analog input pin is spec ified by the adnch1.adntrgc h12 to adnch1.adntrgch10 and adnch1.adntrgch16 to adnch1.adntrgch14 bits. each time selection trigger 1 is generated, the analog input pins specified by the adnch1.adntrgch12 to adnch1.adntrgch10 and adnch1.adntrgch16 to adnch1.adntrgch14 bits are sequentially selected. the signal of a specified analog input pin is converted the number of times s pecified by the adnchen register (up to 16 times), using selection trigger 1 as the trigger, and the result is stored in the adncrm register specified by the adnchen register. the conversion result s are sequentially stored from adncr0. when the signal of the specified ana log input pin has been converted the number of times (up to 16 times) specified by the adnchen register, an a/dn conversion end interrupt request signal (intadn) is generated. after a/d conversion is completed, the a/d converter waits for the trigger with the adnscm.adnce bit remaining set to 1. this operation is suitable for an application where tw o or more analog input signals should be monitored. selection trigger analog input pin a/d conversion result extension register aninx note 1 adncr0 note 3 aninx note 1 | selection trigger 1 aninx note 1 adncrm note 3 aniny note 2 adncr0 note 3 aniny note 2 | selection trigger 2 aniny note 2 adncrm note 3 notes 1. set by adnch1.adntrgch12 to adnch1.adntrgch10 bits 2. set by adnch1.adntrgch16 to adnch1.adntrgch14 bits 3. two or more times can be set by the adnchen register. cautions 1. be sure to set the hardware trigger mode as the c onversion channel specification mode. 2. be sure to set the adnchen register using th e lower bits, justifying to the bottom. any other setting is prohibited. 3. setting of the adnch2 register is invalid. 4. the adnecra, adnecrah, adnflg, and adnflgb registers are not used . if these registers are read, 0000h and 00h are read. 5. selection trigger 1 is ignored if it is generated during a/d conver sion operation. the next selection trigger 1 is accepted when a tri gger is generated afte r completion of a/d conversion (after generation of the intadn signal). remark a/d converter 0: n = 0, k = 0 to 5, m = 0 to 15 a/d converter 1: n = 1, k = 0 to 7, m = 0 to 15
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 671 figure 12-20. example of operation in conver sion channel specification mode: a/d converter 0 001 001 001 001 selection trigger 1 intad0 signal ad0cr0 register ad0cr1 register ad0cr2 register ad0cr3 register analog input pin selection a/d conversion result signals 11 to 0 ad0trgch12 to ad0trgch10 bits ad0trgch16 to ad0trgch14 bits ani00 ani01 ani02 ani03 ani04 ani05 ad0cr0 ad0cr1 ad0cr2 ad0cr3 a/d converter 0 ad0cr4 ad0cr5 trigger specified by ad0tsel.ad0trgsel11 and ad0tsel.ad0trgsel10 bits ( 4) ... ad0cr14 ad0cr15 (1) ad0ce bit = 1 (enable) (8) conversion result is stored in ad0cr2 register (2) trigger specified by ad0tsel.ad0trgsel11 (9) signal of ani01 pin is a/d-converted and ad0tsel.ad0trgsel10 bits is generated (10) c onversion result is stored in ad0cr3 register (3) signal of ani01 pin is a/d-converted (11) ad0scm.ad0cs bit = 0 (4) conversion result is stored in ad0cr0 regist er (12) intad0 interrupt request signal is generated (5) signal of ani01 pin is a/d-converted (13) returns to (3) when the next trigger is input (6) conversion result is stored in ad0cr1 register (14) set ad0ce bit to 0 to end (stop) (7) signal of ani01 pin is a/d-converted remark this is an operation example when the ad0scm .ad0plm, ad0trg1, and ad0trg0 bits = 001, ad0ctl0.ad0md1 and ad0ctl0.ad0md0 bi ts = 10, ad0chen register = 000fh, ad0ch1.ad0trgch12 to ad0ch1.ad0trgch10 bits = 001, and ad0ch1.ad0trgch16 to ad0ch1.ad0trgch14 bits = 001.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 672 12.4.11 extension buffer mode (extension operation mode) when the adnscm.adnce bit is set to 1, the a/d converter waits for a trigger. when selection trigger 1 specified by the adntsel.adntrgsel11 and adntsel.adntrgsel10 bi ts or selection trigger 2 specified by the adntsel.adntrgsel21 and adntsel.adntrgsel20 bits is generated, the converter starts a/d conversion. when conversion is started, the adnscm.adncs bit is set to 1 (conversion is in progress). if the adnscm register is written during a/d conversion operat ion, the conversion is stopped and the converter waits for the trigger again. the analog input pin for selection trigger x is spec ified by the adnchx.adntrgchx2 to adnchx.adntrgchx0 and adnchx.adntrgchx6 to adnchx.adntrgchx4 bits. each time selection trigger x is generated, the analog input pins specified by the adnchx.adntrgchx2 to adnchx.adntrgchx0 and adnchx.adntrgchx6 to adnchx.adntrgchx4 bits are sequentially selected. when selection trigger 1 is used, the signal of t he analog input pin specified by the adntrgch12 to adntrgch10 bits is converted when the trigger is generated for the first ti me. the result is stored in the a/dn conversion result extension buffer register 0 and an a/ dn conversion end interrupt request signal (intadn) is generated. when the trigger is generated the second time, the signal of the analog input pin specified by the adntrgch16 to adntrgch14 bits is conver ted. the result is st ored in the a/dn conversion result extension buffer register 0 and, at the same time, the first value stored in the a/dn conversion result extension buffer register 0 is stored in the a/dn conversion result extension buffer register 1. then t he intadn interrupt request signal is generated. for a/d conversion using select ion trigger 1, up to three a/dn conver sion result extension buffer registers, 0 to 2, can be used. when selection load trigger 1 is later generated, the values of the a/dn conversion result extension buffer registers 0 to 2 are tr ansferred to the adnecr0 to adnecr2 r egisters. after a/d conversion is competed, the converter waits for the trigger wit h the adnscm.adnce bit remaining set to 1. when selection trigger 2 is used, the signal of t he analog input pin specified by the adntrgch22 to adntrgch20 bits is converted when the trigger is generated for the first time, and the result is st ored in the a/dn conversion end extension buffer register 3. then an a/dn conversion end in terrupt request signal (intadn) is generated. when the trigger is generated the second time, the signal of the analog input pin specified by the adntrgch26 to adntrgch24 bits is conv erted and the result is stored in t he a/dn conversion result extension buffer register 4. at the same time, the value stored first in the a/dn conversion result extension buffer register 3 is stored in the a/dn conversion result ex tension buffer register 4, and the intadn interrupt request signal is generated. when selection trigger 2 is used for a/d conversion, up to tw o a/dn conversion result ext ension buffer registers, 3 and 4, can be used. when selection load tr igger 2 is generated again, the values of the a/dn conversion result extension buffer registers 3 and 4 are transferred to and stored in the adnecr3 and adnecr4 registers. after a/d conversion is completed, the converter waits for the tr igger with the adnce bit remaining set to 1. therefore, the contents of the adnecr0 to adnecr4 register s can be saved to ram all at once. this operation is suitable for an application where there is little time to save the conversion result and two or more analog input signals should be monitored when a trigger is generated. selection trigger analog input pin a/d conversion result extension register selection trigger 1 aninx note 1 adnecr0 to adnecr2 selection trigger 1 aniny note 2 adnecr0, adnecr1 selection trigger 1 aninx note 1 adnecr0 selection trigger 2 anins note 3 adnecr3, adnecr4 selection trigger 2 anint note 4 adnecr3 notes 1. set by adnch1.adntrgch12 to adnch1.adntrgch10 bits 2. set by adnch1.adntrgch16 to adnch1.adntrgch14 bits 3. set by adnch2.adntrgch22 to adnch2.adntrgch20 bits 4. set by adnch2.adntrgch26 to adnch2.adntrgch24 bits
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 673 cautions 1. in the extension buffer mode, be sure to set the hardware trigger mode and the adnchen register to 0001h. 2. the conversion result is stored in the ad necra register. the value of the adncrm register is undefined. remark n = 0, 1 figure 12-21. block diagram in extension buffer mode adnmd1, adnmd0 bits adnmd1, adnmd0 bits adntrgsel21, adntrgsel20 bits adntrgsel11, adntrgsel10 bits itrg2 itrg1 selection trigger 1 selection trigger 2 ldtrg1 ldtrg2 itrg3 itrg4 adnecr0 adnecr1 adnecr2 buffer register 0 adnecr3 buffer register 3 buffer register 1 adnecr4 buffer register 4 buffer register 2 edge detector edge detector edge detector edge detector a/d converter n trigger selection error detection adntrgch12 to adntrgch10 bits adntrgch16 to adntrgch14 bits selector adntrgch22 to adntrgch20 bits adntrgch26 to adntrgch24 bits selection load trigger 1 conversion trigger selection signal selection load trigger 2 a/d conversion result signals 11 to 0 a/d conversion end signal selecting analog input pin in normal operation mode selecting analog input pin selector selector selector selector selector selector selector remarks 1. buffer registers 0 to 4: a/dn conversion result extension buffer registers 0 to 4 2. n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 674 figure 12-22. example of operation in ex tension buffer mode: a/d converter 0 (1/2) selection trigger 1 (2) (24) (3) (8) (4) (6) (11) (17) (23) (32) (38) (9) (15) (14) (21) (20) (20) (25) (25) (25) (40) (40) (36) (35) (35) (30) (29) (13) (34) (28) (19) (39) (27) (7) (12) (18) (33) selection trigger 2 selection load trigger 1 intad0 signal selection load trigger 2 ad0ecr0 register ad0ecr1 register ad0ecr2 register ad0ecr3 register ad0ecr4 register buffer register 0 buffer register 1 buffer register 2 buffer register 3 buffer register 4 ani02 ani00 ani05 ani02 ani03 r0 r1 r2 r3 r2 r1 r0 r4 r0 r3 r2 r1 r4 r0 r1 r1 r5 r3 r2 r2 r3 r4 r5 ani00 ani05 ani05 ani00 ani03 analog input pin selection a/d conversion result signals 11 to 0 ad0trgch12 to ad0trgch10 bits ad0trgch16 to ad0trgch14 bits ad0trgch22 to ad0trgch20 bits ad0trgch26 to ad0trgch24 bits remarks 1. buffer registers 0 to 4: a/dn conversion result extension buffer registers 0 to 4 2. r0 to r6: conversion result 3. n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 675 figure 12-22. example of operation in ex tension buffer mode: a/d converter 0 (2/2) (1) ad0ce bit = 1 (enable) (24) selection load trigger 1 is generated (2) selection trigger 2 is generated (25) sh ifted from buffer registers 0 to 2, to (3) signal of ani02 pin is a/d-converted ad0ecr0 to ad0ecr2 (4) conversion result is stored in buffer register 3 (26) ad0scm.ad0cs bit = 0 (5) ad0scm.ad0cs bit = 0 (27) selection trigger 2 is generated (6) intad0 interrupt request signal is generated (28) signal of ani03 pin is a/d-converted (7) selection trigger 1 is generated (29) shift ed from buffer register 3 to buffer register 4 (8) signal of ani00 pin is a/d-converted (30) c onversion result is stored in buffer register 3 (9) conversion result is stored in buffer register 0 (31) ad0scm.ad0cs bit = 0 (10) ad0scm.ad0cs bit = 0 (32) intad0 interrupt request signal is generated (11) intad0 interrupt request signal is gener ated (33) selection trigger 1 is generated (12) selection trigger 1 is generated (34) signal of ani05 pin is a/d-converted (13) signal of ani05 pin is a/d-converted (35) shi fted from buffer register 0 to buffer register 1 to (14) shifted from buffer register 0 to buffer register 1 buffer register 2 (15) conversion result is stored in buffer register 0 (36) conversion result is stored in buffer register 0 (16) ad0scm.ad0cs bit = 0 (37) ad0scm.ad0cs bit = 0 (17) intad0 interrupt request signal is generated (38) intad0 interrupt request signal is generated (18) selection trigger 1 is generated ( 39) selection load trigger 2 is generated (19) signal of ani00 pin is a/d-converted ( 40) shifted from buffer registers 3 and 4 to (20) shifted from buffer register 0 to buffe r register 1 ad0ecr3 and ad0ecr4 registers to buffer register 2 (41) ad0scm.ad0cs bit = 0 (21) conversion result is stored in buffer register 0 (42) when the next trigger is input, the operation is (22) ad0scm.ad0cs bit = 0 performed in accordance with that trigger. (23) intad0 interrupt request signal is generated (43) set adnce bit to 0 to end (stop)
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 676 (1) error detection function the extension buffer mode has an error det ection function. if a trigger (selec tion trigger 1, selection trigger 2, selection load trigger 1, or selecti on load trigger 2) is generated during a/d conversion, an error occurs. the error is detected by the adnflg.adnterr2 and adnflg.adnterr1 flags, and adnflgb.adnterrb2 and adnflgb.adnterrb1 flags. cautions 1. selection trigger 1, selection trigger 2, selection load trigger 1, and selection load trigger 2 are generated when asynch ronous signals itrg1 to it rg4, ldtrg1, and ldtrg2 signals are synchronized. alt hough the timing of inputting th ese triggers seems to be the same, their simultane ous operation is not guaranteed because the asynch ronous signals are synchronized. 2. selection trigger 1 or 2 is ignored, even if it is generated again, during a period of up to 2.5 basic clocks (f ad01 ) after the trigger is once ge nerated (no error occurs). (a) error detection by generation of select ion trigger 1 or 2 during a/d conversion if selection trigger 1 is generated during a/d conversion, the adnflgb.adnterrb1 flag is set to 1 and a/d conversion by selection trigger 1 is ignored. if selection load trigger 1 is generated next, the value of the adnterrb1 flag is stored in the adnflg.adnterr1 flag. similarly, if selection trigger 2 is generated during a/d conversion, the adnflg b.adnterrb2 flag is set to 1 and a/d conversion by selection trigger 2 is ignor ed. when selection load trigger 2 is generated next, the value of the adnterrb2 flag is stored in the adnflg.adnterr2 flag. selection trigger 1 selection trigger 2 selection load trigger 1 selection load trigger 2 adncs flag terrb1 flag terrb2 flag terr1 flag terr2 flag
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 677 (b) error detection by generation of selecti on load trigger 1 or 2 during a/d conversion if selection load trigger 1 is generated during a/d c onversion that uses selection trigger 1, the adnflg.adnterr1 flag is set to 1. a/d conversion and load operation are performed normally. similarly, if selection load trigger 2 is generated duri ng a/d conversion that uses selection trigger 2, the adnterr2 flag is set to 1. a/d conver sion and load operation are performed normally. selection trigger 1 selection trigger 2 selection load trigger 1 selection load trigger 2 adncs flag terrb1 flag l l terrb2 flag terr1 flag terr2 flag (c) error detection by simultaneous generation of selection triggers 1 and 2, and of selection triggers 1 and 2, and selection load triggers 1 and 2 if selection triggers 1 and 2 are simultaneously generated , a/d conversion that uses selection trigger 1 is started and selection trigger 2 is ignored. therefore, the adnflgb.adnterrb2 flag is set to 1. if selection triggers 1 and 2, and selection load tr iggers 1 and 2 are simultaneously generated, the adnflgb.adnterrb2, adnflg.adnterr1, and ad nflg.adnterr2 flags are set to 1. a/d conversion by selection trigger 1 and load operation of selection load triggers 1 and 2 are performed normally. selection trigger 2 is ignored. selection trigger 1 selection trigger 2 selection load trigger 1 selection load trigger 2 adncs flag terrb1 flag l terrb2 flag terr1 flag terr2 flag
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 678 12.5 internal equivalent circuit the following figure shows the equivalent circuit of the analog input block. aninm c 1 c 2 r r c 1 c 2 5.1 k 15 pf 3.9 pf remarks 1. the maximum values are shown (reference values). 2. m = 0 to 5 when n = 0 m = 0 to 7 when n = 1 adnctc register adnfr3 bit adnfr2 bit adnfr1 bit adnfr0 bit number of a/d conversion clocks (f ad01 ) number of sampling clocks 0 0 0 0 89 69.5 0 0 0 1 88 68.5 0 0 1 0 57 37.5 0 0 1 1 56 36.5 0 1 0 0 41 21.5 0 1 0 1 40 20.5 0 1 1 0 35 15.5 0 1 1 1 34 14.5 1 0 0 0 34 14.5 1 0 0 1 33 13.5 1 0 1 0 33 13.5 1 0 1 1 32 12.5 1 1 0 0 32 12.5 1 1 0 1 31 11.5 1 1 1 0 31 11.5 1 1 1 1 30 10.5 caution number of sampling clocks is included in numbe r of a/d conversion clocks. number of a/d conversion clocks (a/d conversion time) sampling clock conversion start conversion end
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 679 an example of calculating an overall error of a/d converters 0 and 1 is shown below. aninm v850e/if3, v850e/ig3 c 1 c 2 r v ain c 0 r i f xx (mhz) a/d conversion time ( s) sampling ( s) r (k ) c 1 (pf) c 2 (pf) c 0 (pf) r i (k ) sampling error (lsb) note 100 1.0 364.8 100 0.5 30.4 100 0.25 0.1 or lower 100 0.125 0.1 or lower 50 1.0 62.4 50 0.5 0.8 50 0.25 0.1 or lower 64 2.00 (32/f ad01 ) 0.78 (12.5/f ad01 ) 5.1 15 3.9 50 0.125 0.1 or lower note the error when considering the signal source impedance is ?sampling error + overall error?. remarks 1. these values are reference values calculated by simulating what happens to c 2 voltage by r i and c 0 when v ain is applied from 0 v to 5 v at the same time as sampling start. 2. m = 0 to 5 when n = 0 m = 0 to 7 when n = 1 3. f xx : system clock frequency f ad01 : basic clock frequency
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 680 12.6 cautions 12.6.1 stopping conversion operation the ongoing conversion operation is st opped when 0 is written to the adnscm.adnce bit. at this time, the conversion result in the a/dn conversi on result register m (adncrm) and a/dn conversion result extension register a (adnecra) is undefined. therefore, read the a/d conver sion result after a/d conversion has been completed (after the a/dn conversion end interrupt r equest signal (intadn) has been issued), and then write 0 to the adnce bit as necessary. note that the adnce bit is not cleared to 0 in a ll the modes even after the intadn signal is generated. remark n = 0, 1 m = 0 to 15 12.6.2 interval of trigger during conversion operation in hardware trigger mode, conversion channel specification mode, and extension buffer mode inputting a trigger during conversion operation is ig nored in the hardware trigger mode, conversion channel specification mode, and extension buffer mode. therefore, the interval of t he trigger (input time) in the hardware trigger mode, conversion channel specification mode, and extension buffer mode must be longer than the a/d conversion time specified by the adnctc.adnfr3 to adnctc.adnfr0 bits (see table 12-2 number of a/d conversion clocks and a/d conversion time ). remark n = 0, 1 12.6.3 writing to adnscm register (1) restarting a/d conversion to restart a/d conversion, write the same value to t he adnscm register. to c hange the adnplm, adntrg1, and adntrg0 bits, be sure to set the adnce bit to 0. (2) contention between end of a/d con version and writing to adnscm register if completion of a/d conversion contends with writing to the adnscm register duri ng a/d conversion operation, the conversion result is correctly stored in the adncrm and adnecra registers, if the a/dn conversion end interrupt request signal (intadn) is generated. if t he intadn signal is not gen erated, the a/d conversion operation is aborted. t herefore, the previous conversion resu lt is held by the adncrm and adnecra registers. (3) successive writing to adnscm register to successively write the adnscm register when the conversion operation is enabled (adnce bit = 1), be sure to wait for time of at least 5 basic clocks (f ad01 ). the adnscm register can be successively written when the adnce bit is set to 1 afte r the adnscm register is written while the adnce bit = 0. remark n = 0, 1 12.6.4 a/d conversi on start timing in the conversion channel specification mode and extens ion buffer mode, starting a/d conversion is delayed up to 1.5 basic clocks (f ad01 ) as compared with the normal operation mode.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 681 12.6.5 operation in standby mode (1) halt mode the a/d conversion operation continues. if the halt mode is releas ed by a maskable interrupt request signal that is not masked, the valu es of the adnscm, adncrm, and adnecra registers are held. (2) idle mode and stop mode no conversion operation is performed because clo ck supply to a/d converters 0 and 1 is stopped. be sure to set the adnscm.adnce bit to 0 when the idle or stop mode is set. at this time, setting the a/d power save mode (adnscm.adnps bit = 0) is recommended. remark n = 0, 1 m = 0 to 15 12.6.6 timing of accepting trigger in conversion channel specificati on mode and extension buffer mode in the conversion channel specification mode and extension buffe r mode, selection trigger 1 or 2 is ignored, even if it is generated again, until the a/dn c onversion end interrupt signal (intadn) is generated after a/d conversion is started by the first generation of selection trigger 1 or 2. in the extension buffer mode, the error flag is set to 1 in accordance with a specified error condition if selection trigger 1 or 2, or sele ction load trigger 1 or 2 is generated during this period (except, however, the case in caution 2 in 12.4.11 (1) error detection function ). remark n = 0, 1 12.6.7 variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of t he supply voltage, or may be affected by noise. to reduce the variation, take counteractive me asures with the program, such as by averaging the a/d conversion results. 12.6.8 a/d conversion result hysteresis characteristics successive comparison type a/d converters hold an analog input voltage in an internal sample & hold capacitor and then perform a/d conversion. after the a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the follo wing phenomena may occur if t he output impedance from the analog input source is too high. ? when the same channel is used for a/d conversions, if the voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear w here the conversion result is affected by the previous value. even if the conversion were to be performed at the same potential, the results may thus vary. ? when switching the analog input channel , hysteresis characteristics may appear where the conversion result is affected by the previous channel value. this is bec ause one a/d converter is used for the a/d conversions. even if the conversion were to be performed at t he same potential, the results may thus vary. to obtain more accurate conversion results, lower the output impedance from the analog input source or execute a/d conversion twice consecutively on the same channel, and discard the first conversion result.
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 682 12.6.9 a/d conversion trigger inte rval for continuous conversion for the a/d conversion trigger interval for continuous conv ersion, secure at least the minimum trigger interval shown below before inputting the next trigger. other wise, the trigger will be invalid (not retained). minimum trigger interval clock count = a/d conversion clock count + 5 clocks minimum trigger interval time = mi nimum trigger interval clock count 1/f ad01 example f ad01 = 16 mhz, a/d conversion time = 2 s, a/d conversion clock count = 32 clocks minimum trigger interval clock count = 32 + 5 = 37 minimum trigger interval timer = 37 1/16 = 2.3125 [ s] a/d conversion trigger a/d conversion trigger interval a/d conversion trigger interval intadn signal 5 clocks (5 1/f ad01 ) 5 clocks (5 1/f ad01 ) remark n = 0, 1
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 683 12.7 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltag e that can be identified. that is , the percentage of the analog input voltage per bit of digital output is called 1 lsb (least significant bit). the percentage of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av refpn ? 0)/100 = av refpn /100 1 lsb is as follows when the resolution is 12 bits. 1 lsb = 1/2 12 = 1/4,096 = 0.024%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 12-23. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av refpn analog input digital output
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 684 (3) quantization error when analog values are converted to digital values, a 1/2 lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2 lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the over all error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 12-24. quan tization error quantization error 1 ...... 1 0 ...... 0 0av refpn analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this shows the difference between the actual meas urement value of the a nalog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 12-25. zero-scale error av refpn analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 685 (5) full-scale error this shows the difference between the actual meas urement value of the a nalog input voltage and the theoretical value (full-scale value ? 3/2 lsb) when the digital output changes from 1??110 to 1??111. figure 12-26. full-scale error av refpn analog input (lsb) digital output (lower 3 bits) 111 av refpn ? 3 0 av refpn ? 2av refpn ? 1 100 011 010 000 full-scale error (6) differential linearity error while the ideal width of code output is 1 lsb, this indicates the difference between the actual measurement value and the ideal value. this indicates the basic characteristics of the a/d c onversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ssn to av refpn . see 12.7 (2) overall error for when the input voltage is increased or decreased, or when two or more channels are used. figure 12-27. differential linearity error ideal 1 lsb width differential linearity error 1 ...... 1 0 ...... 0 av refpn analog input digital output
chapter 12 a/d converters 0 and 1 user?s manual u18279ej3v0ud 686 (7) integral linearity error this shows the degree to which the conversion characteri stics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 12-28. integral linearity error 1 ...... 1 0 ...... 0 0av refpn analog input digital output ideal line integral linearity error (8) conversion time this expresses the time from when the trigger is generated to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on fo r the analog voltage to be sampled by the sample & hold circuit. figure 12-29. sampling time sampling time conversion time
user?s manual u18279ej3v0ud 687 chapter 13 a/d converter 2 13.1 features ? on-chip 10-bit resolution a/d converter ? analog input v850e/if3: ani20 to ani23 (4 channels) v850e/ig3: ani20 to ani27 (8 channels) ? a/d conversion result register v850e/if3: ad2cr0 to ad2cr3 (10 bits 4) v850e/ig3: ad2cr0 to ad2cr7 (10 bits 8) ? a/d conversion trigger mode software trigger mode ? a/d conversion operation mode continuous select mode continuous scan mode one-shot select mode one-shot scan mode ? successive comparison approximation method ? operating voltage: ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av dd2 = 4.0 to 5.5 v
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 688 13.2 configuration the block diagram is shown below. figure 13-1. block diag ram of a/d converter 2 av dd2 av ss2 intad2 ad2ps ad2md1 ad2md0 ad2ef ad2s2 ad2s1 ad2s0 ad2ce sample & hold circuit voltage comparator controller a/d2 conversion result register n (ad2crn/ad2crnh) ad2s ad2m0 ad2m1 ad2fr1 ad2fr0 ad2fr3 ad2fr2 internal bus successive approximation register (sar) selector counter d/a converter ani20 ani21 ani22 ani23 ani24 note ani25 note ani26 note ani27 note remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 note v850e/ig3 only
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 689 cautions 1. if there is noise at the analog i nput pin (ani2n) and at the a/d converter power supply voltage pin (av dd2 ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions succe ssively and use those re sults, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judg ed to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 2. do not apply a voltage outside the av ss2 to av dd2 range to the pins that are used as input pins of a/d converter 2.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 690 a/d converter 2 consists of the following hardware. table 13-1. configuration of a/d converter 2 item configuration analog input v850e/if3: ani20 to ani23 (4 channels) v850e/ig3: ani20 to ani27 (8 channels) registers successive appro ximation register (sar) v850e/if3: a/d2 conversion result registers 0 to 3 (ad2cr0 to ad2cr3) a/d2 conversion result registers 0h to 3h (ad2 cr0h to ad2cr3h): only the higher 8 bits can be read v850e/ig3: a/d2 conversion result registers 0 to 7 (ad2cr0 to ad2cr7) a/d2 conversion result registers 0h to 7h (ad2 cr0h to ad2cr7h): only the higher 8 bits can be read control registers a/d converter 2 mode registers 0, 1 (ad2m0, ad2m1) a/d converter 2 channel specification register (ad2s) (1) successive approximation register (sar) the sar register is a register that compares the voltage value of an analog input pin with the value of the voltage tap of the d/a converter and holds the resul t, starting from the most significant bit (msb). if data is held in the sar all the way to the least signif icant bit (lsb) (end of a/d conversion), the contents of the sar register are transferred in ad2crn register. when all the specified a/d conversion operations have ended, an a/d2 c onversion end interrupt request signal (intad2) is generated. (2) a/d conversion result register n (ad2crn), a/d conversion result register nh (ad2crnh) the ad2crn register is a register that holds the a/d conversion results. t he conversion result is stored in the higher 10 bits of the ad2crn register corresponding to the analog input. the lower 6 bits of these registers are always 0 when read. the higher 8 bits of the result of a/d c onversion are read from the ad2crn register. to read the result of a/d conversion in 16-bit units, s pecify the ad2crn register. to read the higher 8 bits, specify the ad2crnh register. caution the contents of the ad2crn register ma y become undefined depending on the operation to write the ad2m0, ad2m1, and ad2s registers. read the result of conversion from the ad2crn register after conversion and before writing the ad2m0, ad2m1, and ad2s registers. the correct conversion result cannot be read from the ad2crn register if any other procedure is used. (3) sample & hold circuit the sample & hold circuit samples the analog input signal s selected by the input circuit and sends the sampled data to the voltage comparator. this circuit holds t he sampled analog input voltage during a/d conversion. (4) voltage comparator the voltage comparator compares t he value that is sampled and held with the voltage ge nerated from the voltage tap of t he d/a converter.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 691 (5) d/a converter the d/a converter is connected between av dd2 and av ss2 and generates a voltage to be compared with an input analog signal. (6) ani2n pin the ani2n pin is an analog input pin fo r a/d converter 2. this pin inputs the analog signals to be a/d converted. pins other than the one t hat is selected by the ad2s regist er as analog signal input pins can be used as input port pins. cautions 1. make sure that the vo ltages input to the ani2n pin do not exceed the rated values. if a voltage higher than or equal to av dd2 or lower than or equal to av ss2 is input to a channel, the conversion value of the channel is undefi ned, and the conversi on values of the other channels may also be affected. 2. the analog input pin (ani2n) is alternately used as input port pin (p7n). if an instruction to input a signal to port 7 is executed durin g conversion when one of ani2n is selected for a/d conversion, the resolu tion for conversion may drop. (7) av dd2 pin the av dd2 pin alternately functions as the pin for inputting the positive power supply and reference voltage of a/d converter 2. this pin converts signals input to the ani2n pin to digital signals based on the voltage applied between av dd2 and av ss2 . always make the potential at this pin the same as that at the ev dd0 , ev dd1 , and ev dd2 pins (v850e/ig3 only) even when a/d converter 2 is not used. the operating voltag e range of the av dd2 pin is ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av dd2 = 4.0 to 5.5 v. (8) av ss2 pin this is the ground pin of a/d converter 2. always make the potential at this pin t he same as that at the ev ss0 , ev ss1 , and ev ss2 (v850e/ig3 only) pins even when a/d converter 2 is not used. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 13.3 control registers a/d converter 2 is controlled by the following registers. ? a/d converter 2 mode registers 0, 1 (ad2m0 to ad2m1) ? a/d converter 2 channel spec ification register (ad2s) the following registers are also used. ? a/d2 conversion result register n (ad2crn) ? a/d2 conversion result register nh (ad2crnh)
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 692 (1) a/d converter 2 mode register 0 (ad2m0) the ad2m0 register is a register that specifies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read-only. reset sets this register to 00h. ad2ce ad2ce 0 1 conversion operation stopped conversion operation enabled control of a/d conversion operation ad2m0 ad2ps ad2md1 ad2md0 0 0 0 ad2ef ad2ps 0 1 a/d power off a/d power on a/d conversion control ad2ef 0 1 during a/d conversion stop during a/d conversion operation status of a/d converter 2 (status) ad2md1 0 0 1 1 ad2md0 0 1 0 1 successive select mode successive scan mode one-shot select mode one-shot scan mode specification of operation mode after reset: 00h r/w address: fffffb80h ? the first result of conversion by the a/d converter 2 becomes valid when the ad2ce bit is set to 1 (when conversion is enabled) at least 2 s after the ad2ps bit is set to 1 (a/d power is turned on). if the ad2ce bit is set to 1 before 2 s pass, the conversion operation is started and ends after the a/d conversion time, but the conversion result is undefined. ? when the a/d converter 2 is not used, set to 0 the ad2ce bit (stop conversion operation) and the ad2ps bit (turn off a/d power) to reduce the power consumption. ? do not set the ad2ps2 bit during a/d conversion operation (ad2ef bit = 1). while the a/d conversion operation is not performed, the ad2ce and ad2ps bits can be simultaneously cleared to 0. <7> 6 5 4 3 2 1 0 cautions 1. writing to bit 0 is ignored. 2. the conversion resolution of the pin to which an analog signal is input first immediately after a/d conversion is started may dr op. for details, see 13.7 (6) about av dd2 pin. 3. a/d conversion is stopped and started ag ain from the beginning if the ad2m0 and ad2s registers are written during a/d con version operation (ad2ef bit = 1). 4. be sure to set bits 1 to 3 to ?0?.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 693 (2) a/d converter 2 mode register 1 (ad2m1) the ad2m1 register is a register t hat specifies the number of a/d conversion clocks and a/d conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ad2m1 0 00 ad2fr3 ad2fr2 ad2fr1 ad2fr0 after reset: 00h r/w address: fffffb81h cautions 1. see table 13-2 setting example duri ng conversion mode for the ad2fr3 to ad2fr0 bits. 2. changing the ad2fr3 to ad2fr0 bits is prohibited during conversion operation (ad2ce bit = 1). 3. be sure to set bits 4 to 7 to ?0?. table 13-2. setting exampl e during conversion mode ad2fr3 ad2fr2 ad2fr1 ad2fr0 number of a/d conversion clocks note a/d conversion time f ad2 = 32 mhz (f xx = 64 mhz) f ad 2 = 24 mhz (f xx = 48 mhz) 0 0 0 1 62 62/f ad2 setting prohibited setting prohibited 0 0 1 0 93 93/f ad2 setting prohibited 3.86 s 0 0 1 1 124 124/f ad2 3.88 s 5.17 s 0 1 0 0 155 155/f ad2 4.84 s 6.46 s 0 1 0 1 186 186/f ad2 5.81 s 7.75 s 0 1 1 0 217 217/f ad2 6.78 s 9.04 s 0 1 1 1 248 248/f ad2 7.75 s setting prohibited 1 0 0 0 279 279/f ad2 8.72 s setting prohibited 1 0 0 1 310 310/f ad2 9.69 s setting prohibited other than above setting prohibited note the number of clocks (f ad2 ) from the start to the end of a/d conversion. caution set the a/d conversion ti me in a range from 3.8 to 10 s. remark f ad2 : operating clock of a/d converter 2
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 694 (3) a/d converter 2 channel sp ecification register (ad2s) the ad2s register is a register that specif ies the analog input pin to be a/d-converted. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ad2s 0 0 0 0 ad2s2 ad2s1 ad2s0 after reset: 00h r/w address: fffffb82h ani20 ani21 ani22 ani23 ani24 note ani25 note ani26 note ani27 note ani20 ani20, ani21 ani20 to ani22 ani20 to ani23 ani20 to ani24 note ani20 to ani25 note ani20 to ani26 note ani20 to ani27 note ad2s2 0 0 0 0 1 1 1 1 ad2s1 0 0 1 1 0 0 1 1 ad2s0 0 1 0 1 0 1 0 1 select mode scan mode note v850e/ig3 only. with the v850e/if3, this setting is not availa ble because the necessary pins are not provided. caution be sure to set bits 3 to 7 to ?0?.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 695 (4) a/d2 conversion result regi sters n, nh (ad2crn, ad2crnh) the ad2crn and ad2crnh registers ar e registers that hold t he a/d conversion results. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar) and stored in the higher 10 bits of the ad2crn register. the lo wer 6 bits of these registers are always 0 when read. the higher 8 bits of a/d conversion re sult are read to the ad2crnh register. these registers can only be read in 16-bit or 8-bit unit s. when the a/d conversion results are read in 16-bit units, the ad2crn register is specified, and when t he higher 8 bits are read, the ad2crnh register is specified. reset sets ad2crn register to 0000h and ad2crnh register to 00h. caution if a write operation is pe rformed on the ad2m0, ad2m1, and ad2 s registers, the contents of the ad2crn register may become undefined. read the conversion result after the conversion operation and before performing a write operation on the ad2m0, ad2m1, and ad2s registers. the correct conversion result m ay not be read if the timing is other than the above. after reset: 0000h r address: ad2cr0 fffffb90h, ad2cr1 fffffb92h, ad2crn ad 29 ad 28 ad 27 ad 26 ad 25 ad 24 ad 23 ad 22 ad 21 ad 20 000000 ad2cr2 fffffb94h, ad2cr3 fffffb96h, ad2cr4 fffffb98h note , ad2cr5 fffffb9ah note , ad2cr6 fffffb9ch note , ad2cr7 fffffb9eh note v850e/if3 n = 0 to 3 v850e/ig3 n = 0 to 7 note v850e/ig3 only. ad29 ad2crnh ad28 ad27 ad26 ad25 ad24 ad23 ad22 76 54 321 0 after reset: 00h r address: ad2cr0h fffffb91h, ad2cr1h fffffb93h, ad2cr2h fffffb95h, ad2cr3h fffffb97h, ad2cr4h fffffb99h note , ad2cr5h fffffb9bh note , ad2cr6h fffffb9dh note , ad2cr7h fffffb9fh note v850e/if3 n = 0 to 3 v850e/ig3 n = 0 to 7 note v850e/ig3 only. the correspondence between the analog input pins and the ad2crn and ad2crnh registers is shown below. table 13-3. correspondence between analog i nput pins and ad2crn and ad2crnh registers analog input pin a/d conversion result register ani20 ad2cr0, ad2cr0h ani21 ad2cr1, ad2cr1h ani22 ad2cr2, ad2cr2h ani23 ad2cr3, ad2cr3h ani24 note ad2cr4 note , ad2cr4h note ani25 note ad2cr5 note , ad2cr5h note ani26 note ad2cr6 note , ad2cr6h note ani27 note ad2cr7 note , ad2cr7h note note v850e/ig3 only
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 696 the relationship between the analog voltage input to t he analog input pin (ani2n) and the a/d conversion result (of a/d2 conversion result register n (ad2crn)) is as follows: v in sar = int ( av dd2 1,024 + 0.5) adcr note = sar 64 or, av dd2 av dd2 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av dd2 : av dd2 pin voltage adcr: value of a/d2 conversi on result register n (ad2crn) note the lower 6 bits of the ad2crn register are fixed to 0. the relationship between the analog input voltage and the a/d conversion results is shown in figure 13-2. figure 13-2. relationship between analog input voltage and a/d conversion results 1023 1022 1021 sar ad2crn ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h 3 2 1 0 input voltage/av dd2 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion result (ad2crn) remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 697 13.4 operation 13.4.1 basic operation <1> set the ad2m0.ad2ps bit to 1 to turn on a/d power while the ad2m0.ad2ce bit = 0. at this time, bits other than the ad2m0.ad2ce bit can be simultaneously set. <2> select an operation mode of a/d conversion and a/d conversion time by using the ad2m0, ad2m1, and ad2s registers. <3> setting the ad2m0.ad2ce bit to 1 (enable conversion) at least 2 s after turning on a/d power (ad2m0.ad2ps bit = 0 1) starts a/d conversion. if the ad2ce bit is set to 1 before 2 s passes, the conversion operation is started and ends after a/d conversion time, but the conversion result is undefined. <4> when a/d conversion is started, t he voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> when sampling has been performed for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until a/d conversion ends. <6> set bit 9 of the successive approximation register ( sar) and changes the level of the voltage tap of the d/a converter to the reference voltage (1/2av dd2 ). <7> the voltage generated by the volt age tap of the d/a converter is com pared with the analog input voltage by a voltage comparator. if the analog input voltage is found to be greater than (1/2av dd2 ) as a result of comparison, the msb of the sar r egister remains set. if the analog input voltage is less than (1/2av dd2 ), the msb is reset. <8> next, bit 8 of the sar register is automatically set, and the next comparison is start ed. the voltage tap of the d/a converter is selected according to the value of bit 9, to which the result has been already set as shown below. bit 9 = 1: (3/4av dd2 ) bit 9 = 0: (1/4av dd2 ) the voltage tap of t he d/a converter and the analog input voltage are compared and bit 8 of the sar register is manipulated according to the result of the comparison as shown below. analog input voltage voltage tap of d/a converter: bit 8 = 1 analog input voltage voltage tap of d/a converter: bit 8 = 0 comparison is continued like this to bit 0 of the sar register.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 698 <9> when comparison of 10 bits has been completed, the valid digital result remains in the sar register. this value is transferred to the ad2crn register and the conv ersion result is stored in this register (v850e/if3: n = 0 to 3, v850e/ig3: n = 0 to 7). an a/d2 conversion end interrupt request sig nal (intad2) is generated simultaneously in the select mode and when all the s pecified a/d conversion operati ons are completed in the scan mode. <10> in the continuous select mode or continuous scan mode, <4> to <9> are repeated unless the ad2ce bit is set to 0 after completion of a/d conversion. in the one-shot select mode or one- shot scan mode, the conv ersion operation is stopped after it is completed (at this time, the ad2m0.ad2ce bit holds 1 and is not aut omatically cleared). write 1 to the ad2ce bit to start conversion operation again. figure 13-3. basic operation of a/d converter 2 sar ad2crn intad2 a/d conversion time sampling time sampling operation of a/d converter 2 a/d conversion undefined conversion result conversion result remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 699 13.4.2 trigger mode trigger mode that serve as the start timing of an a/d conversion operation is software trigger mode. this mode is set by the ad2m0 register. (1) software trigger mode in this mode, the analog input pin (ani2n) specified by the ad2s.ad2s2 to ad2s.ad2s0 bits is used for the a/d conversion start timing by setting the ad2m0.ad2ce bit to 1. after a/d conversion ends, the conversion result is stor ed in a/d2 conversion result register n (ad2crn). an a/d2 conversion end interrupt request signal (i ntad2) is generated simult aneously when a/d conversion operations are completed in the select mode. intad2 interrupt request signal is generated when all the specified a/d conversion operations are completed in the scan mode. if the operation mode set by the ad2m0.ad2md1 and ad2m0. ad2md0 bits is the continuous select mode or continuous scan mode, the conversion operation is repeat ed unless the ad2m0.ad2ce bit is set to 0. in the one-shot select mode or one-shot scan mode, the conv ersion operation is stopped after a/d conversion ends. the ad2m0.ad2ef bit is set to 1 (conversion in progr ess) when a/d conversion is started, and set to 0 (conversion stops) when it is completed. if the ad2m0 and ad2s registers are written during a/d conv ersion, the conversion is stopped and executed again from the beginning. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 700 13.4.3 operation mode there are four operation modes to which the ani2n pin is set: continuous select mode, continuous scan mode, one-shot select mode, and one-shot sc an mode. these modes are set by t he ad2m0.ad2md1 and ad2m0.ad2md0 registers. the relationship between the ad2m0, ad2m1, and ad2s registers and operation mode is shown below. set value trigger mode operation mode ad2m0 ad2m1 ad2s continuous select x100000xb 0000xxxxb 00000xxxb continuous scan x101000xb 0000xxxxb 00000xxxb one-shot select x110000xb 0000xxxxb 00000xxxb software trigger one-shot scan x111000xb 0000xxxxb 00000xxxb (1) continuous select mode in this mode, the analog input pin (a ni2n) specified by the ad2s register is a/d-converted continuously. the conversion results are stored in the ad2crn register corresponding to t he ani2n pin. the ani2n pin and the ad2crn register correspond one to one, and an a/d2 co nversion end interrupt request signal (intad2) is generated each time one a/d conversion ends. after a/d conversion ends, the conversion is repeated again unless the ad2m0.ad2ce bit is set to 0. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 701 figure 13-4. continuous select mode operation timing (when ad2m0.ad2md1 and ad2m0.ad2 md0 bits = 00, ad2s.ad2s2 to ad2s.ad2s0 bits = 001): v850e/ig3 data 1 (ani21) data 2 (ani21) data 3 (ani21) data 4 (ani21) data 5 (ani21) data 1 (ani21) data 2 (ani21) data 3 (ani21) data 4 (ani21) data 5 (ani21) data 6 (ani21) data 6 (ani21) conversion end ad2ce bit clear conversion start ad2ce bit set conversion start ad2ce bit set intad2 interrupt software processing ad2cr1 register a/d conversion ani21 (input) data 1 data 2 data 3 data 4 data 5 data 6 ani20 ani21 ani22 ani23 ani24 ani25 ani26 ani27 ad2cr0 ad2cr1 ad2cr2 ad2cr3 ad2cr4 ad2cr5 ad2cr6 ad2cr7 a/d converter 2 ad2crn register analog input pin
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 702 (2) continuous scan mode in this mode, the analog input pin (ani2n) specified by the ad2s register is se lected sequentially from the ani20 pin, and a/d conversion is ex ecuted continuously. the a/d conv ersion results are stored in the ad2crn register corresponding to the analog input pin. when conversion of all the specified analog input pin ends, the a/d2 conversion end interrupt request signal (i ntad2) is generated. afte r a/d conversion ends, the conversion is started again from the ani20 pi n, unless the ad2m0.ad2ce bit is set to 0. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 703 figure 13-5. continuous scan mode operation timing (when ad2m0.ad2md1 and ad2m0.ad2 md0 bits = 01, ad2s.ad2s2 to ad2s.ad2s0 bits = 011): v850e/ig3 data 1 (ani20) data 2 (ani21) data 3 (ani22) data 4 (ani23) data 5 (ani20) data 5 (ani20) data 6 (ani21) data 7 (ani22) conversion start ad2ce bit set intad2 interrupt software processing ad2cr0 register a/d conversion ani20 (input) ani21 (input) ani22 (input) ani23 (input) data 2 (ani21) data 96 (ani21) ad2cr1 register data 3 (ani22) ad2cr2 register data 4 (ani23) ad2cr3 register data 1 data 2 data 3 data 4 data 6 data 5 data 7 data 1 (ani20) ani20 ani21 ani22 ani23 ani24 ani25 ani26 ani27 ad2cr0 ad2cr1 ad2cr2 ad2cr3 ad2cr4 ad2cr5 ad2cr6 ad2cr7 a/d converter 2 ad2crn register analog input pin
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 704 (3) one-shot select mode in this mode, the analog input pin (ani2n) specified by the ad2s regi ster is a/d-converted once. the conversion result is stored in the ad2crn register corresponding to the ani2n pin. the ani2n pin and the ad2crn register correspond one to one, and an a/d2 co nversion end interrupt request signal (intad2) is generated each time one a/d conversion ends. after a/d conversion ends, the c onversion operation is stopped. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 figure 13-6. one-shot select mode operation timing (when ad2m0.ad2md1 and ad2m0.ad2 md0 bits = 10, ad2s.ad2s2 to ad2s.ad2s0 bits = 001): v850e/ig3 data 1 (ani21) data 2 (ani21) data 1 (ani21) data 2 (ani21) conversion start ad2ce bit set conversion end ad2ce bit clear conversion start ad2ce bit set intad2 interrupt ad2cr1 register a/d conversion ani21 (input) data 1 data 2 software processing ani20 ani21 ani22 ani23 ani24 ani25 ani26 ani27 ad2cr0 ad2cr1 ad2cr2 ad2cr3 ad2cr4 ad2cr5 ad2cr6 ad2cr7 a/d converter 2 ad2crn register analog input pin
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 705 (4) one-shot scan mode in this mode, pins up to the analog input pin (ani2n) s pecified by the ad2s register from the ani20 pin are selected sequentially, and a/d conversion is executed. the a/d conversion results are stored in the ad2crn register corresponding to the analog input pin. when co nversion of all the specif ied analog input pins ends, the a/d2 conversion end interrupt request signal (intad2) is generated. after a/d conversion ends, the conversion operation is stopped. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 706 figure 13-7. one-shot scan mode operation timing (when ad2m0.ad2md1 and ad2m0.ad2 md0 bits = 11, ad2s.ad2s2 to ad2s.ad2s0 bits = 011): v850e/ig3 conversion start ad2ce bit set data 1 (ani20) data 2 (ani21) data 3 (ani22) data 4 (ani23) data 5 (ani20) data 1 (ani20) data 5 (ani20) data 6 (ani21) conversion start ad2ce bit set intad2 interrupt ad2cr0 register a/d conversion ani20 (input) ani21 (input) ani22 (input) ani23 (input) data 2 (ani21) ad2cr1 register data 3 (ani22) ad2cr2 register data 4 (ani23) ad2cr3 register data 1 data 2 data 3 data 4 data 5 data 6 software processing ani20 ani21 ani22 ani23 ani24 ani25 ani26 ani27 ad2cr0 ad2cr1 ad2cr2 ad2cr3 ad2cr4 ad2cr5 ad2cr6 ad2cr7 a/d converter 2 ad2crn register analog input pin
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 707 13.5 operation in software trigger mode when the ad2m0.ad2ce bit is set to 1, a/d conversion is started. when a/d conversion is started, the ad2m 0.ad2ef bit = 1 (conversion in progress). if the ad2m0 and ad2s registers are written during a/d c onversion, the conversion is stopped and executed again from the beginning. (1) operation in software tri gger continuous select mode in this mode, one analog input pin (ani2n) specified by the ad2s register is a/d-converted once. the conversion results are stored in one ad2crn register. the ani2n pin and ad2crn register correspond one to one. each time an a/d conversion is executed, an a/d2 co nversion end interrupt request signal (intad2) is generated and a/d conversion ends. after a/d conversi on ends, the conversion is repeated again unless the ad2m0.ad2ce bit is set to 0. it is not necessary to set (1) the ad2m 0.ad2ce bit to restart a/d conversion note . note in the software trigger continuous select mode, the a/d conversion operation is not stopped unless the ad2m0.ad2ce bit is set to 0. if the ad2crn regi ster is not read before t he next a/d conversion ends, it is overwritten. this mode is suitable for applications in which the a/d conversion value of one analog input pin is read. analog input pin a/d conversion result register ani2n ad2crn remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 figure 13-8. operation example of software trigger continuous se lect mode: v850e/ig3 ani20 ani21 ani22 ani23 ad2cr0 ad2cr1 ad2cr2 ad2cr3 a/d converter 2 ad2m0 ani24 ani25 ani26 ani27 ad2cr4 ad2cr5 ad2cr6 ad2cr7 (1) the ad2ce bit = 1 (enable) (5) the intad2 interrupt request signal is generated (2) the ani22 pin is a/d-converted (6) return to (2) (3) the conversion result is stored in the ad2cr2 regi ster (7) to end the conversion, the ad2ce bit = 0 (stop) (4) the ad2m0.ad2ef bit = 0 remark this is an operation example with the following setting. ad2m0.ad2md1 and ad2m0.ad2md0 bits = 00, ad2s.ad2s2 to ad2s.ad2s0 bits = 010
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 708 (2) software trigger conti nuous scan mode operations in this mode, pins up to the analog input pin (ani2n) s pecified by the ad2s register from the ani20 pin are selected sequentially, and a/d conversion is executed c ontinuously. the a/d conver sion results are stored in the ad2crn register corresponding to the analog input pin. when conversion of all the specified analog input pins ends, the a/d2 conversion end interrupt request signal (intad2) is generated. after a/d c onversion ends, the conversion is start ed again from the ani20 pin, unless the ad2m0.ad2ce bit is set to 0. it is not necessary to set (1) the ad2m 0.ad2ce bit to restart a/d conversion note . note in the software trigger continuous scan mode, the a/ d conversion operation is not stopped unless the ad2m0.ad2ce bit is set to 0. if the ad2crn regi ster is not read before t he next a/d conversion ends, it is overwritten. this mode is suitable for applications in which mu ltiple analog inputs are constantly monitored. analog input pin a/d conversion result register ani20 ad2cr0 ani2n note ad2crn note set by the ad2s.ad2s0 to ad2s.ad2s2 bits. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 figure 13-9. operation example of software trigger continuous scan mode: v850e/ig3 ani20 ani21 ani22 ani23 ad2cr0 ad2cr1 ad2cr2 ad2cr3 a/d converter 2 ad2m0 ani24 ani25 ani26 ani27 ad2cr4 ad2cr5 ad2cr6 ad2cr7 (1) the ad2ce bit = 1 (enable) (6) the ani22 pin is a/d-converted (2) the ani20 pin is a/d-converted (7) the conver sion result is stored in the ad2cr2 register (3) the conversion result is stored in the ad2cr0 regi ster (8) the intad2 interrupt request signal is generated (4) the ani21 pin is a/d-converted (9) return to (2) (5) the conversion result is stored in the ad2cr1 regi ster (10) to end the conversion, the ad2ce bit = 0 (stop) remark this is an operation example with the following setting. ad2m0.ad2md1 and ad2m0.ad2md0 bits = 01, ad2s.ad2s2 to ad2s.ad2s0 bits = 010 . . . . . .
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 709 (3) software trigger one-shot select mode in this mode, the voltage of one analog in put pin (ani2n) specified by the ad2s register is a/d-converted once. the conversion result is stored in one ad2crn register. the ani2n pin and the ad2crn register correspond one to one. each time an a/d conversion is executed, an a/d2 co nversion end interrupt request signal (intad2) is generated and a/d conversion ends. after a/d conver sion ends, the conversion operation is stopped. if the ad2m0.ad2ce bit is set to 1, a/d conversion can be restarted. this mode is suitable for applications in which the re sults of each first-time a/d conversion are read. analog input pin a/d conversion result register ani2n ad2crn remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 figure 13-10. operation example of software trigger one-shot select mode: v850e/ig3 ani20 ani21 ani22 ani23 ad2cr0 ad2cr1 ad2cr2 ad2cr3 a/d converter 2 ad2m0 ani24 ani25 ani26 ani27 ad2cr4 ad2cr5 ad2cr6 ad2cr7 (1) the ad2ce bit = 1 (enable) (4) the ad2m0.ad2ef bit = 0 (2) the ani22 pin is a/d-converted (5) the intad2 interrupt request signal is generated (3) the conversion result is stored in the ad2cr2 register remark this is an operation example with the following setting. ad2m0.ad2md1 and ad2m0.ad2md0 bits = 10, ad2s.ad2s2 to ad2s.ad2s0 bits = 010
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 710 (4) software trigger one-s hot scan mode operations in this mode, pins up to the analog input pin (ani2n) s pecified by the ad2s register from the ani20 pin are selected sequentially, and a/d conversion is executed c ontinuously. the a/d conver sion results are stored in the ad2crn register corresponding to the analog input pin. when conversion of all the specified analog input pin ends, the a/d2 conversion end interrupt request signal (intad2) is generated. after a/d conversion ends, the conversion operation is stopped. if the ad2m0.ad2ce bit is set to 1, a/d conversion can be restarted. this mode is suitable for applications in which mu ltiple analog inputs are constantly monitored. analog input pin a/d conversion result register ani20 ad2cr0 ani2n note ad2crn note set by the ad2s.ad2s0 to ad2s.ad2s2 bits. remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 figure 13-11. operation example of softwa re trigger one-shot scan mode: v850e/ig3 ani20 ani21 ani22 ani23 ad2cr0 ad2cr1 ad2cr2 ad2cr3 a/d converter 2 ad2m0 ani24 ani25 ani26 ani27 ad2cr4 ad2cr5 ad2cr6 ad2cr7 (1) the ad2ce bit = 1 (enable) (6) the ani22 pin is a/d-converted (2) the ani20 pin is a/d-converted (7) the conver sion result is stored in the ad2cr2 register (3) the conversion result is stored in the ad2cr0 register (8) the ad2m0.ad2ef bit = 0 (4) the ani21 pin is a/d-converted (9) the intad2 interrupt request signal is generated (5) the conversion result is stored in the ad2cr1 register remark this is an operation example with the following setting. ad2m0.ad2md1 and ad2m0.ad2md0 bits = 11, ad2s.ad2s2 to ad2s.ad2s0 bits = 010 . . . . . .
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 711 13.6 internal equivalent circuit the following figure shows the equivalent circuit of the analog input block. ani2n c 1 c in r in r c 1 c 2 2.6 k 15 pf 6.2 pf remarks 1. the maximum values are shown (reference values). 2. v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 ad2m1 register ad2fr3 bit ad2fr2 bit ad2fr1 bit ad2fr0 bit number of a/d conversion clocks (f ad2 ) number of sampling clocks 0 0 0 1 62 33 0 0 1 0 93 49.5 0 0 1 1 124 66 0 1 0 0 155 82.5 0 1 0 1 186 99 0 1 1 0 217 115.5 0 1 1 1 248 132 1 0 0 0 279 148.5 1 0 0 1 310 165 caution number of sampling clocks is included in numbe r of a/d conversion clocks. number of a/d conversion clocks (a/d conversion time) sampling clock conversion start conversion end
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 712 an example of calculating an overall e rror of a/d converter 2 is shown below. ani2n v850e/if3, v850e/ig3 c 1 c 2 r v ain c 0 r i f xx (mhz) a/d conversion time ( s) sampling ( s) r (k ) c 1 (pf) c 2 (pf) c 0 (pf) r i (k ) sampling error (lsb) note 100 1.0 0.1 or lower 100 0.5 0.1 or lower 100 0.25 0.1 or lower 100 0.125 0.1 or lower 50 1.0 0.1 or lower 50 0.5 0.1 or lower 50 0.25 0.1 or lower 64 3.88 (62/f ad2 ) 1.03 (33/f ad2 ) 2.6 15 6.2 50 0.125 0.1 or lower note the error when considering the signal source impedance is ?sampling error + overall error?. remarks 1. these values are reference values calculated by simulating what happens to c 2 voltage by r i and c 0 when v ain is applied from 0 v to 5 v at the same time as sampling start. 2. v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 3. f xx : system clock frequency f ad2 : operating clock frequency
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 713 13.7 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consum ption can be reduced by clearing the ad2m0.ad2ce and ad2m0.ad2ps bits to 0. (2) input range of ani2n pin input the voltage within the specified range to the ani2n pin. if a voltage equal to or higher than av dd2 or equal to or lower than av ss2 (even within the range of the absolute maxi mum ratings) is input to this pin, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the ani2n pin must be effectively protected from noise. the influence of noise increases as the output impedanc e of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 13-12 is recommended. figure 13-12. processing of analog input pin av dd2 ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), v dd0 , v dd1 ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), v ss0 , v ss1 av ss2 clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av dd2 or equal to or lower than av ss2 may be generated. c = 100 to 1000 pf ani2n remark v850e/if3: n = 0 to 3 v850e/ig3: n = 0 to 7 (4) alternate input the analog input pin (ani2n) functions alternately as input port (p7n). when selecting one of the ani2n pin to execute a/d conversion, do not execut e an input instruction to port 7 during conversion as the conversion resolution may drop.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 714 (5) interrupt request flag (ad2if) the interrupt request flag (ad2if) is not cleared even if the contents of the ad2s r egister are changed. if the analog input pin is changed during a/d co nversion, therefore, the result of converting the previously selected analog input signal may be stored and the a/d2 conversi on end interrupt request flag may be set immediately before the ad2s register is rewritten. if the ad2if flag is read immediately after the ad2s register is rewritten, the ad2if flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, cl ear the ad2if flag before resuming conversion. figure 13-13. generation timing of a/ d2 conversion end interrupt request ad2s rewriting (ani2n conversion start) ad2s rewriting (ani2m conversion start) ad2if is set, but ani2m conversion has not ended a/d conversion a/d conversion result register intad2 ani2n ani2n ani2m ani2m ani2m ani2n ani2n ani2m remark v850e/if3: n = 0 to 3, m= 0 to 3 v850e/ig3: n = 0 to 7, m = 0 to 7
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 715 (6) av dd2 pin (a) the av dd2 pin is used as the power supply pin of the a/d converter 2 and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same potential as ev dd0 , ev dd1 , and ev dd2 (v850e/ig3 only) to the av dd2 pin as shown in figure 13-12. (b) the av dd2 pin is also used as the reference voltage pin of the a/d converter 2. if the source supplying power to the av dd2 pin has a high impedance or if the power s upply has a low current supply capability, the reference voltage may fluctuate due to the cu rrent that flows during conversion (especially, immediately after the conversion operation enable (a d2ce bit = 1)). as a result, the conversion accuracy may drop. to avoid this, it is re commended to connect a capacitor across the av dd2 and av ss2 pins to suppress the reference voltage fluctuation as shown in figure 13-14. (c) if the source supplying power to the av dd2 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 13-14. av dd2 pin connection example av dd2 av ss2 main power supply (7) reading ad2crn register when the ad2m0, ad2m1, or ad2s register is written, the contents of the ad2crn register may be undefined. read the conversion result after completion of conversion and before writing to the ad2m0, ad2m1, and ad2s registers. the correct conversion result may not be read at a timing different from the above. (8) a/d conversion result if there is noise at the analog input pin (ani 2n) or at the power supply voltage pin (av dd2 ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effe ct on the system from this illegal conversion result. an example of this software processing is shown below. ? take the average result of a number of a/d conv ersions and use that as the a/d conversion result. ? execute a number of a/d conversions successively a nd use those results, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judged to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing counteractive measures.
chapter 13 a/d converter 2 user?s manual u18279ej3v0ud 716 (9) standby mode because the a/d converter 2 stops operating in the id le and stop modes, conversion results are invalid, so power consumption can be reduced. operations are resumed after the idle and stop modes are released, but the a/d conversion results after the idle and stop modes are released are invalid. when using the a/d converter 2 after the idle and stop modes are released, before setting the idle and stop modes or releasing the idle and stop modes, set the ad2m0.ad2ce bit to 0 then set the ad2ce bit to 1 after releasing the idle and stop modes. (10) variation of a/d conversion results the results of the a/d conversion ma y vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the variation, take counteractive measures with the program, such as by averaging the a/d conversion results. (11) a/d conversion result hysteresis characteristics successive comparison type a/d converters hold an analog input voltage in an internal sample & hold capacitor and then perform a/d conversion. after the a/ d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur if the output impedance from the analog input source is too high. ? when the same channel is used for a/d conversions, if th e voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. even if the conversion were to be performed at the same potentia l, the results may thus vary. ? when switching the analog input channel, hysteres is characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. even if the conversion were to be performed at the same potential, t he results may thus vary. to obtain more accurate conversion results, lower the output impedance from the analog input source or execute a/d conversion twice consecutively on the same channel, and discard the first conversion result. 13.8 how to read a/d converter characteristics table for details about the a/d conver ter characteristics table, see 12.7 how to read a/d converter characteristics table .
user?s manual u18279ej3v0ud 717 chapter 14 asynchronous ser ial interface a (uarta) 14.1 mode switching between uarta and other serial interface 14.1.1 mode switching between uarta0 and csib0 in the v850e/if3 and v850e/ig3, uarta0 and csib0 functi on alternately, and these pins cannot be used at the same time. to switch between uarta0 and csib0, the pmc4, pfc4, and pfce4 registers must be set in advance. caution the operations related to transmission and reception of uarta0 or csib0 are not guaranteed if the mode is switched during transm ission or reception. be sure to disable the unit that is not used. figure 14-1. mode switch settings of uarta0 and csib0 pfc4 after reset: 00h r/w address: fffff468h pfc47 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 0 1 2 3 4 5 6 7 pfce4 after reset: 00h r/w address: fffff708h pfce47 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 0 1 2 3 4 5 6 7 i/o port sckb0 i/o intp13 input setting prohibited setting prohibited pmc42 0 1 1 1 1 pfce42 0 0 1 1 pfc42 0 1 0 1 specification of alternate function of p42 pin pmc4 after reset: 00h r/w address: fffff448h pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 1 2 3 4 5 6 7 i/o port sob0 output txda0 output setting prohibited setting prohibited pmc41 0 1 1 1 1 pfce41 0 0 1 1 pfc41 0 1 0 1 specification of alternate function of p41 pin i/o port sib0 input rxda0 input pmc40 0 1 1 pfc40 0 1 specification of alternate function of p40 pin remark = don?t care
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 718 14.1.2 mode switching between uarta1 and i 2 c in the v850e/if3 and v850e/ig3, uarta1 and i 2 c function alternately, and their pins cannot be used at the same time. to switch between uarta1 and i 2 c, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to tran smission and reception of uarta1 or i 2 c are not guaranteed if the mode is switched during transmissi on or reception. be sure to disable the unit that is not used. figure 14-2. mode switch settings of uarta1 and i 2 c pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port txda1 output sda i/o setting prohibited setting prohibited pmc31 0 1 1 1 1 pfce31 0 0 1 1 pfc31 0 1 0 1 specification of alternate function of p31 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port rxda1 input scl i/o setting prohibited setting prohibited pmc30 0 1 1 1 1 pfce30 0 0 1 1 pfc30 0 1 0 1 specification of alternate function of p30 pin remark x = don?t care
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 719 14.1.3 mode switching between uarta2 and csib1 in the v850e/if3 and v850e/ig3, uarta2 and csib1 function alternately, and their pins cannot be used at the same time. to switch between uarta2 and csib1, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of uarta2 or csib1 are not guaranteed if the mode is switched during transm ission or reception. be sure to disable the unit that is not used. figure 14-3. mode switch settings of uarta2 and csib1 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port sckb1 i/o intp11 input cs0 note output setting prohibited pmc34 0 1 1 1 1 pfce34 0 0 1 1 pfc34 0 1 0 1 specification of alternate function of p34 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port sob1 output txda2 output pmc33 0 1 1 pfc33 0 1 specification of alternate function of p33 pin i/o port sib1 input rxda2 input cs1 note output setting prohibited pmc32 0 1 1 1 1 pfce32 0 0 1 1 pfc32 0 1 0 1 specification of alternate function of p32 pin note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark x = don?t care
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 720 14.2 features { transfer rate: 300 bps to 1.25 mbps (using peripheral clock (f xx ) of 64 mhz and dedicated baud rate generator) { full-duplex communication: internal uarta receive data register n (uanrx) internal uarta transmit data register n (uantx) { 2-pin configuration: txdan: transmit data output pin rxdan: receive data input pin { reception error output function ? parity error ? framing error ? overrun error { interrupt sources: 3 ? reception error interrupt (intuanre): this inte rrupt is generated by oring the three types of reception errors ? reception end interrupt (intuanr): this interr upt occurs upon transfer of receive data from the shift register to the uanrx register after serial transfer end, in the reception enabled status. ? transmission enable interrupt (intuant): this interr upt occurs upon transfer of transmit data from the uantx register to the shift regi ster in the transmission enabled status. { character length: 7, 8 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb-/lsb-first transfer selectable { transmit/receive data inverted input/output possible remark n = 0 to 2
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 721 14.3 configuration the block diagram of the uartan is shown below. figure 14-4. block diagram of uartan uanopt0 uanctl0 uanstr uanctl1 uanctl2 clock selector uanrx reception unit transmission unit transmit shift register transmission controller reception controller baud rate generator receive shift register filter selector baud rate generator selector parity framing overrun uantx internal bus internal bus intuanr intuant txdan rxdan f xx /2 to f xx /4096 intuanre remarks 1. n = 0 to 2 2. for the configuration of the baud rate generator, see figure 14-12 . uartan consists of the following hardware units. table 14-1. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx)
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 722 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the base clock (f uclk ) for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register us ed to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstr register consists of flags indicating the e rror contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receiv e data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transfe rred from the uartan receive shift register to the uanrx register in synchronization with the comple tion of shift-in processing of 1 frame. transfer to the uanrx register also causes the recepti on end interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the uartan transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register , the uartan transmit shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. tr ansmission starts when transmit data is written to the uantx register. when data can be wri tten to the uantx register (when dat a of one frame is transferred from the uantx register to the uartan transmit shift regi ster), the transmission enable interrupt request signal (intuant) is generated.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 723 14.4 control registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 2) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock (f uclk ), and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 14.7 (1) (a) base clock ). ? when the operation is enabled (uanpwr bit = 1), the transmission operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uantxe = 1. ? when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uantxe bit = 0 by the uanpwr bit even if the uantxe bit is 1. the transmission operation is enabled when the uanpwr bit is set to 1 again. disable reception operation enable reception operation uanrxe 0 1 reception operation enable ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. ? to initialize the reception unit, clear the uanrxe bit to 0, wait for two cycles of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 14.7 (1) (a) base clock ). ? when the operation is enabled (uanpwr bit = 1), the reception operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uanrxe = 1. the start bit is ignored if it is received before the reception operation is enabled. ? when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uanrxe bit = 0 by the uanpwr bit even if the uanrxe bit is 1. the reception operation is enabled when the uanpwr bit is set to 1 again. <7> 0
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 724 (2/2) 7 bits 8 bits uancl note 0 1 specification of data character length of 1 frame of transmit/receive data 1 bit 2 bits uansl note 0 1 specification of length of stop bit for transmit data only the first bit of the receive data stop bits is checked, regardless of the value of the uansl bit. if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, since the uanstr.uanpe bit is not set, no error interrupt due to a parity error is output. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 note 0 0 1 1 parity selection during transmission parity selection during reception uanps0 note 0 1 0 1 msb-first transfer lsb-first transfer uandir note 0 1 transfer direction selection note this register can be rewritten only when the uanp wr bit = 0 or the uantxe bit = uanrxe bit = 0. however, setting any or all of the uanpwr, uant xe, and uanrxe bits to 1 at the same time is possible. remark for details of parity, see 14.6.6 parity types and operations . (2) uartan control register 1 (uanctl1) for details, see 14.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 14.7 (3) uartan control register 2 (uanctl2) .
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 725 (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register that c ontrols the serial transfer operation of uartan. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. 0 uanopt0 (n = 0 to 2) 0 0 1 0 1 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h 7 0 ? the output level of the txdan pin can be inverted using the uantdl bit. ? this register can be set when the uanctl0.uanpwr bit = 0 or when the uanctl0.uantxe bit = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit ? the input level of the rxdan pin can be inverted using the uanrdl bit. ? this register can be set when the uanpwr bit = 0 or the uanctl0.uanrxe bit = 0. ? when the uanrdl bit is set to 1 (inverted input of receive data), reception must be enabled (uanctl0.uanrxe bit = 1) after setting the data reception pin to the uart reception pin (rxdan) when reception is started. when the pin mode is changed after reception is enabled, the start bit will be mistakenly detected if the pin level is high. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit caution be sure to set bits 3 and 5 to 7 to ?0?, and set bits 2 and 4 to ?1?. operation with other settings is not guaranteed. (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays t he uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bi t units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions uanstr register ? after reset ? uanctl0.uanpwr bit = 0 uantsf bit ? uanctl0.uantxe bit = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe bit = 0 caution be sure to read and ch eck the error flags of the uanpe, uanfe, and uanove bits, and clear the flags by writing ?0? to them.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 726 uantsf ? when the uanpwr bit = 0 or the uantxe bit = 0 has been set. ? when, following transfer end, there was no next data transfer from uantx register write to uantx register uantsf 0 1 transfer status flag uanstr (n = 0 to 2) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag ? the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. ? the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. ? the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when receive data has been set to the uanrx register and the next receive operation is ended before that receive data has been read. uanove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the uanrx register. ? the uanove bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . <7> <0>
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 727 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer register that stores par allel data converted by the uartan receive shift register. the data stored in the uartan receive shift register is transferred to the uanrx regi ster upon end of reception of 1 byte of data. a reception end interrupt reques t signal (intuanr) is generated at this timing. during lsb-first reception when the data length has been s pecified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error occurs (uanstr.uanove bit = 1), the re ceive data at this time is not transferred to the uanrx register and is discarded. this register is read-only in 8-bit units. in addition to reset, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx (n = 0 to 2) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h 7 0 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. transmission starts when transmit data is written to t he uantx register in the transmission enabled status (uanctl0.uantxe bit = 1). upon end of the transfer of the data of the uantx re gister to the uartan transmit shift register, the transmission enable interrupt request signal (intuant) is generated. this register can be read or written in 8-bit units. reset sets this register to ffh. uantx (n = 0 to 2) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h 7 0
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 728 14.5 interrupt request signals the following three interrupt request signals are generated from uartan. ? reception error interrupt request signal (intuanre) ? reception end interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) among these three interrupt signals, the reception error in terrupt signal has the highest default priority, and the reception end interrupt request signal and transmission enable interrupt request signal follow in this order. table 14-2. interrupts and their default priorities interrupt priority reception error high reception end ? transmission enable low (1) reception error interrupt request signal (intuanre) a reception error interrupt request signal is generated while reception is enabled by oring the three types of reception errors (parity error, framing error, and over run error) explained in the uanstr register section. (2) reception end interrupt request signal (intuanr) a reception end interrupt request signal is output when da ta is shifted into the uartan receive shift register and transferred to the uanrx register in the reception enabled status. no reception end interrupt request signal is generated in the reception disabled status. (3) transmission enable interr upt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 729 14.6 operation 14.6.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 14-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, s pecification of the stop bit length, and specification of msb-/lsb-first transfer ar e performed using the uanctl0 register. moreover, control of uartan output/inverted output for the txdan pin is performed using the uanopt0.uantdl bit. ? start bit ................. 1 bit ? character bits........ 7 bits/8 bits ? parity bit ................ even parity/odd parity/0 parity/no parity ? stop bit .................. 1 bit/2 bits
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 730 figure 14-5. uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdan inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 731 14.6.2 uart transmission a high level is output to the txdan pin by setting the uanctl0.uanpwr bit to 1. next, the transmission enabled status is set by setting t he uanctl0.uantxe bit to 1, and transmission is started by writing transmit data to the uantx register. the st art bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not pr ovided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is tr ansferred to the uartan transmit shift register upon the start of the transmit operation. a transmission enable interrupt request signal (intuant) is generated upon end of transmission of the data of the uantx register to the uartan transmit shift register, and th ereafter the contents of the ua rtan transmit shift register are output to the txdan pin. write of the next transmit data to the uantx register is enabled by generating the intuant signal. figure 14-6. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant remarks 1. lsb first 2. n = 0 to 2
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 732 14.6.3 continuous transmission procedure uartan can write the next transmit data to the uantx regist er when the uartan transmit shift register starts the shift operation. the transmit timing of the uartan transmi t shift register can be judged from the transmission enable interrupt request signal (intuant). an efficient communicat ion rate is realized by writing the data to be transmitted next to the uantx register during transfer. caution during continuous transmission execution, perform initialization after checking that the uanstr.uantsf bit is 0. the transmit data cannot be guaranteed when initialization is performed while the uantsf bit is 1. remark n = 0 to 2 figure 14-7. continuous transmission processing flow start register settings uantx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 733 figure 14-8. continuous transmission operation timing (a) transmission start start data (1) data (1) txdan pin uantx register transmit shift register intuant signal uantsf bit data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) txdan pin uantx register transmit shift register intuant signal uantsf bit uanpwr or uantxe bit parity stop stop start data (n) parity parity stop remark n = 0 to 2
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 734 14.6.4 uart reception the reception wait status is set by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. in the reception wait status, the rxdan pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the falling edge of the rxdan pin is detected and sampling is started at the falling edge. the start bit is recognized if the rxdan pin is low level at the start bit sampling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uart an receive shift register according to the set baud rate. when the reception end interrupt reques t signal (intuanr) is output upon recept ion of the stop bit, the data of the uartan receive shift register is written to the uanrx regist er. however, if an overrun error occurs (uanstr.uanove bit = 1), the receive data at this time is not wr itten to the uanrx register and is discarded. even if a parity error (uanstr.uanpe bit = 1) or a framin g error (uanstr.uanfe bit = 1) occurs during reception, reception continues until the recepti on position of the first stop bit, and the intuanre signal is output following reception end. remark n = 0 to 2 figure 14-9. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuanr signal uanrx register remark : start bit sampling point cautions 1. be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun error occurs during r eception of the next data, and reception errors continue occurring indefinitely. 2. the operation during recepti on is performed assuming that th ere is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the ua nrx register after the reception end interrupt request signal (intuanr) has been generated, a nd clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 befo re the intuanr signal is generated, the read value of the uanrx register cannot be guaranteed. 4. if receive end processing (intuanr signal gene ration) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuanr signal may be generated in spite of these being no data stored in the uanrx register. to end recep tion without wait ing intuanr signal generation, be sure to clear (0) the interrupt request flag (uanric.uanrif), after se tting (1) the interrupt mask flag (uanric.uanrmk) and then set (1 ) the uanpwr bit = 0 or uanrxe bit = 0.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 735 14.6.5 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the uanstr regist er and a reception error interrupt request signal (intuanre) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. caution the reception end interrupt request signal (intuanr) and r eception error interrupt request signal (intuanre) are not generated simultaneous ly. the intuanr signal is generated when a reception ends normally. the intuanre signa l is generated and the intuanr signal is not generated when a reception error occurs. remark n = 0 to 2 ? reception error causes error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data ended before data was read from uanrx register
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 736 14.6.6 parity types and operations the parity bit is used to detect bit errors in the comm unication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transmi t data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1? among the rec eption data, including the parit y bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among t he transmit data, including the parity bit, is controlled so that it is an odd number . the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receiv e data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity e rror occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that ther e is no parity bit. no parity error occurs since there is no parity bit.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 737 14.6.7 receive data noise filter this filter samples signals received via the rxdan pin using the base clock (f uclk ) supplied by the dedicated baud rate generator. when the same sampling value is read twice, the match det ector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 1 clock cy cle width is judged to be noise and is not delivered to the internal circuit (see figure 14-11 ). see 14.7 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 14-10, the processing that goes on wit hin the receive operation is delayed by 3 clocks in relation to the external signal status. remark n = 0 to 2 figure 14-10. noise filter circuit match detector in base clock (f uclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a figure 14-11. timing of rxdan signal judged as noise internal signal b base clock (f uclk ) rxdan (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 738 14.7 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 14-12. configuration of baud rate generator f uclk selector uanpwr bit 8-bit counter match detector baud rate output clock uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxe bit (or uanrxe bit) uanctl1: uancks3 to uancks0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xx /2048 f xx /4096 caution if the cpu clock (f cpu ) is slower than f uclk , uartan cannot be used. remarks 1. n = 0 to 2 2. f xx : peripheral clock frequency (a) base clock when the uanctl0.uanpwr bit is 1, the cl ock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits is supplied to the 8-bit co unter. this clock is called the base clock (f uclk ). when the uanpwr bit = 0, f uclk is fixed to the low level. (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register. the base clock (f uclk ) is selected by the uanctl1.uancks3 to uanctl1.uancks0 bits. the frequency division value for the 8-bit count er can be set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits.
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 739 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan base clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 0 uanctl1 (n = 0 to 2) 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h, ua2ctl1 fffffa21h 7 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 f xx /4,096 setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above remark f xx : peripheral clock frequency
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 740 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. this register can be read or written in 8-bit units. reset sets this register to ffh. caution clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. uanbrs7 uanctl2 (n = 0 to 2) uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset: ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h, ua2ctl2 fffffa22h 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) - 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited remark f uclk : frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 741 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] f uclk : frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits k: value set using the uanctl2.uanbrs7 to uanc tl2.uanbrs0 bits (k = 4, 5, 6, ..., 255) (5) baud rate error the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be wit hin the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in section (7) allowable baud rate range during reception. example peripheral clock frequency = 32 mhz = 32,000,000 hz set value of uanctl1.uancks3 to uanctl1.uancks0 bits = 0000b (f uclk = 16,000,000 hz) set value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits = 00110100b (k = 52) target baud rate = 153,600 baud rate = 16,000,000/ (2 52) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate)
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 742 (6) baud rate setting example table 14-3. baud rate generator setting data f xx = 64 mhz f xx = 32 mhz baud rate (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 08h d0h 0.16 07h d0h 0.16 600 07h d0h 0.16 06h d0h 0.16 1,200 06h d0h 0.16 05h d0h 0.16 2,400 05h d0h 0.16 04h d0h 0.16 4,800 04h d0h 0.16 03h d0h 0.16 9,600 03h d0h 0.16 02h d0h 0.16 19,200 02h d0h 0.16 01h d0h 0.16 31,250 02h 80h 0 00h 80h 0 38,400 01h d0h 0.16 00h d0h 0.16 76,800 00h d0h 0.16 00h 68h 0.16 153,600 00h 68h 0.16 00h 34h 0.16 312,500 00h 33h 0.39 00h 1ah ? 1.54 625,000 00h 1ah ? 1.54 00h 0dh ? 1.54 1,250,000 00h 0dh ? 1.54 00h 06h 6.67 remark f xx : peripheral clock frequency err: baud rate error (%)
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 743 (7) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 14-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartan transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 2 as shown in figure 14-13, the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 2) k: set value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 744 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 14-4. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: set value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
chapter 14 asynchronous serial interface a (uarta) user?s manual u18279ej3v0ud 745 (8) transfer rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via st art bit detection by the receiving side, so this has no influence on the transfer result. figure 14-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) 14.8 cautions when the clock supply to uartan is stopped (for example, in idle or stop mode), the operation stops with each register retaining the value it had imm ediately before the clock supply was stoppe d. the txdan pin output also holds and outputs the value it had immediat ely before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanc tl0.uanrxe, and uanctl0.uantxe bits to 000. remark n = 0 to 2
user?s manual u18279ej3v0ud 746 chapter 15 asynchronous serial interface b (uartb) 15.1 mode switching between uartb and csib2 in the v850e/if3 and v850e/ig3, uartb and csib2 function al ternately, and these pins cannot be used at the same time. to switch between uartb and csib2, the pm c3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of uartb or csib2 are not guaranteed if the mode is switched during transmission or recep tion. be sure to disable the unit that is not used. figure 15-1. mode switch settings of uartb and csib2 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port sckb2 i/o intp12 input astb note output setting prohibited pmc37 0 1 1 1 1 pfce37 0 0 1 1 pfc37 0 1 0 1 specification of alternate function of p37 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port sob2 output txdb output setting prohibited setting prohibited pmc36 0 1 1 1 1 pfce36 0 0 1 1 pfc36 0 1 0 1 specification of alternate function of p36 pin i/o port sib2 input rxdb input setting prohibited setting prohibited pmc35 0 1 1 1 1 pfce35 0 0 1 1 pfc35 0 1 0 1 specification of alternate function of p35 pin note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark x = don?t care
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 747 15.2 features ? transfer rate: maximum 5.33 mbps (using a dedicated baud rate generator) ? full-duplex communications ? single mode and fifo mode selectable ? single mode: 8-bit 1-stage data register (ubtx register or ubrx register) is used for each of transmission and reception. ? fifo mode transmit fifo: ubtx register (8 bits 16 stages). receive fifo: ubrxap register (16 bits 16 stages) 2 bits of the higher 8 bits of t he ubrxap register are for an error flag. ? two-pin configuration txdb: transmit data output pin rxdb: receive data input pin ? reception error detection function ? overflow error (fifo mode only) ? parity error ? framing error ? overrun error (single mode only) ? interrupt sources: 5 types ? reception error interrupt request signal (intubtire) ? reception end interrupt request signal (intubtir) ? transmission enable interrupt request signal (intubtit) ? fifo transmission end interrupt reques t signal (intubtif) (fifo mode only) ? reception timeout interrupt request signal (intubtito) (fifo mode only) ? the character length of transmit/receive data is specified according to the ubctl0 register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? msb first/lsb first selectable for transfer data ? on-chip dedicated baud rate generator
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 748 15.3 configuration the block diagram of the uartb is shown below. figure 15-2. block diagram of uartb rxdb internal bus receive shift register uartb control register 0 (ubctl0) uartb control register 2 (ubctl2) uartb status register (ubstr) uartbfifo control register 0 (ubfic0) uartbfifo control register 1 (ubfic1) uartbfifo control register 2 (ubfic2) uartbfifo status register 0 (ubfis0) uartbfifo status register 1 (ubfis1) ubrx receive fifo timeout counter sampling block receive controller transmit controller baud rate generator reception unit transmission unit baud rate generator transmit shift register ubtx transmit fifo intubtito txdb intubtif intubtit intubtir intubtire f xx remarks 1. f xx : peripheral clock 2. for the configuration of the baud rate generator, see figure 15-9 .
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 749 uartb consists of the following hardware units. table 15-1. configuration of uartb item configuration registers uartb control register 0 (ubctl0) uartb control register 2 (ubctl2) uartb status register (ubstr) uartb fifo control register 0 (ubfic0) uartb fifo control register 1 (ubfic1) uartb fifo control register 2 (ubfic2) uartb fifo status register 0 (ubfis0) uartb fifo status register 1 (ubfis1) receive shift register uartb receive data register ap (ubrxap) uartb receive data register (ubrx) transmit shift register uartb transmit data register (ubtx) (1) uartb control register 0 (ubctl0) this register controls the transfer operation of uartb. (2) uartb status register (ubstr) this register indicates the transfer status during tr ansmission and the contents of a reception error. the status flag of this register, which indicates the transfe r status during transmission, indicates the data retention status of the transmit shift register and the transmit data register (the ub tx register in the single mode or transmit fifo in the fifo mode). each reception erro r flag is set to 1 when a reception error occurs, and cleared to 0 when 0 is written to the ubstr register. (3) uartb control register 2 (ubctl2) this register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of uartb. (4) uartb fifo control register 0 (ubfic0) this register is used to select the operation mode of uartb, clear the transmi t fifo/receive fifo that becomes valid in the fifo mode, an d specify the timing mode in whic h the transmission enable interrupt request signal (intubtit)/reception end inte rrupt request signal (intubtir) occurs. (5) uartb fifo control register 1 (ubfic1) this register is valid in the fifo mode. it generates a reception timeout interrupt request signal (intubtito) if data is stored in the receive fifo when the next data does not come (start bit is not detected) even after the reception wait time of the next data ha s elapsed after the stop bit has been received. (6) uartb fifo control register 2 (ubfic2) this register is valid in the fifo mode. it is used to set the timi ng to generate the transmission enable interrupt request signal (intubtit) /reception end interrupt request signal (intubtir), using the number of data transmitted or received as a trigger.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 750 (7) uartb fifo status register 0 (ubfis0) this register is valid in the fifo mode. the number of bytes of data stored in the receive fifo can be read from this register. (8) uartb fifo status register 1 (ubfis1) this register is valid in the fifo mode. the number of empty bytes of the transmit fifo can be read from this register. (9) receive shift register this is a shift register that converts the serial data that was input to the rxdb pin into parallel data. one byte of data is received, and if a stop bit is detected, the received data is trans ferred to the receive data register. this register cannot be directly manipulated. (10) uartb receive data register ap ( ubrxap), uartb receive data register (ubrx) the receive data register holds receiv e data. in the single mode, the 8-bit 1-stage ubrx register is used. the 16-bit 16-stage receive fifo (ubrxap registe r) is used in the fifo mode. the receive data is stored in the lower 8 bits of the receive fifo (ubrxap registe r) and the error information of the received data is stored in the high er 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo mode, the error data can be identified by reading the ubrxap register in 16-bit (halfword) units (error informati on is appended as ubpef bit = 1 or ubfef bit = 1). when the lower 8 bits of the ubrxap register are read in 8-bit (byte) uni ts, the higher 8 bits are di scarded. therefore, if no error has occurred, only the receive data of the ubr xap register can be read successively by being read in 8-bit (byte) units in the same way as the ubrx register. when 7-bit length data is received with the lsb first, the received data is transferred to bits 6 to 0 of the receive data register from the lsb (b it 0), with the msb (bit 7) always being 0. when data is received with the msb first, the received data is transferred to bits 7 to 1 of the receive data regi ster from the msb (bit 7), with the lsb (bit 0) always being 0. if an overrun error oc curs, the receive data at that time is not transferred to the receive data register. while reception is enabled, the received data is transfe rred from the receive shift register to the receive data register, in synchronization with the shift-in processing of one frame. a reception end interrupt request signal (intubtir) is generated by transferring the data to the ubrx register in the single mode, or transferring the number of receive data set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits to receive fifo in the fifo mode. if data is stored in receive fifo when the next data does not come (start bit is not detec ted) after the next data reception wait time specified by the ubfic1.ubtc4 to ubfic1.ubtc0 bits has elaps ed in the fifo mode, a re ception timeout interrupt request signal (intub tito) is generated. (11) transmit shift register this is a shift register that converts the parallel data that was transferred from the transmit data register into serial data. when one byte of data is transferred from the transmit dat a register, the transmit shift register data is output from the txdb pin. this register cannot be directly manipulated.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 751 (12) uartb transmit data register (ubtx) the transmit data register is a bu ffer for transmit data. the 8-bit 1-stage ubtx register is used as this buffer in the single mode. in the fifo mode, the 8-bit 16-stage transmit fifo is used. when 7-bit length data is transmitted with the lsb first, bi ts 6 to 0 of the transmit data register are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always bei ng 0. when data is transmitted with the msb first, bits 7 to 1 of the transmit data register ar e transmitted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. in the single mode, transmission is st arted by writing transmit data to the ubtx register while transmission is enabled (ubctl0.ubtxe bit = 1). when writing the tr ansmit data to the ubtx register is enabled (when 1- byte data is transferred from the ubtx register to t he transmit shift register), a transmission enable interrupt request signal (intubtit) is generated. in the fifo mode, transmission is star ted by writing at least the number of transmit data set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits and 16 bytes or less to transmit fifo and then enabling transmission (ubtxe bit = 1). when the number of trans mit data set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits have been transferred from transmit fi fo to the transmit shift register (transmit data of the number set as the trigger can be written), a tr ansmission enable interrupt request signal (intubtit) is generated. in the fifo m ode, a fifo transmission enable interrupt request signal (intubtif) is generated when there is no more data in transmit fifo and the tr ansmit shift register (when fifo and the register become empty). (13) timeout counter this counter is used to recognize that data exists (remains) in receive fifo when the number of received data does not reach the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits, and is valid only in the fifo mode. if data is stored in receive fifo when the next data does not come (start bit is not detected) after the next data reception wait time specified by the ubfic1.ubtc4 to ubfic1.ubtc0 bits has elapsed after the stop bit has been received, a reception timeout inte rrupt request signal (i ntubtito) is generated. (14) sampling block this block samples the rxdb signal at the rising edge of the input clock (f xx ). if the same sampling value is detected two times, output of the match detector changes, and the value is sampled as input data. data of less than one clock width is judged as noise and is not transmitted to the internal circuitry.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 752 15.4 control registers (1) uartb control register 0 (ubctl0) the ubctl0 register controls the transfer operations of uartb. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. cautions 1. when using uartb, set the external pi ns related to the uartb function in the alternate- function mode, set uartb control register 2 (ubctl2). then set the ubpwr bit to 1 before setting the other bits. 2. be sure to input a high level to the rxdb pin when setti ng the external pins related to the uartb function in the alternate-function mode . if a low level is input, it is judged that a falling edge is input after the ubrxe bit has been set to 1, and reception may be started. remark when reception is disabled, the receive shift r egister does not detect a start bit. no shift-in processing or transfer processing to the receive dat a register is performed, and the contents of the receive data register are retained. when reception is enabled, the receive shift oper ation starts, in synchronization with the detection of the start bit, and when the reception of one fram e is completed, the contents of the receive shift register are transferred to the receive data register. a reception end interrupt request signal (intubti r) is also generated, in synchronization with the transfer to the receive data register (in fifo m ode, transfer triggered by reaching set number of receive data). if data is stored in receive fifo when the next dat a does not come (start bit is not detected) after the next data reception wait time specified by the ubfic1.ubtc4 to ubfic1.ubtc0 bits has elapsed in the fifo mode, a reception timeout in terrupt request signal (intubtito) is generated.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 753 (1/2) ubpwr ubctl0 ubtxe ubrxe ubdir ubps1 ubps0 ubcl ubsl 32 1 after reset: 10h r/w address: fffffa40h 0 <4> <5> <6> <7> transmission is disabled transmission is enabled ubtxe 0 1 transmission enable ? on startup, set the ubpwr bit to 1 and then set the ubtxe bit to 1. to stop transmission, clear the ubtxe bit to 0 and then the ubpwr bit to 0. ? when the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the ubtxe bit is set to 1 again after an interval of two cycles of f xx has elapsed since the ubtxe bit was cleared to 0. stops supply of clocks to uartb supplies clocks to uartb ubpwr 0 1 operation clock control to uartb ? when the ubpwr bit is cleared to 0, the uartb can be asynchronously reset. ? when the ubpwr bit = 0, uartb is in a reset state. therefore, to operate uartb, the ubpwr bit must be set to 1. ? when the ubpwr bit is changed from 1 to 0, all registers of uartb are initialized. when the ubpwr bit is set to 1 again, the uartb registers must be set again. ? the txdb pin output is high level when the ubpwr bit is cleared to 0. reception is disabled reception is enabled ubrxe 0 1 reception enable ? on startup, set the ubpwr bit to 1 and then set the ubrxe bit to 1. to stop reception, clear the ubrxe bit to 0 and then the ubpwr bit to 0. ? when the reception unit status is to be initialized, the reception status may not be able to be initialized unless the ubrxe bit is set to 1 again after an interval of two cycles of f xx has elapsed since the ubrxe bit was cleared to 0.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 754 (2/2) msb transfer first lsb transfer first ubdir 0 1 specification of transfer direction mode (msb/lsb) ? clear the ubpwr bit or ubtxe and ubrxe bits to 0 before changing the setting of the ubdir bit. do not output a parity bit output 0 parity output odd parity output even parity receive with no parity receive as 0 parity judge as odd parity judge as even parity ubps1 0 0 1 1 parity selection during transmission parity selection during reception ubps0 0 1 0 1 ? clear the ubtxe and ubrxe bits to 0 before overwriting the ubps1 and ubps0 bits. ? if ?0 parity? is selected for reception, no parity judgment is made. therefore, no error interrupt is generated because the ubstr.ubpe bit is not set to 1. 7 bits 8 bits ubcl 0 1 specification of data character length of 1-frame transmit/receive data clear the ubtxe and ubrxe bits to 0 before overwriting the ubcl bit. 1 bit 2 bits ubsl 0 1 specification of stop bit length of transmit data ? clear the ubtxe bit to 0 before overwriting the ubsl bit. ? since reception always operates by using a single stop bit length, the ubsl bit setting does not affect receive operations. remark for details of parity, see 15.7.6 parity types and corresponding operation .
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 755 (2) uartb status register (ubstr) the ubstr register indicates the tr ansfer status and reception error contents while uartb is transmitting data. the status flag that indicates the tran sfer status during transmission indica tes the data retention status of the transmit shift register and transmit dat a register (the ubtx register in t he single mode or transmit fifo in the fifo mode). the status flag that indicates a recept ion error holds its status until it is cleared to 0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution when the ubctl0.ubpwr bit or ubctl0.ubrxe bi t is set to 0, or when 0 is written to the ubstr register, the ubstr.ubovf, ubstr. ubpe, ubstr.ubfe, and ubstr.ubove bits are cleared to 0. (1/2) ubtsf ubstr 0 0 0 ubovf ubpe ubfe ubove 3 <2> <1> after reset: 00h r/w address: fffffa44h <0> 4 5 6 <7> overflow did not occur. overflow occurred (during reception). ? in single mode (ubfic0.ubmod bit = 0) data to be transferred to the transmit shift register and ubtx register does not exist (cleared (0) when ubctl0.ubpwr bit = 0 or ubctl0.ubtxe bit = 0). ? in fifo mode (ubfic0.ubmod bit = 1) data to be transferred to the transmit shift register and transmit fifo does not exist (cleared (0) when ubctl0.ubpwr bit = 0 or ubctl0.ubtxe bit = 0). ? in single mode (ubfic0.ubmod bit = 0) data to be transferred to the transmit shift register or ubtx register exists (transmission in progress). ? in fifo mode (ubfic0.ubmod bit = 1) data to be transferred to the transmit shift register and transmit fifo exists (transmission in progress). ubovf 0 1 overflow flag ? the ubovf bit is valid only in the fifo mode (when ubfic0.ubmod bit = 1), and invalid in the single mode (when ubfic0.ubmod bit = 0). ? if an overflow occurs, the received data is not written to receive fifo but discarded. the value of the ubtsf bit is reflected after two periods of f xx have elapsed, after the transmit data is written to the ubtx register. therefore, exercise care when referencing the ubtsf bit after transmit data has been written to the ubtx register. ubtsf 0 1 transfer status flag
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 756 (2/2) parity error did not occur. parity error occurred (during reception). ubpe 0 1 parity error flag ? the ubpe bit is valid only in the single mode (when ubfic0.ubmod bit = 0), and invalid in the fifo mode (when ubfic0.ubmod bit = 1). ? the operation of the ubpe bit differs according to the settings of the ubctl0.ubps1 and ubctl0.ubps0 bits. framing error did not occur. framing error occurred (during reception). ubfe 0 1 framing error flag ? the ubfe bit is valid only in the single mode (when ubfic0.ubmod bit = 0), and invalid in the fifo mode (when ubfic0.ubmod bit = 1). ? only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. overrun error did not occur. overrun error occurred (during reception). ubove 0 1 overrun error flag ? the ubove bit is valid only in the single mode (when ubfic0.ubmod bit = 0), and invalid in the fifo mode (when ubfic0.ubmod bit = 1). ? when an overrun error occurs, the next receive data value is not written to the ubrx register and the data is discarded.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 757 (3) uartb control register 2 (ubctl2) the ubctl2 register is used to specify the division ra tio by which to control the baud rate (serial transfer speed) of uartb. this register can be read or written in 16-bit units. reset sets this register to ffffh. caution when rewriting the ubbrs15 to ubbrs0 bi ts of this register, set the ubctl0.ubtxe and ubctl0.ubrxe bits to 0 or clear the ubctl0.ubpwr bit to 0. 14 ub brs 14 13 ub brs 13 12 ub brs 12 2 ub brs 2 3 ub brs 3 4 ub brs 4 5 ub brs 5 6 ub brs 6 7 ub brs 7 8 ub brs 8 9 ub brs 9 10 ub brs 10 11 ub brs 11 15 ub brs 15 1 ub brs 1 0 ub brs 0 ubctl2 after reset: ffffh r/w address: fffffa42h remark for the ubbrs15 to ubbrs0 bits, see table 15-2 division value of 16-bit counter . table 15-2. division value of 16-bit counter ub brs 15 ub brs 14 ub brs 13 ub brs 12 ub brs 11 ub brs 10 ub brs 9 ub brs 8 ub brs 7 ub brs 6 ub brs 5 ub brs 4 ub brs 3 ub brs 2 ub brs 1 ub brs 0 k output clock selected 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 4 f xx /k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 f xx /k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 5 f xx /k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 6 f xx /k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 65532 f xx /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 65533 f xx /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 65534 f xx /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 65535 f xx /k remarks 1. f xx : peripheral clock 2. k: value set by the ubctl2.ubbrs15 to ub ctl2.ubbrs0 bits (k = 4, 5, 6, ?, 65535) 3. x: don?t care
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 758 (4) uartb transmit data register (ubtx) the ubtx register is used to set transmit data. it functions as the 8-bit 1-stage ubtx register, in the single mode (ubfic0.ubmod bit = 0), and as the 8-bit 16-stage transmit fifo in the fifo mode (ubfic0.ubmod bit = 1). in the single mode, transmission is st arted by writing transmit data to the ubtx register when transmission is enabled (ubctl0.ubtxe bit = 1). when data can be writt en to the ubtx register (when 1 byte of data is transferred from the ubtx register to the transmit sh ift register), a transmission enable interrupt request signal (intubtit) is generated. in the fifo mode, transmission is started by enabling tr ansmission (ubtxe bit = 1) after writing at least the number of transmit data set as the trigger by the ubfi c2.ubtt3 to ubfic2.ubtt0 bits and 16 bytes or less to transmit fifo. when the number of transmit data set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits have been transferred from transmit fi fo to the transmit shift register (transmit data of the number set as the trigger can be written to trans mit fifo), a transmission enable interrupt request signal (intubtit) is generated. in the fifo mode, a fifo transmission enable interrupt request signal (intubtif) is generated when there is no more data in transmit fi fo and the transmit shift register (when the fifo and register become empty). for the generation timing of the interrupt, see 15.5 interrupt request signals . when 7-bit length data is transmitted with the lsb first, bi ts 6 to 0 of the transmit data register are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always bei ng 0. when data is transmitted with the msb first, bits 7 to 1 of the transmit data register ar e transmitted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. this register is write-only in 8-bit units. data is written to the transmit data register. reset sets this register to ffh. ubtd7 ubtx ubtd6 5 ubtd5 ubtd4 3 ubtd3 2 ubtd2 1 ubtd1 ubtd0 0 4 6 7 after reset: ffh w address: fffffa48h
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 759 (5) uartb receive data register ap ( ubrxap), uartb receive data register (ubrx) these registers store parallel data c onverted by the receive shift regist er. they function as the 8-bit 1- stage ubrx register, in the single mode (u bfic0.ubmod bit = 0), and as the 16-bit 16-stage receive fifo (ubrxap register) in the fifo m ode (ubfic0.ubmod bit = 1). the receive data is stored in the lower 8 bits of the receive fifo (ubrxap registe r) and the error information of the received data is stored in the high er 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo m ode, the ubrxap register is read in 16-bit (halfword) units. in this way, the flag of the data stored in rece ive fifo can be checked (error information is appended as ubpef bit = 1 or ubfef bit = 1), so that the error data can be recogn ized (when the lower 8 bits of the ubrxap register are read in 8-bit (byte) units, the higher 8 bits are di scarded. therefore, if no error has occurred, the receive data of the ubrxap register can be read successively by being read in 8-bit (byte) units in the same way as the ubrx register). if reception is enabled (ubctl0.ubrxe bit = 1), the receiv e data is transferred from the receive shift register to the receive data register, in synchronization with the co mpletion of the shift-in processing of one frame. by transferring the receive data to the ubrx register in the single mode or by transferring the number of receive data set as the trigger by th e ubfic2.ubrt3 to ubfic2 .ubrt0 bits to the rece ive fifo in the fifo mode, a reception end interrupt request signal (intubti r) is generated. if data is stored in receive fifo when the next data does not come (start bit is not detec ted) even after the next data reception wait time specified by the ubfic1.ubtc4 to ubfic1.ubtc0 bits has elapsed in the fifo mode, a reception timeout interrupt request signal (i ntubtito) is generated. for information about the timing for generating these interrupt requests, see 15.5 interrupt request signals . if data is received with the lsb first when the data l ength is specified as 7 bits, the received data is transferred to bits 6 to 0 of the receive data register fr om the lsb (bit 0), with the msb (bit 7) always being 0. if data is received with the m sb first, it is transferred to bits 7 to 1 of the receive data register from the msb (bit 7) with the lsb (bit 0) always bei ng 0. however, if an overrun error o ccurs, the receive data at that time is not transferred to the receive data register. the ubrxap register is read-only in 16-bit units. ho wever, the lower 8 bits of the ubrxap register are read-only in 8-bit units. the ubrx register is read-only in 8-bit units. in addition to reset input, the value of these registers can be set to ffh in the single mode or to 00ffh in the fifo mode, by clearing the ubctl0.ubpwr bit to 0. cautions 1. the ubpef and ubfef bits cannot be read because these re gisters serve as 8-bit registers in the single mode. 2. when no reception error has occurred in the fifo mode , the receive data of the ubrxap register can be read successively by reading the lower 8 bits of the ubrxap register in 8-bit (byte) units. an 8-bit access to the higher 8 bits is prohibited. if they are accessed, the operati on is not guaranteed.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 760 cautions 3. do not perform the following opera tions when debugging a system that uses the single mode. ? setting a break for an instruction immedi ately after the ubrx register is read ? setting a break before dma transfer with th e ubrx register specified as the transfer source is ended ? setting a break before end of reception of th e next data after reception of data and reading the ubrx register, and checking the ubrx register in the i/o register window of the debugger if any of these operations is performe d, an overrun error may occur during the subsequent reception. 14 0 13 0 12 0 2 ub rd2 3 ub rd3 4 ub rd4 5 ub rd5 6 ub rd6 7 ub rd7 8 ub fef 9 ub pef 10 0 11 0 15 0 1 ub rd1 0 ub rd0 ubrxap after reset: 00ffh r address: fffffa46h 2 ubrd2 3 ubrd3 4 ubrd4 5 ubrd5 6 ubrd6 7 ubrd7 1 ubrd1 0 ubrd0 ubrx after reset: ffh r address: fffffa46h no framing error framing error occurs (during reception). ubfef 0 1 framing error flag ? the ubfef bit is valid only in the fifo mode (ubfic0.ubmod bit = 1), and is invalid in the single mode (ubfic0.ubmod bit = 0). ? only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. no parity error parity error occurs (during reception). ubpef 0 1 parity error flag ? the ubpef bit is valid only in the fifo mode (ubfic0.ubmod bit = 1), and is invalid in the single mode (ubfic0.ubmod bit = 0). ? the operation of the ubpef bit differs depending on the set values of the ubctl0.ubps1 and ubctl0.ubps0 bits. stores receive data. ubrd7 to ubrd0
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 761 (6) uartb fifo control register 0 (ubfic0) the ubfic0 register is used to sele ct the operation mode of uartb and the functions that become valid in the fifo mode (ubmod bit = 1). in the fifo mode, it clears transmit fifo/receive fifo and specifies the timing mode in which the transmission enable interrupt request signal (intubtit) /reception end interrupt request signal (intub tir) is generated. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) ubmod ubfic0 0 0 0 ubtfc ubrfc ubitm ubirm 32 1 after reset: 00h r/w address: fffffa4ah 0 4 5 6 7 normal status clear (this bit automatically returns to 0 after transmit fifo is cleared.) ubtfc 0 1 transmit fifo clear trigger bit ? the ubtfc bit is valid only in the fifo mode (ubmod bit = 1), and is invalid in the single mode (ubmod bit = 0). ? when 1 is written to the ubtfc bit, the pointer to transmit fifo is cleared to 0. in the pending mode (ubitm bit = 0), the interrupt request signal (intubtit) held pending is cleared note . however, bit 7 (utif) of the interrupt control register (utic) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubtfc bit, the status is retained. no operation, such as clearing or setting, is executed. ? when writing 1 to the ubtfc bit, be sure to clear the ubctl0.ubtxe bit to 0 (disabling transmission). if 1 is written to the ubtfc bit when the ubtxe bit is 1 (transmission enabled), the operation is not guaranteed. single mode fifo mode ubmod 0 1 specification of uartb operation mode note after transmit fifo is cleared (ub tfc bit = 1), accessing the registers related to uartb is prohibited for the duration of four cycles of f xx or until clearing the ubtfc bit (automatic recovery) is confirmed by reading the ubfic0 register. if these register s are accessed, the operat ion is not guaranteed. remark f xx : peripheral clock
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 762 (2/2) normal status clear (this bit automatically returns to 0 after receive fifo is cleared.) ubrfc 0 1 receive fifo (ubrxap) clear trigger bit in the fifo mode, the intubtit signal is generated as soon as transmit data of the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits have been transferred from transmit fifo to the transmit shift register. after the intubtit signal request has been generated, specify the timing of actually generating the intubtit signal as the pending mode or pointer mode. for details, see 15.6 (2) pending mode/pointer mode . pending mode pointer mode ubitm 0 1 specification of intubtit interrupt generation timing in fifo mode pending mode pointer mode ubirm 0 1 specification of intubtir interrupt generation timing in fifo mode ? the ubrfc bit is valid only in the fifo mode (ubmod bit = 1), and is invalid in the single mode (ubmod bit = 0). ? when 1 is written to the ubrfc bit, the pointer to receive fifo is cleared to 0. in the pending mode (ubirm bit = 0), the interrupt request signal (intubtir) held pending is cleared note . however, bit 7 (urif) of the interrupt control register (uric) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubrfc bit, the status is retained. no operation, such as clearing or setting, is executed. ? when writing 1 to the ubrfc bit, be sure to clear the ubctl0.ubrxe bit to 0 (disabling reception). if 1 is written to the ubrfc bit when the ubrxe bit is 1 (reception enabled), the operation is not guaranteed. in the fifo mode, the intubtir signal is generated as soon as receive data of the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits have been transferred from the receive shift register to receive fifo. after the intubtir signal request has been generated, specify the timing of actually generating the intubtir signal as the pending mode or pointer mode. for details, see 15.6 (2) pending mode/pointer mode . note after receive fifo (ubrxap) is cleared (ubrfc bi t = 1), accessing the registers related to uartb is prohibited for the duratio n of four cycles of f xx or until clearing the ubrfc bit (automatic recovery) is confirmed by reading the ubfic0 r egister. if these registers are accessed, the operation is not guaranteed. remark f xx : peripheral clock
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 763 (7) uartb fifo control register 1 (ubfic1) the ubfic1 register is valid in the fifo mode (ubfic0.ubmod bit = 1) . it generates a reception timeout interrupt request signal (intubtito) if data is stored in receive fifo when the next data does not come (start bit is not detected) after the lapse of the time set by the ubtc4 to ubtc0 bits (next data reception wait time), after the stop bit has been received. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ubtce ubfic1 0 0 ubtc4 ubtc3 ubtc2 ubtc1 ubtc0 654321 after reset: 00h r/w address: fffffa4bh 7 0 32 bytes (32 8/baud rate) 31 bytes (31 8/baud rate) 30 bytes (30 8/baud rate) 29 bytes (29 8/baud rate) ? ? ? 4 bytes (4 8/baud rate) 3 bytes (3 8/baud rate) 2 bytes (2 8/baud rate) 1 byte (1 8/baud rate) ubtc3 0 0 0 0 ? ? ? 1 1 1 1 ubtc4 0 0 0 0 ? ? ? 1 1 1 1 next data reception wait time ubtc2 0 0 0 0 ? ? ? 1 1 1 1 ubtc1 0 0 1 1 ? ? ? 0 0 1 1 disable use of timeout counter function. enable use of timeout counter function. ubtce 0 1 specification of timeout counter function disable/enable when counting up of the reception wait time, set by the ubtc4 to ubtc0 bits, is complete, the count value of the timeout counter is cleared to 0, regardless of the status of the data stored in receive fifo. when the next start bit is later detected, counting is started again from the stop bit of that data. ubtc0 0 1 0 1 ? ? ? 0 1 0 1
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 764 (8) uartb fifo control register 2 (ubfic2) the ubfic2 register is valid in the fifo mode (ubfic 0.ubmod bit = 1). it sets the timing of generating an interrupt, using the number of transmit/receive data as a trigger. when data is transmitted, the number of data transferred from transmit fifo is specified as th e condition of generating the interrupt. when data is received, the number of data stored in receive fifo is specified as the interr upt generation condition. this register can be read or written in 16-bit units. when the higher 8 bits of the ubfic2 register can be used as the ubfic2h register and the lower 8 bits, as the ubfic2l register, these registers ca n be read or written in 8-bit units. reset sets the ubfic2 register to 0000h an d the ubfic2h and ubfic2l registers to 00h. caution be sure to set the ubctl0.ubtxe bit (to disable transmission) and ubctl0.ubrxe bit (to disable reception) to 0 before wr iting data to the ubfic2 register . if data is written to the ubfic2 register with the ubtxe or ubrxe bit set to 1, the operation is not guaranteed. (1/2) ubtt2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ubtt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ubtt1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ubtt0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14 0 13 0 12 0 2 ub rt2 3 ub rt3 4 0 5 0 6 0 7 0 8 ub tt0 9 ub tt1 10 ub tt2 11 ub tt3 15 0 1 ub rt1 0 ub rt0 ubfic2 after reset: 0000h r/w address: fffffa4ch 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes pointer mode pending mode ? set the number of transmit fifo transmit data to be the trigger. ? each time data of the specified number has shifted out from transmit fifo to the transmit shift register, the intubtit signal is generated. in the pending mode (ubfic0.ubitm bit = 0), the intubtit signal is generated under the conditions of the pending mode. ? in the pointer mode (ubfic0.ubitm bit = 1), the number of transmit data set as the trigger can be only 1 byte (ubtt3 to ubtt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. settable setting prohibited settable number of data of transmit fifo set as trigger
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 765 (2/2) ubrt2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ubrt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ubrt1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ubrt0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes ? set the number of receive fifo receive data to be the trigger. ? each time data of the specified number has been stored from the receive shift register to receive fifo, the intubtir interrupt is generated. in the pending mode (ubfic0.ubirm bit = 0), the intubtir signal is generated under the conditions of the pending mode. ? in the pointer mode (ubfic0.ubirm bit = 1), the number of receive data set as the trigger can be only 1 byte (ubrt3 to ubrt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. pointer mode pending mode settable setting prohibited settable number of data of transmit fifo set as trigger
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 766 (9) uartb fifo status register 0 (ubfis0) the ubfis0 register is valid in the fifo mode (ubfic 0.ubmod bit = 1). it is used to read the number of bytes of the data stored in receive fifo. this register is read-only in 8-bit units. reset sets this register to 00h. 0 ubfis0 0 0 ubrb4 ubrb3 ubrb2 ubrb1 ubrb0 654321 after reset: 00h r address: fffffa4eh 7 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes invalid ubrb3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ubrb4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 receive fifo pointer ubrb2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ubrb1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ubrb0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 other than above indicates the number of bytes (readable bytes) of the data stored in receive fifo as a receive fifo pointer.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 767 (10) uartb fifo status register 1 (ubfis1) the ubfis1 register is valid in t he fifo mode (ubfic0.ubmod bit = 1). this register can be used to read the number of empty bytes of transmit fifo. this register is read-only in 8-bit units. reset sets this register to 10h. caution the values of the ubtb4 to ubtb0 bits are reflected after tran smit data has been written to the ubtx register and then time of two cycles of f xx has passed. theref ore, care must be exercised when referencing the ubfis1 register after transmit data has been written to the ubtx register. 0 ubfis1 0 0 ubtb4 ubtb3 ubtb2 ubtb1 ubtb0 654321 after reset: 10h r address: fffffa4fh 7 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes invalid ubtb3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ubtb4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 transmit fifo pointer ubtb2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ubtb1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ubtb0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 setting prohibited indicates the number of empty bytes of transmit fifo (bytes that can be written) as a transmit fifo pointer.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 768 15.5 interrupt request signals the following five types of interrupt requests are generated from uartb. ? reception error interrupt request signal (intubtire) ? reception end interrupt request signal (intubtir) ? transmission enable interrupt request signal (intubtit) ? fifo transmission end interrupt request signal (intubtif) ? reception timeout interrupt request signal (intubtito) the default priorities among these five types of interrupt requests is, from high to low, reception error interrupt request signal, reception end interrupt request signal, trans mission enable interrupt request signal, fifo transmission end interrupt request signal, and reception timeout interrupt request signal. table 15-3. generated inte rrupts and default priorities interrupt priority reception error 1 reception end 2 transmission enable 3 fifo transmission end 4 reception timeout 5 (1) reception error interrupt request signal (intubtire) (a) single mode when reception is enabled, a reception error interrupt request signal is generated according to the logical or of the three types of reception errors (parity error, framing error, overrun error) explained for the ubstr register. when reception is disabled, no reception erro r interrupt request signal is generated. (b) fifo mode when reception is enabled, a reception error interrupt request signal is generated according to the logical or of the three types of reception errors (parity er ror, framing error, overflow error) explained for the ubstr register. when reception is disabled, no reception erro r interrupt request signal is generated.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 769 (2) reception end interrupt request signal (intubtir) (a) single mode when reception is enabled, a reception end interrupt r equest signal is generated if data is shifted into the receive shift register and stored in the ubrx register (if the receive data can be read). when reception is disabled, no reception en d interrupt request signal is generated. (b) fifo mode when reception is enabled, a reception end interrupt r equest signal is generated if data is shifted into the receive shift register and receive data of the num ber set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits is transferred to receive fifo (i f receive data of the spec ified number can be read). when reception is disabled, no reception en d interrupt request signal is generated. (3) transmission enable interr upt request signal (intubtit) (a) single mode the transmission enable interrupt request signal is gener ated if transmit data of one frame, including 7 or 8 bits of characters, is shifted out from the transmi t shift register and the ubtx register becomes empty (if transmit data can be written). (b) fifo mode the transmission enable interrupt request signal is ge nerated if transmit data of the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits is transferred to the transmit shift register from transmit fifo (if transmit data of t he specified number can be written). (4) fifo transmission end inte rrupt request signal (intubtif) (a) single mode cannot be used. (b) fifo mode the fifo transmission end interrupt request signal is generated when no more data is in transmit fifo and the transmit shift register (when the fifo and regi ster become empty). after the fifo transmission end interrupt request signal has occurred, clear the in terrupt request signal (intubtit) held pending in the pending mode (ubfic0.ubitm bit = 0) by clearing the fifo (ubf ic0.ubtfc bit = 1). caution if the fifo transmission end interrupt re quest signal is generated (all transmit data are not transmitted) because writing the next tran smit data to transmit fifo is delayed, do not clear the fifo.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 770 (5) reception timeout interrupt request signal (intubtito) (a) single mode cannot be used. (b) fifo mode the reception timeout interrupt request signal is gener ated if data is stored in receive fifo when the next data does not come (start bit is not detected) even a fter the next data reception wait time specified by the ubfic1.ubtc4 to ubfic1.ubtc0 bits has elapsed, when the timeout counter function is used (ubfic1.ubtce bit = 1). the reception timeout interrupt request signal is not generated while reception is disabled. if receive data of the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits is not received, the timing of reading the number of rece ive data less than the specified number can be set by the reception timeout interrupt request signal. since the timeout counter starts counting at start bit detection, a receive timeout interrupt request signal does not occur if data of 1 character has not been received.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 771 15.6 control modes (1) single mode/fifo mode the single mode or fifo mode can be se lected by using the ubfic0.ubmod bit. (a) single mode ? each of the ubrx and ubtx registers consists of 8 bits 1 stage. ? when 1 byte of data is received, the intubtir signal is generated. ? if the next reception operation of uartb is ended be fore the receive data of the ubrx register is read after the intubtir signal has been generated, t he intubtire signal is generated and an overrun error occurs. (b) fifo mode ? receive fifo (ubrxap register) consists of 16 bits 16 stages and transmit fifo consists of 8 bits 16 stages. ? receive fifo can recognize error data by reading the 16-bit ubrxap register only when a reception error (parity error or framing error) occurs. ? transmission is started when transmission is en abled (ubctl0.ubtxe bit = 1) after transmit data of at least the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits and 16 bytes or less are written to transmit fifo. ? the pending mode or pointer mode can be select ed for the generation timing of the intubtit and intubtir signals.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 772 (2) pending mode/pointer mode the pending mode or pointer mode can be selected by using the ubfic0.ubitm and ubfic0.ubirm bits in the fifo mode (ubfic0.ubmod bit = 1). if transmission is started by writ ing data of more than double the amount set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits to transmit fifo, the transmission enable interrupt request signal (intubtit) may occur more than once. the reception end interrupt request signal (intubtir) may also occur more than once if the number of receive dat a set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits is 8 bytes or less in receive fifo. in the pending or pointer mode, it can be specified how an interrupt is handled after it has been held pending. (a) pending mode (i) during transmission (w riting to transmit fifo) ? if the data of the first transmission enable inte rrupt request signal (intubtit) is not written to transmit fifo after the interrupt has occurred, t he second intubtit signal does not occur (is held pending) even if the generation condition of the second intubtit signal is satisfied (when transmit data of the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits is transferred from transmit fifo to the transmit shift register). when data for the first intubtit signal is late r written to transmit fifo, the pending intubtit signal is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubfic2.ubtt3 to ubfic2.ubtt0 bits = 0000): 15 times max. when trigger is set to 2 bytes (ubfic2.ubtt3 to ubfic2.ubtt0 bits = 0001): 7 times max. : when trigger is set to 6 bytes (ubfic2.ubtt3 to ubfic2.ubtt0 bits = 0101): 1 time max. when trigger is set to 7 bytes (ubfic2.ubtt3 to ubfic2.ubtt0 bits = 0110): 1 time max. when trigger is set to 8 bytes (ubfic2.ubtt3 to ubfic2.ubtt0 bits = 0111): 1 time max. ? in the pending mode, transmit data of the number set as the tr igger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits is always written to transmi t fifo when the transmission enable interrupt request signal (intubtit) occurs. writing data to tr ansmit fifo is prohibited if the data is more or less than the specified number. if data more or less than the specified number is written, the operation is not guaranteed. ? fix the ubfic2.ubtt3 to ubfi c2.ubtt0 bits to 0000 (set number of transmit data: 1 byte) to write transmit data to transmit fifo by dma. if any other setting is made, the operation is not guaranteed.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 773 (ii) during reception (reading from receive fifo) ? if data for the first reception end interrupt request signal (intubtir) is not read from receive fifo, the second intubtir signal does not occur (is hel d pending) even if the generation condition of the second intubtir is satisf ied (if receive data of the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits can be read from receive fifo). when data for the first intubtir signal is later read from the receive fifo, the pending intubtir signal is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubfic2.ubrt 3 to ubfic2.ubrt0 bits = 0000): 15 times max. when trigger is set to 2 bytes (ubfic2.ubrt 3 to ubfic2.ubrt0 bits = 0001): 7 times max. : when trigger is set to 6 bytes (ubfic2.ubrt 3 to ubfic2.ubrt0 bits = 0101): 1 time max. when trigger is set to 7 bytes (ubfic2.ubrt 3 to ubfic2.ubrt0 bits = 0110): 1 time max. when trigger is set to 8 bytes (ubfic2.ubrt 3 to ubfic2.ubrt0 bits = 0111): 1 time max. ? in the pending mode, receive data of the num ber set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits is always read from receiv e fifo when the reception end interrupt request signal (intubtir) occurs. reading data from receive fifo is prohibited if t he data is more or less than the specified number. if data more or less t han the specified number is read, the operation is not guaranteed. ? fix the ubfic2.ubrt3 to ubfi c2.ubrt0 bits to 0000 (set number of receive data: 1 byte) to read receive data from receive fifo by dma. if any other setting is made, the operation is not guaranteed. (b) pointer mode (i) during transmission (w riting to transmit fifo) ? each time the data of 1 byte is transferred to the transmit shift register from transmit fifo, a transmission enable interrupt request signal (intubtit) occurs. ? in the pointer mode, be sure to fix the ubfic2 .ubtt3 to ubfic2.ubtt0 bits to 0000 (set number of transmit data: 1 byte) as the number of transmit data set as the trigger for transmit fifo when the transmission enable interrupt request signal (i ntubtit) occurs. if any other setting is made, the operation is not guaranteed. ? writing transmit data to transmit fifo by dma is prohibited. the operation is not guaranteed if dma control is used. ? after the transmission enable interrupt reques t signal (intubtit) has been acknowledged, data of the number of empty bytes of tr ansmit fifo can be written to transmit fifo by referencing the ubfis1 register.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 774 (ii) during reception (reading from receive fifo) ? each time the data of 1 byte is transferred to receive fifo from the receive shift register, a reception end interrupt request signal (intubtir) occurs. ? in the pointer mode, be sure to fix the ubfic2 .ubrt3 to ubfic2.ubrt0 bits to 0000 (set number of receive data: 1 byte) as the number of receive data set as the trigger for receive fifo when the reception end interrupt request signal (intubti r) occurs. if any other setting is made, the operation is not guaranteed. ? reading receive data from receive fifo by dma is prohibited. the operat ion is not guaranteed if dma control is used. ? after the reception end interrupt request signal (intubtir) has been acknowledged, data of the number of bytes stored in receive fifo can be read from receive fifo by referencing the ubfis0 register. in some cases, however, data is not stored in receive fifo even though the intubtir signal is generated (ubfis 0.ubrb4 to ubfis0.ubrb0 bits = 0000 0). in these cases, do not read data from receive fifo. always read data from re ceive fifo when the number of bytes stored in receive fifo is 1 byte or more (ubrb4 to ubrb0 bits = other than 00000).
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 775 15.7 operation 15.7.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 15-3. the character bit length within one data frame, the type of parity, and the stop bit length are specified by uartb control register 0 (ubctl0). also, data is transferred with lsb first/msb first. figure 15-3. asynchronous serial interface tran smit/receive data format (lsb-first transfer) 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 776 15.7.2 transmit operation in the single mode (ubfic0.ubmod bit = 0), transmission is enabled when the ubctl0.u btxe bit is set to 1, and transmission is started when transmit data is written to the ubtx register. in the fifo mode (ubfic0.ubmod bit = 1), transmission is started when transmit data of at least the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits and 16 bytes or less is written to transmit fifo and then the ubtxe bit is set to 1. caution setting the ubctl0.ubtxe bit to 1 before writi ng transmit data to transmit fifo in the fifo mode is prohibited. the operation is not guaranteed if this setting is made. (1) transmission enabled state this state is set by the ubctl0.ubtxe bit. ? ubtxe = 1: transmission enabled state ? ubtxe = 0: transmission disabled state however, because this bit is also used by csib2, enable transmission after setting the cb2ctl0.cb2pwr bit to 0. since uartb does not have a cts (transmission enabled si gnal) input pin, a port should be used to confirm whether the destination is in the reception enabled state. (2) starting a transmit operation ? in single mode (ubfic0.ubmod bit = 0) in the single mode, transmission is started when tran smit data is written to the ubtx register while transmission is enabled. ? in fifo mode (ubfic0.ubmod bit = 1) in the fifo mode, transmission is star ted when transmit data of at leas t the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits and 16 by tes or less is written to transmit fifo and then transmission is enabled (ubtxe bit = 1). data in the transmit data register (ubtx register in single mode or transmit fifo in the fifo mode) is transferred to the transmit shift register when transmission is started. then, the trans mit shift register outputs data to the txdb pin sequentially beginning with th e lsb (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 777 (3) transmission interrupt request signal (a) transmission enable interr upt request signal (intubtit) ? in single mode (ubfic0.ubmod bit = 0) in the single mode, the transmission enable interrupt request signal (intubtit) occurs when transmit data can be written to the ubtx register (when 1 byte of data is transferred from the ubtx register to the transmit shift register). ? in fifo mode (ubfic0.ubmod bit = 1) in the fifo mode, the intubtit signal occurs wh en transmit data of the number set as the trigger specified by the ubfic2.ubtt3 to ubfic2.ubtt0 bits is transferred from transmit fifo to the transmit shift register (if transmit data of t he number set as the trigger can be written). ? if pending mode is specified (ubfic0.ubitm bit = 0) in fifo mode if the pending mode is specified in the fifo mode, the second intubtit signal is held pending after the first intubtit signal has occurred, until as many transmit data as the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits are written to transmit fifo, even if the generation condition of the second intubtit signal is satisfied. w hen as many transmit data as the number set as the trigger are written to transmit fifo in response to the first intubtit signal, the second pending intubtit signal is generated. ? if pointer mode is specified (ubfic0.ubitm bit = 1) in fifo mode if the pointer mode is specified in the fifo mode, the second intubtit signal occurs when the generation condition of the second intubtit signal is satisfied even if as many transmit data as the number set as the trigger by the ubfic2.ubtt3 to ub fic2.ubtt0 bits are not written to transmit fifo when the first intubtit signal occurs. (b) fifo transmission end inte rrupt request signal (intubtif) the fifo transmission end interrupt re quest signal (intubtif) occurs when no more data is in transmit fifo and the transmit shift register in the fifo mode (ubfic0.ubmod bit = 1) . after the intubtif signal has occurred, clear the pending intubtit signal in the pending mode (ubfic0.ubitm bit = 0) by clearing the fifo (ubfic0.ubtfc bit = 1). if t he intubtif signal occurs because writing the next transmit data to transmit fifo is delayed (if all transmit data have not been transmitted), do not clear the fifo. if the data to be transmitted next has not been written to the transmit data register, the transmit operation is suspended. caution in the single mode, the transmission enable interrupt re quest signal (intubtit) occurs when the ubtx register becomes empty (when 1 byte of data is transferred from the ubtx register to the transmit shi ft register). in the fifo m ode, the fifo transmission end interrupt request signal (intubtif ) occurs when data is no longe r in transmit fifo and the transmit shift register (when the fifo and register are empty). however, the intubtit signal or intubtif signal is not generated if the transmit da ta register becomes empty due to reset input.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 778 figure 15-4. timing of asynchronous serial interf ace transmission enable in terrupt request signal (intubtit) start stop d0 d1 d2 d6 d7 parity txdb (output) intubtit (output) remark in the fifo mode, the intubtit signal occurs at the above timing when as many transmit data as the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits are serially transferred. figure 15-5. timing of asynchronous serial interf ace fifo transmission end interrupt request signal (intubtif) start stop d0 d1 d2 d6 d7 parity txdb (output) intubtif (output) remark the intubtif signal occurs at the above timing when data is no longer in transmit fifo and the transmit shift register (when the fifo and register are empty).
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 779 15.7.3 continuous transmission operation ? in single mode (ubfic0.ubmod bit = 0) in the single mode, the next data can be written to the ub tx register as soon as the transmit shift register has started a shift operation. the timing of transfer can be identified by the transmission enable interrupt request signal (intubtit). by writ ing the next transmit data to the ubtx r egister via the intubtit signal within one data frame transmission period, data can be transmitt ed without an interval and an efficient communication rate can be realized. caution confirm that the ubstr.ubtsf bit is 0 be fore executing initializat ion during transmission processing. if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed. ? if pending mode is specified (ubfic0.ubitm bit = 0) in fifo mode if transmit data of at least the number set as the transmi t trigger by ubfic2.ubtt3 to ubfic2.ubtt0 bits and 16 bytes or less is written to transmit fifo, transmission starts. if the pending mode is specified in the fifo mode, as many of the next tr ansmit data as the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits c an be written to transmit fifo as soon as the transmit shift register has started shifting the last data of th e specified number of data. the timing of transfer can be identified by the intubtit signal. by writing as m any of the next transmit data as the number set as the trigger to transmit fifo or writing the data to the fifo within the transmission period of the data in transmit fifo via the intubtit signal, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubstr.ubtsf bit is 0 be fore executing initializat ion during transmission processing (this can also be done by the fifo transmission end interrupt request signal (intubtif)). if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed. to write transmit data to transmit fifo by dma, set the number of transmit data specified as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits to 1 byte; otherwise the operation will not be guaranteed. ? if pointer mode is specified (ubfic0.ubitm bit = 1) in fifo mode if the pointer mode is specified in t he fifo mode, a intubtit signal occu rs and the next data can be written to transmit fifo as soon as the transmit shift register has started shifting the number of transmit data set as the trigger. at this time, as many data as the number of empty bytes of transmit fifo can be written by referencing the ubfis1 register. the timing of transfer c an be identified by the intubtit signal. by writing as many of the next transmit dat a as the number specified as the trigger to transmit fifo or writing the data to the fifo within the transmission period of the data in tr ansmit fifo via the intu btit signal, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubstr.ubtsf bit is 0 be fore executing initializat ion during transmission processing (this can also be done by the fifo transmission end interrupt request signal (intubtif)). if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 780 15.7.4 receive operation the awaiting reception state is set by setting the ubct l0.ubpwr bit to 1 and then setting the ubctl0.ubrxe bit to 1. rxdb pin sampling begins and a start bit is detect ed. when the start bit is detected, the receive operation begins, and data is stored sequentially in the receive shift register according to the baud rate that was set. in the single mode (ubfic0.ubmod bit = 0), a receptio n end interrupt request signa l (intubtir) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the ubrx register to memory by this interrupt servicing. in the fifo mode (ubfic0.ubmod bit = 1), the intubt ir signal occurs when as many receive data as the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits are transferred to receive fifo. if the pending mode is specified (ubfic0.ubirm bit = 0) in the fifo mode, as many receive data as the number set as the trigger by the ubfic2.ubrt3 to ub fic2.ubrt0 bits can be read from receive fifo. if the pointer mode is specified (ubfic0.ubirm bit = 1) in the fifo mode, as many data as the number of bytes stored in receive fifo (0 bytes or more) can be read from receive fifo by referencing the number of receive data specified as the trigger by the ubrt3 to ubrt0 bits (1 byte) or the ubfis0 register. caution if the pointer mode is specified in the fi fo mode and if as many da ta as the number of bytes stored in receive fifo are read by referencing the ubfis0 register, no da ta may be stored in receive fifo (ubfis0.ubrb4 to ubfis0.ubrb0 bits = 00000) e ven though the reception end interrupt request signal (intubtir) has occurred. in this case, do not read data from receive fifo. be sure to read data fr om receive fifo after confirming that the number of bytes stored in receive fifo = 1 byte or more (ubr b4 to ubrb0 bits = other than 00000). (1) reception enabled state this state is set by the ubctl0.ubrxe bit. ? ubrxe = 1: reception enabled state ? ubrxe = 0: reception disabled state however, because this bit is also used by csib2, enable reception after setting the cb2ctl0.cb2pwr bit to 0 and disabling the csib2 operation. in the reception disabled state, t he reception hardware stands by in the initial state. at this time, the reception end interrupt request signal or reception e rror interrupt request signal does not occur, and the contents of the receive data register (ubrx register in the single mode or receive fifo in the fifo mode (ubrxap register)) are retained. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdb pin is sampled using the serial cl ock from uartb control register 2 (ubctl2).
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 781 (3) reception interrupt request signal (a) reception end interrupt request signal (intubtir) ? in single mode (ubfic0.ubmod bit = 0) when ubctl0.ubrxe bit = 1 and the reception of one fr ame of data is ended (the stop bit is detected) in the single mode, a reception end interrupt requ est signal (intubtir) is generated and the receive data in the receive shift register is transferre d to the ubrx register at the same time. also, if an overrun error occurs, the receive data at th at time is not transferred to the ubrx register, and a reception error interrupt reques t signal (intubtire) is generated. if a parity error or framing error occurs during the reception operation, the reception operation continues up to the position at which the stop bit is received. after completion of reception, an intubtire signal occurs (the receive data in the re ceive shift register is transferred to the ubrx register). if the ubrxe bit is reset (0) during a receive operati on, the receive operation is immediately stopped. at this time, the contents of the ubrx register remain unchanged, the contents of the uartb status register (ubstr) are cleared, and the intubtir and intubtire signals do not occur. no intubtir signal is generated when the ubrxe bit = 0 (reception is disabled). ? in fifo mode (ubfic0.ubmod bit = 1) in the fifo mode, the reception end interrupt r equest signal (intubtir) occurs when data of one frame has been received (stop bit is detected) and when as many receive data as the number specified as the trigger by the ubfic2.ubrt3 to ubfic2.ubr t0 bits are transferred from the receive shift register to receive fifo. if an overflow error occurs , the receive data is not transferred to receive fifo and the reception error interrupt request signal (intubtire) occurs. if a parity error or framing error occurs during re ception, reception contin ues up to the reception position of the stop bit. after reception has been completed, the intubtire signal occurs and the receive data in the receive shift register is transferre d to receive fifo. at this time, error in formation is appended as the ubrxap.ubpef or ubrxap.ubfef bit = 1. if the intubtire signal occurs, the error data can be recognized by reading receive fifo as a 16-bit register, ubrxap.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 782 (b) reception timeout interrupt request signal (intubtito) (only in fifo mode) when the timeout counter function (ubfic1.ubtce bit = 1) is used in the fifo mode, the reception timeout interrupt request signal (intubtito) occurs if the next data does not come even after the next data reception wait time specified by the ubfic1.ubt c4 to ubfic1.ubtc0 bits has elapsed and if data is stored in receive fifo. the intubtito signal does not occur while reception is disabled. if as many receive data as the number set as the tr igger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits are not received, the timing of reading less receiv e data than the specified number can be set by the intubtito signal. since the timeout counter starts counting at start bit detection, a receive timeout interrupt request signal does not occur if data of 1 character has not been received. figure 15-6. timing of asynchronous serial interf ace reception end interrupt re quest signal (intubtir) start d0 d1 d2 d6 d7 rxdb (input) intubtir (output) receive data register parity stop cautions 1. be sure to read all the data (the number of data indicated by the ubfis0.ubrb4 to ubfis0.ubrb0 bits) stored in the receive data register (ubrx register in the single mode or receive fifo in the fifo mode ( ubrxap register)) even when a reception error occurs. unless the receive data register is read, an overrun error occurs when the next data is received, causing the reception error status to persist. if the pending mode is specified in the fi fo mode, however, be sure to clear the fifo (ubfic0.ubrfc bit = 1) after readi ng the data stored in receive fifo. in the fifo mode, the fifo can be clear ed even without reading the data stored in receive fifo. if a parity error or framing error occurs in the fifo mode, the ubrxap register can be read in 16-bit (halfword) units. 2. data is alwa ys received with one stop bit (1). a second stop bit is ignored.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 783 15.7.5 reception error in the single mode (ubfic0.ubmod bit = 0), the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. in the fifo mode (ubfic0.ubmod bit = 1), the three types of errors that can occur during a receive operation are a parity error, framing error, and overflow error. as a result of data receptio n, the ubstr.ubpe, ubstr.ubfe , or ubstr.ubove bit is set to 1 if a parity error, framing error, or overrun error occurs in the single mode. the ubstr.ubovf bit is set to 1 if an overflow error occurs in the fifo mode. the ubrxap.ubpef or ubrxap.ubfef bit is set to 1 if a pari ty error or framing error occurs in the fifo mode. at the same time, a reception error interr upt request signal (intubtire) occurs. the contents of the error can be detected by r eading the contents of the ubstr or ubrxap register. the contents of the ubstr regi ster are reset when 0 is written to the ubovf, ubpe, ubfe, or ubove bit, or the ubctl0.ubpwr or ubctl0.ubrxe bit. t he contents of the ubrxap register are reset when 0 is written to the ubctl0.ubpwr bit. table 15-4. reception error causes error flag valid operation mode error flag reception error cause ubpe ubpe parity error the parity specification during transmission does not match the parity of the receive data ubfe ubfe framing erro r no stop bit detected ubove single mode ubove overrun error the recepti on of the next data is ended before data is read from the ubrx register ubovf ubovf overflow e rror the reception of the next data is ended while receive fifo is full and before data is read. ubpef ubpef parity error the parity specification during transmission does not match the parity of the data to be received. ubfef fifo mode ubfef framing error the stop bit is not detected when the target data is loaded.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 784 15.7.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (1) even parity (a) during transmission the parity bit is controlled so t hat the number of bits with the valu e ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1 ? within the transmit data is even: 0 (b) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (a) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1 ? within the transmit data is even: 1 (b) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 785 15.7.7 receive data noise filter the rxdb signal is sampled at the rising edge of the input clock (f xx ). if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 15-8 ). also, since the circuit is configured as shown in figure 15-7, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. figure 15-7. noise filter circuit rxdb q f xx in ld_en q in internal signal a internal signal b match detector remark f xx : peripheral clock figure 15-8. timing of rx db signal judged as noise internal signal a f xx rxdb (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match remark f xx : peripheral clock
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 786 15.8 dedicated baud rate generator (brg) a dedicated baud rate generator, which consists of a 16 -bit programmable counter, generates serial clocks during transmission/reception in uartb. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 16-bit counters exist for transmission and for recept ion. the baud rate for transmission/reception is the same at the same channel. (1) baud rate genera tor configuration figure 15-9. baud rate generator configuration clock 16-bit counter match detector baud rate ubctl2.ubbrs15 to ubctl2.ubbrs0 1/2 ubpwr, ubtxe (or ubrxe) f xx output clock remark f xx : peripheral clock (a) base clock (clock) when ubctl0.ubpwr bit = 1, the input clock (f xx ) is supplied to the transmission/reception unit. this clock is called the base clock. when the ubpwr bit = 0, the clock signal is fixed at low level.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 787 (2) serial clock generation a serial clock can be generated according to the settings of the ubctl2 register. the 16-bit counter divisor value can be selected a ccording to the ubctl2.ubbrs15 to ubctl2.ubbrs0 bits. (a) baud rate the baud rate is the value obtained according to the following formula. [bps] k 2 frequency clock base rate baud = base clock frequency = f xx k = value set according to ubctl2.ubbrs15 to ubctl2.ubbrs0 bits (k = 4, 5, 6, ..., 65535) (b) baud rate error the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is described in paragraph (4). example: base clock (f xx ) = 64 mhz = 64,000,000 hz settings of ubctl2.ubbrs15 to ubctl2.ubbrs0 bits = 0000000001100110b (k = 102) target baud rate = 312500 bps baud rate = 64 m/(2 102) = 64000000/(2 102) = 313725 [bps] error = (313725/312500 ? 1) 100 = 0.392 [%] when base clock (f xx ) = 60 mhz and k = 96, the error is 0%.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 788 (3) baud rate setting example table 15-5. baud rate ge nerator setting data (1/2) f xx = 64 mhz f xx = 60 mhz f xx = 50 mhz baud rate (bps) k (decimal) k (hexadecimal) err k (decimal) k (hexadecimal) err k (decimal) k (hexadecimal) err 300 ? ? ? ? ? ? ? ? ? 600 53333 d055h 0.001 50000 c350h 0.000 41667 a2c3h ? 0.001 1200 26667 682bh ? 0.001 25000 61a8h 0.000 20833 5161h 0.002 2400 13333 3415h 0.003 12500 30d4h 0.000 10417 28b1h ? 0.003 4800 6667 1a0bh ? 0.005 6250 186ah 0.000 5208 1458h 0.006 9600 3333 0d05h 0.010 3125 0c35h 0.000 2604 0a2ch 0.006 19200 1667 0683h ? 0.020 1563 061bh 0.000 1302 0516h 0.006 31250 1024 0400h 0.000 960 03c0h 0.000 800 0320h 0.000 38400 833 0341h 0.040 781 030dh 0.000 651 028bh 0.006 76800 417 01a1h ? 0.080 391 0187h 0.000 326 0146h ? 0.147 153600 208 00d0h 0.160 195 00c3h 0.000 163 00a3h ? 0.147 312500 102 0066h 0.392 96 0060h 0.000 80 0050h 0.000 500000 64 0040h 0.000 60 003ch 0.000 50 0032h 0.000 1000000 32 0020h 0.000 30 001eh 0.000 25 0019h 0.000 2000000 16 0010h 0.000 15 000fh 0.000 13 000dh ? 3.846 3000000 11 000bh ? 3.030 10 000ah 0.000 8 0008h 4.167 4000000 8 0008h 0.000 8 0008h ? 6.250 ? ? ? 5000000 6 0006h 6.667 6 0006h 0.000 ? ? ? 5333333 6 0006h 0.000 ? ? ? ? ? ? caution the maximum allowable fre quency of the peripheral clock (f xx ) is 64 mhz. the maximum transfer speed of the baud rate is 5.33 mbps. remark f xx : peripheral clock k: settings of ubctl2.ubbrs15 to ubctl2.ubbrs0 bits err: baud rate error [%]
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 789 table 15-5. baud rate ge nerator setting data (2/2) f xx = 40 mhz f xx = 32 mhz baud rate (bps) k (decimal) k (hexadecimal) err k (decimal) k (hexadecimal) err 300 ? ? ? 53333 d055h 0.001 600 33333 8235h 0.001 26667 682bh ? 0.001 1200 16667 411bh ? 0.002 13333 3415h 0.003 2400 8333 208dh 0.004 6667 1a0bh ? 0.005 4800 4167 1047h ? 0.008 3333 0d05h 0.010 9600 2083 0823h 0.016 1667 0683h ? 0.020 19200 1042 0412h ? 0.032 833 0341h 0.040 31250 640 0280h 0.000 512 0200h 0.000 38400 521 0209h ? 0.032 417 01a1h ? 0.080 76800 260 0104h 0.160 208 00d0h 0.160 153600 130 0082h 0.160 104 0068h 0.160 312500 64 0040h 0.000 51 0033h 0.392 500000 40 0028h 0.000 32 0020h 0.000 1000000 20 0014h 0.000 16 0010h 0.000 2000000 10 000ah 0.000 8 0008h 0.000 3000000 7 0007h ? 4.762 ? ? ? 4000000 ? ? ? ? ? ? 5000000 ? ? ? ? ? ? 5333333 ? ? ? ? ? ? caution the maximum allowable fre quency of the peripheral clock (f xx ) is 64 mhz. the maximum transfer speed of the baud rate is 5.33 mbps. remark f xx : peripheral clock k: settings of ubctl2.ubbrs15 to ubctl2.ubbrs0 bits err: baud rate error [%]
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 790 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 15-10. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartb latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable value maximum allowable value stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-10, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the ubctl2 register. if all da ta up to the final data (sto p bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ? 1 brate: uartb baud rate k: ubctl2 set value fl: 1-bit data length latch timing margin: 2 clocks minimum allowable value: fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? =
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 791 therefore, the maximum baud rate that can be re ceived at the transfer destination is as follows. brate 2 21k k 22 (flmin/11) brmax 1 + = = ? similarly, the maximum allowable value can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the minimum baud rate that can be received at the transfer destination is as follows. brate 2 21k k 20 (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartb and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 15-6. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.33 % ? 2.44 8 +3.53 % ? 3.61 16 +4.14 % ? 4.19 32 +4.45 % ? 4.48 64 +4.61 % ? 4.62 128 +4.68 % ? 4.69 256 +4.72 % ? 4.73 512 +4.74 % ? 4.74 1024 +4.75 % ? 4.75 2048 +4.76 % ? 4.76 4096 +4.76 % ? 4.76 8192 +4.76 % ? 4.76 16384 +4.76 % ? 4.76 32768 +4.76 % ? 4.76 65535 +4.76 % ? 4.76 remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: ubctl2 set value
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 792 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 15-11. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f xx yields the following equation. flstp = fl + 2/(f xx ) therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + 2/(f xx )
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 793 15.9 control flow (1) example of continuous tr ansmission processing flow in single mode (cpu control) figure 15-12. example of continuo us transmission processing flow in single mode (cpu control) set uartb-related registers yes ubtsf = 0? (ubstr) no start ubtxe = 1 (ubctl0) : enable transmission write ubtx register : write transmit data ubtxe = 0 (ubctl0) : disable transmission yes intubtit interrupt = 1? : ubtx register can be written? no yes transmission ended? : all transmit data written? : transmission ended? no end
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 794 (2) example of continuous r eception processing flow in si ngle mode (cpu control) figure 15-13. example of continuous reception processing flow in single mode (cpu control) set uartb-related registers start ubrxe = 1 (ubctl0) : enable reception error processing in single mode yes intubtire interrupt = 1? : reception error occurred? yes intubtir interrupt = 1? : 1-byte reception ended? no yes reception ended? : reception ended? no no end read ubrx register : read receive data ubrxe= 0 (ubctl0) : disable reception
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 795 (3) example of continuous tr ansmission processing flow in single mode (dma control) figure 15-14. example of continuo us transmission processing flow in single mode (dma control) set uartb/dmac-related registers note start dtfrm register = 28h : assign dma transfer destination (in the case of intubtit) and clear dfm bit yes dma ended? : dma transfer ended? no yes ubtsf = 0? (ubstr) : transmission ended? no ubtxe = 0 (ubctl0) : disable transmission end emm = 1 (dchcm) : enable dma transfer ubtxe = 1 (ubctl0) : enable transmission write ubtx register : write transmit data note in this control flow example, transmission of the first byte of the data is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh, dsaml registers). remark m = 0 to 3
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 796 (4) example of continuous r eception processing flow in si ngle mode (dma control) figure 15-15. example of continuous reception processing flow in single mode (dma control) set uartb/dmac-related registers start dtfrm register = 27h : assign dma transfer destination (in the case of intubtir) and clear dfm bit yes dma ended? : dma transfer (reception) ended? no ubrxe = 0 (ubctl0) : disable reception end emm = 1 (dchcm) : enable dma transfer ubrxe = 1 (ubctl0) : enable reception remark m = 0 to 3
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 797 (5) example of continuous tr ansmission processing flow in fifo mode (cpu control) figure 15-16. example of continuous transmissi on processing flow in fifo mode (cpu control) set uartb-related registers start write transmit fifo note 1 : write transmit data yes intubtif interrupt = 1? : transmission ended? note 2 yes intubtit interrupt = 1? : writing to transmit fifo enabled? no yes transmission ended? : writing all transmit data ended? no : transmission ended? no end ubtxe = 0 (ubctl0) write transmit fifo note 3 : disable transmission clear transmit fifo ubtxe = 1 (ubctl0) : enable transmission yes intubtif interrupt = 1? no notes 1. write more transmit data than the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits to transmit fifo. 2. this is the case where transmission is ended (transmit fifo and the transmit shift register become empty) before the next transmit data is written. to continue data transmission, clear the intubtif and intubtit signals and write the next data to transmit fifo. 3. in the pending mode (ubfic0.ubitm bit = 0), write as many transmit data as the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits of to transmit fifo. in the pointer mode (ubitm bit = 1), reference the ubfis1.ubtb4 to ubfis1.ubtb0 bits and write as many data as the number of empty bytes in transmit fifo to transmit fifo. write 16-byte data to fully use the 8-bit 16-stage fifo function.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 798 (6) example of continuous reception processing in fi fo mode (cpu control) figure 15-17. example of continuous recepti on processing in fifo mode (cpu control) set uartb-related registers start ubrxe = 1 (ubctl0) : enable reception yes intubtito interrupt = 1? : reception timeout occurred? yes intubtir interrupt = 1? : reading from receive fifo enabled? no yes reception ended? : reading all receive data ended? no no no intubtire interrupt = 1? : reception error occurred? yes end read receive fifo note 1 : read receive data error processing in fifo mode ubrxe = 0 (ubctl0) : disable reception check ubfis0 register read receive fifo note 2 : read receive data remaining in receive fifo clear receive fifo notes 1. read as many receive data as the number set as the trigger by the ubfic2.ubrt3 to ubfic2.ubrt0 bits from receive fifo in the pending mode (ubfic0.ubirm bit = 0). in the pointer mode (ubirm bit = 1), reference the ubfis0.ubrb4 to ubfis0.ubrb0 bits and read as many data as the number of bytes stored in receive fifo from receive fifo. 2. read as many data (remaining receive data less than the number set as the trigger) as the number of bytes stored in receive fifo from receive fifo by referencing the ubfis0.ubrb4 to ubfis0.ubrb0 bits.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 799 (7) example of continuous tran smission (pending mode) processing in fifo mode (dma control) figure 15-18. example of continuous transmission (pe nding mode) processing in fifo mode (dma control) set uartb/dmac-related registers note 1 start dtfrm register = 28h : assign dma transfer destination (in the case of intubtit) and clear dfm bit yes dma ended? : dma transfer ended? no yes intubtif interrupt = 1? : transmission ended? no ubtxe = 0 (ubctl0) : disable transmission end emm = 1 (dchcm) : enable dma transfer ubtxe = 1 (ubctl0) : enable transmission clear transmit fifo write transmit fifo note 2 : write transmit data notes 1. in this control flow example, transmission of the data described in note 2 is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh, dsaml registers). 2. write as many transmit data as the number set as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits (= 1 byte) to transmit fifo. remark m = 0 to 3
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 800 (8) example of continuous recepti on (pending mode) processing flow in fifo mode (dma control) figure 15-19. example of continuous reception (pending mode) processing flow in fifo mode (dma control) set uartb/dmac-related registers start dtfrm register = 27h : assign dma transfer destination (in the case of intubtir) and clear dfm bit yes dma ended? : dma transfer (reception) ended? no ubrxe = 0 (ubctl0) : disable reception end emm = 1 (dchcm) : enable dma transfer ubrxe = 1 (ubctl0) : enable reception clear receive fifo remark m = 0 to 3
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 801 (9) example of reception erro r processing in single mode figure 15-20. example of reception erro r processing flow in single mode start read ubrx register : extract receive data (error data) end clear error flag read ubstr register : check error flag caution reception can be continued by completing th is control flow before reception of the next data is ended. if the next da ta is received before this contro l flow is ended, a reception error interrupt request signal (intubtire) may o ccur even if the data has been received correctly.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 802 (10) example of reception error pr ocessing flow in fifo mode (1) figure 15-21. example of reception erro r processing flow in fifo mode (1) start ubrxe = 0 (ubctl0) note : stop reception end read ubfis0 register : check receive fifo pointer read ubrxap register : extract receive data and check error ubrfc = 1 (ubfic0) : clear receive fifo clear error flag read ubstr register : check error flag note if the error flag is cleared when ubrxe bit = 0, the ubctl0 register does not have to be set.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 803 (11) example of reception error pr ocessing flow in fifo mode (2) figure 15-22. example of reception erro r processing flow in fifo mode (2) start end read ubfis0 register : check receive fifo pointer read ubrxap register : extract receive data and check error clear error flag read ubstr register : check error flag caution reception can be continued by completing this cont rol flow before reception of the next data is ended. extract the receive data a nd check if a reception error has occurred before receive fifo becomes empty. note that this control flow is va lid only when a parity error or a framing error occurs. if an overflow e rror occurs, receive fi fo must be cleared (ubfic0.ubrfc bit = 1). if the next data is received before this c ontrol flow is ended, a reception error interrupt request signal (intubtire) may occur even if the data has been received correctly.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 804 15.10 cautions cautions concerning uartb are shown below. (1) when supply clo ck to uartb is stopped when the supply of clocks to uartb is stopped (for example, idle and stop modes), operation stops with each register retaining the value it had immediately be fore the supply of clocks was stopped. the txdb pin output also holds and outp uts the value it had imm ediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting the ubpwr bit = 0, ubrxe bit = 0, and ubtxe bit = 0. (2) caution on setting ubctl0 register ? when using uartb, set the external pins related to the uartb function to the alternate function and set the ubctl2 register. then set the ubctl0.ubpw r bit to 1 before setting the other bits. ? be sure to input a high level to the rxdb pin when setting the external pins related to the uartb function to the alternate function. if a low level is input, it is judged that a falling edge is input after the ubctl0.ubrxe bit has been set to 1, and reception may be started. (3) caution on setting ubfic2 register be sure to clear the ubctl0.ubtxe bit (to dis able transmission) and ubctl0.ubrxe bit (to disable reception) to 0 before writing data to the ubfic2 register. if data is written to the ubfic2 register with the ubtxe or ubrxe bit set to 1, the operation is not guaranteed. (4) transmission interrupt request signal in the single mode, the transmission enable interrupt request signal (intubtit) occurs when the ubtx register becomes empty (when 1 byte of data is transf erred from the ubtx register to the transmit shift register). in the fifo mode, the fifo transmission end interrupt request signal (intubtif) occurs when data is no longer in transmit fifo and the transmit shi ft register (when the fifo and register are empty). however, the intubtit signal or intubtif signal do es not occur if the transmit data register becomes empty due to reset input. (5) initialization during continu ous transmission in single mode confirm that the ubstr.ubtsf bit is 0 before executing initialization during transmission processing. if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed. (6) initialization during continuous tr ansmission (pending m ode) in fifo mode confirm that the ubstr.ubtsf bit is 0 before executing initialization during transmission processing (this can also be done by checking the fifo transmission end interrupt request signal (intubtif)). if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed. to write transmit data to transmit fifo by dma control, set the number of transmit data specified as the trigger by the ubfic2.ubtt3 to ubfic2.ubtt0 bits to 1 byte; otherwise the operation will not be guaranteed. (7) initialization during continuous tran smission (pointer m ode) in fifo mode confirm that the ubstr.ubtsf bit is 0 before executing initialization during transmission processing (this can also be done by checking the fifo transmission end interrupt request signal (intubtif)). if initialization is executed while the ubtsf bit is 1, the transmit data is not guaranteed.
chapter 15 asynchronous serial interface b (uartb) user?s manual u18279ej3v0ud 805 (8) receive operation in fifo m ode (pointer mode specified) if the pointer mode is specified in the fifo mode and if as many data as the number of bytes stored in receive fifo are read by referencing the ubfis0 register, no data may be stored in receive fifo (ubfis0.ubrb4 to ubfis0.ubrb0 bits = 00000) even though the reception end interrupt request signal (intubtir) has occurred. in this case, do not read data from receive fifo. be sure to read data from receive fifo after confirming that the number of bytes stored in receive fifo = 1 byte or more (ubrb4 to ubrb0 bits = other than 00000).
user?s manual u18279ej3v0ud 806 chapter 16 clocked serial interface b (csib) 16.1 mode switching between csib and other serial interface 16.1.1 mode switching between csib0 and uarta0 in the v850e/if3 and v850e/ig3, csib0 and uarta0 functi on alternately, and these functions cannot be used at the same time. to use csib0 and uarta0, the pmc4, pfc4, and pfce4 registers must be set in advance. caution the operations related to transmission and reception of csib0 or uarta0 are not guaranteed if the mode is switched during transm ission or reception. be sure to disable the unit that is not used. figure 16-1. mode switch settings of csib0 and uarta0 pfc4 after reset: 00h r/w address: fffff468h pfc47 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 0 1 2 3 4 5 6 7 pfce4 after reset: 00h r/w address: fffff708h pfce47 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 0 1 2 3 4 5 6 7 i/o port sckb0 i/o intp13 input setting prohibited setting prohibited pmc42 0 1 1 1 1 pfce42 0 0 1 1 pfc42 0 1 0 1 specification of alternate function of p42 pin pmc4 after reset: 00h r/w address: fffff448h pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 1 2 3 4 5 6 7 i/o port sob0 output txda0 output setting prohibited setting prohibited pmc41 0 1 1 1 1 pfce41 0 0 1 1 pfc41 0 1 0 1 specification of alternate function of p41 pin i/o port sib0 input rxda0 input pmc40 0 1 1 pfc40 0 1 specification of alternate function of p40 pin remark = don?t care
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 807 16.1.2 mode switching between csib1 and uarta2 in the v850e/if3 and v850e/ig3, csib1 and uarta2 functi on alternately, and these functions cannot be used at the same time. to use csib1 and uarta2, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of csib1 or uarta2 are not guaranteed if the mode is switched during transm ission or reception. be sure to disable the unit that is not used. figure 16-2. mode switch settings of csib1 and uarta2 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port sckb1 i/o intp11 input cs0 note output setting prohibited pmc34 0 1 1 1 1 pfce34 0 0 1 1 pfc34 0 1 0 1 specification of alternate function of p34 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port sob1 output txda2 output pmc33 0 1 1 pfc33 0 1 specification of alternate function of p33 pin i/o port sib1 input rxda2 input cs1 note output setting prohibited pmc32 0 1 1 1 1 pfce32 0 0 1 1 pfc32 0 1 0 1 specification of alternate function of p32 pin note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark = don?t care
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 808 16.1.3 mode switching between csib2 and uartb in the v850e/if3 and v850e/ig3, csib2 and uartb functi on alternately, and these fu nctions cannot be used at the same time. to use csib2 and uartb, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of csib2 or uartb are not guaranteed if the mode is switched during transm ission or reception. be sure to disable the unit that is not used. figure 16-3. mode switch settings of csib2 and uartb pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port sckb2 i/o intp12 input astb note output setting prohibited pmc37 0 1 1 1 1 pfce37 0 0 1 1 pfc37 0 1 0 1 specification of alternate function of p37 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port sob2 output txdb output setting prohibited setting prohibited pmc36 0 1 1 1 1 pfce36 0 0 1 1 pfc36 0 1 0 1 specification of alternate function of p36 pin i/o port sib2 input rxdb input setting prohibited setting prohibited pmc35 0 1 1 1 1 pfce35 0 0 1 1 pfc35 0 1 0 1 specification of alternate function of p35 pin note pd70f3454gc-8ea-a and 70f3454f1-da9-a only remark = don?t care
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 809 16.2 features { transfer rate: 8 mbps (using internal clock) { master mode and slave mode selectable { interrupt request signals: 3 ? reception end interrupt request signal (intcbnr): this signal is generated when reception is enabled and receive data is transferred from the shift register to the csibn receive data register (cbnrx) after completion of a serial transfer. ? transmission enable interrupt request signal (intcbnt ): this signal is generated when transmission is enabled in the continuous transmission or continuous transmission/reception mode and transmission data is transferred from the csibn transmit data register (cbntx) to the shift register. ? reception error interrupt request signal (intcbnre): th is signal is generated if an overrun error occurs (cbnstr.cbnove bit = 1) when reception is enabled in the continuous transfer mode. { serial clock and data phase switchable { 3-wire serial interface, transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { 3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock i/o transmission mode, reception mode, an d transmission/reception mode specifiable { double buffer for both transmission and reception { overrun error detection remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 810 16.3 configuration the following shows the block diagram of csibn. figure 16-4. block diagram of csibn cbnctl2 cbnctl0 cbnstr intcbnr sobn intcbnt cbntx so latch cbnrx cbnctl1 sibn f cclk f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 sckbn intcbnre internal bus controller phase control shift register phase control selector remarks 1. n = 0 to 2 2. f cclk : communication clock (8 mhz (max.)) csibn includes the following hardware. table 16-1. configuration of csibn item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) control registers csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr)
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 811 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception mode. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbnrxl register. reset sets this register to 0000h. in addition to reset, the cbnrx register can be initia lized by clearing (to 0) the cbnctl0.cbnpwr bit. after reset: 0000h r address: cb0rx fffffd04h, cb0rxl fffffd04h, cb1rx fffffd14h, cb1rxl fffffd14h, cb2rx fffffd24h, cb2rxl fffffd24h cbnrx (n = 0 to 2) (2) csibn transmit data register (cbntx) the cbntx register is a 16-bit buffer regist er used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to the cbntx register in the transmission mode. if the transfer data length is 8 bits, the lower 8 bits of th is register can be read or wr itten in 8-bit units as the cbntxl register. reset sets this register to 0000h. after reset: 0000h r/w address: cb0tx fffffd06h, cb0txl fffffd06h, cb1tx fffffd16h, cb1txl fffffd16h, cb2tx fffffd26h, cb2txl fffffd26h cbntx (n = 0 to 2) remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnr xe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cb nrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 812 16.4 control registers the following registers are used to control csibn. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) cbnctl0 is a register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. (1/2) cbnpwr disable csibn operation and reset the cbnstr register enable csibn operation cbnpwr 0 1 specification of csibn operation disable/enable cbnctl0 (n = 0 to 2) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h ? the cbnpwr bit controls the csibn operation and resets the internal circuit. disable transmit operation enable transmit operation cbntxe note 0 1 specification of transmit operation disable/enable ? the sobn output is low level when the cbntxe bit is 0. ? when the cbnrxe bit is cleared to 0, no reception end interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated. disable receive operation enable receive operation cbnrxe note 0 1 specification of receive operation disable/enable < > < > < > < > < > note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. caution be sure to set bits 3 and 2 to ?0?.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 813 (2/2) single transfer mode continuous transfer mode cbntms note 1 0 1 transfer mode specification communication start trigger invalid communication start trigger valid cbnsce 0 1 specification of start transfer disable/enable ? in master mode this bit enables or disables the communication start trigger. (a) in single reception mode set the cbnsce bit to 0 before reading the receive data (cbnrx register) note 2 . (b) in continuous reception mode set the cbnsce bit to 0 one communication clock before reception of the last data is ended note 3 . ? in slave mode this bit enables or disables the communication start trigger. (a) in single reception mode or continuous reception mode set the cbnsce bit to 1 note 4 . ? in single transmission or transmission/reception mode, or continuous transmission or transmission/reception mode the function of the cbnsce bit is invalid. it is recommended to set this bit to 1. ? when using single transmission or transmission/reception mode with communication type 2 or 4 (cbnctl1.cbndap bit = 1), write the transfer data to the cbntx register after checking that the cbnstr.cbntsf bit is 0. ? when using dma, use the continuous transfer mode. msb first lsb first cbndir note 1 0 1 specification of transfer direction mode (msb/lsb) notes 1. these bits can only be rewritten when the cbnpwr bit = 0. however, the cbnpwr bit can be set to 1 at the same time as these bits are rewritten. 2. if the cbnsce bit is read while it is 1, t he next communication operation is started. 3. the cbnsce bit is not set to 0 one communic ation clock before the end of the last data reception, the next communication op eration is automatically started. to start communication operation again after r eading the last data, set the cbnsce bit to 1 and perform a dummy read of the cbnrx register. 4. to start the reception, a dummy read is necessary.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 814 (a) how to use cbnsce bit (i) in single reception mode <1> when the reception of the la st data is ended with intcbnr interr upt servicing, clear the cbnsce bit to 0, and then read the cbnrx register. <2> when the reception is disabled after the rec eption of the last data has been ended, check that the cbnstr.cbntsf bit is 0, and then clear the cbnpwr and cbnrxe bits to 0. to continue reception, set the cbnsce bit to 1 and start the next receive operation by performing a dummy read of the cbnrx register. (ii) in continu ous reception mode <1> clear the cbnsce bit to 0 during reception of the last data with intcbnr interrupt servicing by the reception before the last recept ion, and then read the cbnrx register. <2> after receiving the intcbnr signal of the la st reception, read the la st data from the cbnrx register. <3> when the reception is disabled after the rec eption of the last data has been ended, check that the cbnstr.cbntsf bit is 0, and then clear the cbnpwr and cbnrxe bits to 0. to continue reception, set the cbnsce bit to 1 and start the next receive operation by performing a dummy read of the cbnrx register. caution in continuous reception mode, the ser ial clock is not stopped until the reception executed when the cbnsce bit is cleared to 0 is ended afte r the reception is started by a dummy read.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 815 (2) csibn control register 1 (cbnctl1) cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution the cbnctl1 register can be rewritte n only when the cbnc tl0.cbnpwr bit = 0. 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckbn cbnctl1 (n = 0 to 2) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset: 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 communication clock (f cclk ) f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 external clock (sckbn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) communication type 1 communication type 2 communication type 3 communication type 4 caution set f cclk to 8 mhz or lower.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 816 (3) csibn control register 2 (cbnctl2) cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. this register can be read or written in 8-bit units. reset sets register to 00h. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h 0 cbnctl2 (n = 0 to 2) 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length remark if the number of transfer bits is other than 8 or 16, prepare and use data st uffed from the lsb of the cbntx and cbnrx registers.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 817 (a) transfer data length change function the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value othe r than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether t he transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. remark n = 0 to 2 (i) transfer bit length = 10 bits, msb first 15 10 9 0 sobn sibn insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 sobn 11 12 15 sibn insertion of 0
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 818 (4) csibn status register (cbnstr) cbnstr is an 8-bit register t hat displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset sets this register to 00h. in addition to reset, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr (n = 0 to 2) 00 0 00 0 cbnove after reset: 00h r/w address: cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h ? during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cbnove 0 1 overrun error flag ? an overrun error occurs when the next reception starts without performing a cpu read of the value of the cbnrx register, upon end of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. ? the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < > caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, the written data is not transfer red because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 819 16.5 operation 16.5.1 single transfer mode (m aster mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (6) (8) no (7) intcbnr interrupt generated? transmission ended? end yes yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 820 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock output and transmit data output, gen erate the reception end interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, start the next transmission by writing the transmit dat a to the cbntx register again after the intcbnr signal is generated. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 821 16.5.2 single transfer mode (m aster mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no intcbnr interrupt generated? reception ended? end yes yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a1h start reception (1), (2), (3) (4) (5) (6) (8) (9) (10) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 822 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, out put the serial clock to the sckbn pi n, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock output and data captur ing, generate the reception end interr upt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcbnr signal is generated. (8) to read the cbnrx register without starting the next reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 823 16.5.3 single transfer mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (6) (10) no (8) transmission/reception ended? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 824 (2) operation timing sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the re ceive data of the sibn pin. (6) when transmission/reception of t he transfer data length set with the cbnctl2 register is completed, stop the serial clock output, transmit data output, and data capturing, generate the reception end interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write t he transmit data to the cbntx register again. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 825 16.5.4 single transfer mode (s lave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (4) (6) (8) no (7) intcbnr interrupt generated? transmission ended? end yes yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 826 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 07h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock input and transmit data output, gener ate the reception end interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnr signal is generated, and wait for a serial clock input. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 827 16.5.5 single transfer mode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start reception ended? end yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a1h start reception no intcbnr interrupt generated? yes no yes (1), (2), (3) (4) (5) (4) (6) (6) (8) (9) (10) sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 828 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive data of the sibn pin in syn chronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock input and data capturing, gen erate the reception end interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcbnr signal is generated, and wait for a serial clock input. (8) to end reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 829 16.5.6 single transfer mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (4) (6) (10) no (8) transmission/reception ended? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 830 (2) operation timing sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sobn pin in synchronization with the serial clock, and capture the receiv e data of the sibn pin. (6) when transmission/reception of the transfer data length set with the cbnctl2 register is completed, stop the serial clock input, transmit data output, and data capturing, gener ate the reception end interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write the trans mit data to the cbntx regist er again, and wait for a serial clock input. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 831 16.5.7 continuous transfer mode (master mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4), (8) (5) (11) no (7) transmission ended? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (6), (9) intcbnt interrupt generated? yes no (10) yes cbntsf bit = 0? (cbnstr register) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 832 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal intcbnr signal l bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when a new transmit data is written to the cbntx register before co mmunication end, the next communication is started following communication end. (9) the transfer of the transmit data from the cbnt x register to the shift register is ended and the intcbnt signal is generated. to end continuous transmission at the curr ent transmission, do not write to the cbntx register. (10) when the next transmit data is not written to t he cbntx register before tr ansfer end, stop the serial clock output to the sckbn pin after trans fer end, and clear the cbntsf bit to 0. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transmissi on mode, the reception end interrupt request signal (intcbnr) is not generated. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 833 16.5.8 continuous transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 834 (1) operation flow start yes intcbnr interrupt generated? intcbnre interrupt generated? end no no yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a3h start reception (1), (2), (3) (4) (5) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h no yes cbntsf bit = 0? (cbnstr) intcbnr interrupt generated? (9) (10) (11) (8) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 835 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sibn pin intcbnr signal cbnsce bit sobn pin l sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, output the serial clock to the sckbn pin, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception is ended, the reception end inte rrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (7) when the cbnctl0.cbnsce bit = 1 upon communi cation end, the next communication is started following communication end. (8) to end continuous reception at the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is ended, the intcbnr signal is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before co mmunication end, stop the serial clock output to the sckbn pin, and clear the cbntsf bit to 0, to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 836 16.5.9 continuous transfer mode (mast er mode, transmissi on/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /4 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 837 (1) operation flow start end yes (13) no is receive data last data? yes (12) no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e3h yes (9) no (1), (2), (3) (4) (5) (7) (7) (6), (11) (8) (13) (14) (15) (15) (10) no yes intcbnt interrupt generated? no yes cbntsf bit = 0? (cbnstr) write cbntx register yes (11) no is data being transmitted last data? start transmission/reception cbnctl0 register 00h intcbnre interrupt generated? intcbnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 838 (2) operation timing (1/2) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /4, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the receive data of the sibn pin. (6) when transfer of the transmit data fr om the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission/reception, write the tr ansmit data to the cbntx register again after the intcbnt signal is generated. (8) when one transmission/reception is ended, the re ception end interrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (9) when a new transmit data is written to the cb ntx register before comm unication end, the next communication is started following communication end. (10) read the cbnrx register. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 839 (2/2) (11) the transfer of the transmit data from the cbnt x register to the shift register is ended and the intcbnt signal is generated. to end cont inuous transmission/reception at the current transmission/reception, do not wr ite to the cbntx register. (12) when the next transmit data is not written to t he cbntx register before tr ansfer end, stop the serial clock output to the sckbn pin after trans fer end, and clear the cbntsf bit to 0. (13) when the reception error interrupt request signal (intcbnre) is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 840 16.5.10 continuous transfer mode (slave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (4) (5), (8) (11) no (7) transmission ended? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (10) yes cbntsf bit = 0? (cbnstr register) no (6), (9) intcbnt interrupt generated? yes no (9) yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 841 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when a serial clock is input following end of t he transmission of the transfer data length set with the cbnctl2 register, continuous transmission is started. (9) when transfer of the transmit data from the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the intcbnt signal is generated. to end continuous transmission at the current transmission, do no t write to the cbntx register. (10) when the clock of the transfer dat a length set with the cbnctl2 register is input without writing to the cbntx register, clear the cbntsf bit to 0 to end transmission. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transmission mode, the reception end interrupt request signal (intcbnr) is not generated. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 842 16.5.11 continuous transfer m ode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 843 (1) operation flow start yes intcbnr interrupt generated? intcbnre interrupt generated? end no no yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a3h start reception (1), (2), (3) (4) (5) (4) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h intcbnr interrupt generated? (9) (10) (11) (8) no yes cbntsf bit = 0? (cbnstr) no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 844 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sibn pin intcbnr signal cbnsce bit sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive dat a of the sibn pin in synchronization with the serial clock. (6) when reception is ended, the reception end inte rrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (7) when a serial clock is input in the cbnctl0.cbns ce bit = 1 status, continuous reception is started. (8) to end continuous reception at the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is ended, the intcbnr signal is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before co mmunication end, clear the cbntsf bit to 0 to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 845 16.5.12 continuous transfer mode (s lave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cb ncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 846 (1) operation flow start end yes (13) no is receive data last data? yes (12) no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e3h yes (9) no (1), (2), (3) (4) (5) (7) (7) (8) (13) (14) (15) (15) (10) no yes cbntsf bit = 0? (cbnstr) write cbntx register yes (11) no is data being transmitted last data? start transmission/reception cbnctl0 register 00h intcbnre interrupt generated? intcbnr interrupt generated? (6), (11) no yes intcbnt interrupt generated? (4) no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 847 (2) operation timing (1/2) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sobn pin in synchronization with the serial clock, and capture the receiv e data of the sibn pin. (6) when transfer of the transmit data from the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when reception of the transfer dat a length set with the cbnctl2 regist er is completed, the reception end interrupt request signal (intcbnr) is generated , and reading of the cbnrx register is enabled. (9) when a serial clock is input continuously, continuous transmission/re ception is started. (10) read the cbnrx register. (11) when transfer of the transmit data from the cbntx register to the shi ft register is ended and writing to the cbntx register is enabled, the intcbnt signal is generated. to end continuous transmission/reception at the current transmission/ reception, do not write to the cbntx register. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 848 (2/2) (12) when the clock of the transfer data length set with the cbnc tl2 register is input without writing to the cbntx register, the intcbnr signal is gener ated. clear the cbntsf bit to 0 to end transmission/reception. (13) when the reception error interrupt request signal (intcbnre) is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 849 16.5.13 reception error when transfer is performed with reception enabled (cbnct l0.cbnrxe bit = 1) in the continuous transfer mode, the reception error interrupt request signal (intcbnre) is generated when the next receive operation is ended before the cbnrx register is read after the reception end interru pt request signal (intcbnr) is generated, and the overrun error flag (cbnstr.cbnove) is set to 1. even if an overrun error has occurred, t he previous receive data is lost since the cbnrx register is updated. even if a reception error has occurred, the intcbnre signal is generated again upon the next reception end if the cbnrx register is not read. to avoid an overrun error, end reading the cbnrx regist er until one half clock before sampling the last bit of the next receive data from the intcbnr signal generation. (1) operation timing sckbn pin cbnrx register read signal (1) (2) (4) 01h 02h 05h 0ah 15h 2ah 55h aah 00h 01h 02h 05h 0ah 15h 2ah 55h shift register aah 55h cbnrx register sibn pin intcbnr signal intcbnre signal cbnove bit sibn pin capture timing (3) (1) start continuous transfer. (2) end of the first transfer (3) the cbnrx register cannot be read until on e half-clock before the end of the second transfer. (4) when an overrun error occurs and the reception erro r interrupt request signal (intcbnre) is generated, the overrun error flag (cbnstr.cbnove) is set (1). the receive data is overwritten. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 850 16.5.14 clock timing (1/2) (i) communication type 1 ( cbnckp and cbndap bits = 00) d6 d5 d4 d3 d2 d1 sckbn pin sibn pin capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit d0 d7 (ii) communication type 3 (cbnckp and cbndap bits = 10) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn pin capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data writt en to the cbntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon end of communication. 2. the intcbnr interrupt occurs if reception is correctly ended and receive data is ready in the cbnrx register while reception is enabled. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, th e written data is not transfer red because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 851 (2/2) (iii) communication type 2 (cbnckp and cbndap bits = 01) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn pin capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit (iv) communication type 4 (cbnckp and cbndap bits = 11) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn pin capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data writt en to the cbntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon end of communication. 2. the intcbnr interrupt occurs if reception is correctly ended and receive data is ready in the cbnrx register while reception is enabled. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, th e written data is not transfer red because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications. remark n = 0 to 2
chapter 16 clocked serial interface b (csib) user?s manual u18279ej3v0ud 852 16.6 output pins (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. remark n = 0 to 2 cbnckp cbncks2 cbncks1 cbncks0 sckbn pin output 1 1 1 high impedance 0 other than above fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbnctl1.cbncks2 to cbnctl1.cbncks0 bits is rewritten. (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. remark n = 0 to 2 cbntxe cbndap cbndir sobn pin output 0 fixed to low level 0 sobn latch value (low level) 0 cbntx value (msb) 1 1 1 cbntx value (lsb) remarks 1. the sobn pin output changes when any one of the cbnctl0.cbnt xe, cbnctl0.cbndir, or cbnctl1.cbndap bits is rewritten. 2. : don?t care
user?s manual u18279ej3v0ud 853 chapter 17 i 2 c bus to use the i 2 c bus function, use the p30/sc l and p31/sda pins as the serial transmit/receive data and set them to n-ch open-drain output. in the v850e/if3 and v850e/ig3, one channel of i 2 c bus is provided. 17.1 mode switching between i 2 c and uarta1 in the v850e/if3 and v850e/ig3, i 2 c and uarta1 function alternately, and t hese pins cannot be used at the same time. to switch between i 2 c and uarta1, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of i 2 c or uarta1 are not guaranteed if the mode is switched during transmissi on or reception. be sure to di sable the unit that is not used. figure 17-1. mode switch settings of i 2 c and uarta1 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h pfce37 pfce36 pfce35 pfce34 0 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port txda1 output sda i/o setting prohibited setting prohibited pmc31 0 1 1 1 1 pfce31 0 0 1 1 pfc31 0 1 0 1 specification of alternate function of p31 pin pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 i/o port rxda1 input scl i/o setting prohibited setting prohibited pmc30 0 1 1 1 1 pfce30 0 0 1 1 pfc30 0 1 0 1 specification of alternate function of p30 pin remark = don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 854 17.2 features the i 2 c has the following two modes. ? operation stop mode ? i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi master supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl) line and a serial data bus (sda) line. this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ? data?, and ?stop condition? data to the sl ave device, via the serial data bus. the slave device automatically detects these received st ate and data by hardware. this function can simplify the part of application progr am that controls the i 2 c bus. since the scl and sda pins are us ed for n-ch open drain outputs, i 2 c requires pull-up resistors for the serial clock line and the serial data bus line.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 855 figure 17-2. block diagram of i 2 c internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator bus status detector match signal iic shift register 0 (iic0) so latch iice0 dq set clear cl00 trc0 dfc0 dfc0 sda scl n-ch open-drain output n-ch open-drain output data retention time correction circuit start condition generator stop condition generator ack generator wakeup controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic iic shift register 0 (iic0) iicc0.stt0, iicc0.spt0 iics0.msts0, iics0.exc0, iics0.coi0 iics0.msts0, iics0.exc0, iics0.coi0 f xx lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector internal bus cld0 dad0 smc0 dfc0 cl00 iicocksen iicocks1 iicocks0 clx0 iic clock select register 0 (iiccl0) stcf0 iicbsy0 stcen0 iicrsv0 iic flag register 0 (iicf0) iic function expansion register 0 (iicx0) iicops clock select register (iicocks) f xx /4, f xx /6, f xx 8, f xx /10 prescaler
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 856 a serial bus configuration example is shown below. figure 17-3. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 857 17.3 configuration i 2 c includes the following hardware. table 17-1. configuration of i 2 c item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock select register 0 (iiccl0) iic function expansion register 0 (iicx0) iicops clock select register (iicocks) (1) iic shift register 0 (iic0) the iic0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iic0 register can be used for both transmission and reception. write and read operations to the iic0 r egister are used to control the act ual transmit and receive operations. the iic0 register can be read or written in 8-bit units. reset sets iic0 to 00h. (2) slave address register 0 (sva0) the sva0 register sets local addresses when in slave mode. the sva0 register can be read or written in 8-bit units. reset sets sva0 to 00h. (3) so latch the so latch is used to retain the sda pin?s output level. (4) wakeup controller this circuit generates an interrupt request signal (intiic ) when the address received by this register matches the address value set to the sva0 register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic). an i 2 c interrupt is generated followi ng either of two triggers. ? falling of the eighth or ninth clock of t he serial clock (set by iicc0.wtim0 bit) ? interrupt request generated when a stop condition is detected (set by iicc0.spie0 bit)
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 858 (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iicc0.stt0 bit is set. however, in the communication reservation disabled st atus (iicf0.iicrsv0 bit = 1), when the bus is not released (iicf0.iicbsy0 bit = 1), start condition requests are ignored and the iicf0.stcf0 bit is set to 1. (13) stop condition generator a stop condition is generated when t he iic0.spt0 bit is set (1). (14) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicf0.stcen0 bit.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 859 17.4 registers i 2 c is controlled by the following registers. ? iic control register 0 (iicc0) ? iic status register 0 (iics0) ? iic flag register 0 (iicf0) ? iic clock select register 0 (iiccl0) ? iic function expansion register 0 (iicx0) ? iicops clock select register (iicocks) the following registers are also used. ? iic shift register 0 (iic0) ? slave address register 0 (sva0) remark for the alternate-function pin settings, see table 4-14 settings when port pins are used for alternate functions .
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 860 (1) iic control register 0 (iicc0) the iicc0 register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. the iicc0 register can be r ead or written in 8-bit or 1-bit units. however, set the spie0, wtim0, and acke0 bits when the iice0 bit is 0 or during the wait period. when setting the iice0 bit from ?0? to ?1?, these bits can also be set at the same time. reset sets this register to 00h. (1/4) after reset: 00h r/w address: fffffd82h <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable/dis able specification 0 stop operation. reset the iics0 register note 1 . stop internal operation. 1 enable operation. be sure to set this bit to 1 when the scl and sda lines are high level. condition for clearing (iice0 bit = 0) condition for setting (iice0 bit = 1) ? cleared by instruction ? reset ? set by instruction lrel0 note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl and sda lines are set to high impedance. the stt0, spt0, iics0.msts0, iics0.exc0, iics0.coi 0, iics0.trc0, iics0.ackd0, and iics0.std0 bits are cleared to 0. the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lrel0 bit = 0) condition for setting (lrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, and the iicf0.stcf0, iicf0 .iicbsy0, iiccl0.cld0, and iiccl0.dad0 bits are reset. 2. this flag?s signal is invalid when the iice0 bit = 0. caution if the i 2 c operation is enabled (iice0 bit = 1) when the scl line is high level and the sda line is low level, the start condition is detected i mmediately. to avoid th is, after enabling the i 2 c operation, immediately set the lrel0 bit to 1 with a bit manipulation instruction.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 861 (2/4) wrel0 note wait cancellation control 0 do not cancel wait 1 cancel wait. this setting is automatica lly cleared to 0 after wait is canceled. condition for clearing (wrel0 bit = 0) condition for setting (wrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction spie0 note enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 bit = 0) condition for setting (spie0 bit = 1) ? cleared by instruction ? reset ? set by instruction wtim0 note control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is co mpleted. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after ack is issued. however, when t he slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 bit = 0) condition for setting (wtim0 bit = 1) ? cleared by instruction ? reset ? set by instruction acke0 note acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda line is set to low level. the acke0 bit setting is invalid for address reception. in this case, ack is generated when the addresses match. however, the acke0 bit setting is valid for address reception of the extension code. condition for clearing (acke0 bit = 0) condition for setting (acke0 bit = 1) ? cleared by instruction ? reset ? set by instruction note this flag?s signal is invalid when the iice0 bit = 0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 862 (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sda line is changed from high level to low level while the scl line is high level and then the start condi tion is generated. next, after the rated amount of time has elapsed, the scl line is changed to low level (wait status). when a third party is communicating ? when communication reservation functi on is enabled (iicf0.iicrsv0 bit = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation functi on is disabled (iicrsv0 bit = 1) the iicf0.stcf0 bit is set to 1 and the informati on set (1) to the stt0 bit is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and slave has been notified of final reception. for master transmission: a start condition may not be generat ed normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the spt0 bit. ? when the stt0 bit is set to 1, setting the stt0 bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (stt0 bit = 0) condition for setting (stt0 bit = 1) ? when the stt0 bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared when start conditi on is generated by master device ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit = 0 (operation stop) ? reset ? set by instruction remark the stt0 bit is 0 if it is read after data setting.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 863 (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda line goes to low level, either set the scl line to high level or wait until the scl pin goes to high level. next, after the rated amount of time has elapsed, t he sda line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition may not be generated normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the stt0 bit. ? the spt0 bit can be set to 1 only when in master mode note . ? when the wtim0 bit has been cleared to 0, if the spt0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generat ed during the high-level period of the ninth clock. the wtim0 bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the spt0 bit should be set to 1 during the wait peri od that follows output of the ninth clock. ? when the spt0 bit is set to 1, setting the spt0 bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (spt0 bit = 0) condition for setting (spt0 bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit = 0 (operation stop) ? reset ? set by instruction note set the spt0 bit to 1 only in master mode. however, the spt0 bit must be set to 1 and a stop condition generated before the first stop condition is detected follo wing the switch to operation enable status. for details, see 17.15 cautions . caution when the iics0.trc0 bit is set to 1, th e wrel0 bit is set to 1 during the ninth clock and wait is canceled, after which the trc0 bi t is cleared to 0 and the sda line is set to high impedance. remark the spt0 bit is 0 if it is read after data setting.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 864 (2) iic status register 0 (iics0) the iics0 register indica tes the status of the i 2 c bus. the iics0 register is read-only, in 8-bit or 1-bit units. however, the iics0 register can only be read when t he iicc0.stt0 bit is 1 or during the wait period. reset sets this register to 00h. (1/3) after reset: 00h r address: fffffd86h <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 bit = 0) condition for setting (msts0 bit = 1) ? when a stop condition is detected ? when the ald0 bit = 1 (arbitration loss) ? cleared by the iicc0.lrel0 bit = 1 (exit from communications) ? when the iicc0.iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the msts0 bit is cleared to 0. condition for clearing (ald0 bit = 0) condition for setting (ald0 bit = 1) ? automatically cleared after the iics0 register is read note ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. note this bit is also cleared when a bit manipulation in struction is executed for another bit in the iics0 register.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 865 (2/3) exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 bit = 0) condition for setting (exc0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (s et at the rising edge of the eighth clock). coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 bit = 0) condition for setting (coi0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 ? reset ? when the received address matches the local address (sva0 register) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status ). the sda line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sd a line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trc0 bit = 0) condition for setting (trc0 bit = 1) ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? cleared by the iicc0.wrel0 bit = 1 note (wait release) ? when the ald0 bit changes from 0 to 1 (arbitration loss) ? reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input in the first byte?s lsb (transfer direction specification bit) note the iics0.trc0 bit is cleared to 0 and the sda line become high impedance when the iicc0.wrel0 bit is set to 1 and wait state is released at the ninth clock wit h the trc0 bit = 1.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 866 (3/3) ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 bit = 0) condition for setting (ackd0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? after the sda pin is set to low level at the rising edge of the scl pin?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std0 bit = 0) condition for setting (std0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd0 bit = 0) condition for setting (spd0 bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 867 (3) iic flag register 0 (iicf0) iicf0 is a register that set the operation mode of i 2 c and indicate the status of the i 2 c bus. these registers can be read or writt en in 8-bit or 1-bit units. howeve r, the stcf0 and iicbsy0 bits are read- only. the iicrsv0 bit can be used to enable/disable the communication reservation function (see 17.14 communication reservation ). the stcen0 bit can be used to set the initial value of the iicbsy0 bit (see 17.15 cautions ). the iicrsv0 and stcen0 bits can be written only when the operation of i 2 c is disabled (iicc0.iice0 bit = 0). when operation is enabled, the iic f0 register can be read. reset sets this register to 00h.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 868 <7> stcf0 condition for clearing (stcf0 bit = 0) ? clearing by setting the stt0 bit = 1 ? when the iice0 bit = 1 0 (operation stop) ? reset condition for setting (stcf0 bit = 1) ? generating start condition unsuccessful and the stt0 bit cleared to 0 when communication reservation is disabled (iicrsv0 bit = 1). stcf0 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag iicc0.stt0 clear flag iicf0 <6> iicbsy0 5 0 4 0 3 0 2 0 <1> stcen0 <0> iicrsv0 after reset: 00h r/w note address: fffffd8ah condition for clearing (iicbsy0 bit = 0) ? detection of stop condition ? when the iice0 bit = 1 0 (operation stop) ? reset condition for setting (iicbsy0 bit = 1) ? detection of start condition ? setting of the iice0 bit when the stcen0 bit = 0 iicbsy0 0 1 bus release status (initial communication status when stcen0 bit = 1) bus communication status (initial communication status when stcen0 bit = 0) i 2 c bus status flag condition for clearing (stcen0 bit = 0) ? detection of start condition ? reset condition for setting (stcen0 bit = 1) ? setting by instruction stcen0 0 1 after operation is enabled (iice0 bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv0 bit = 0) ? clearing by instruction ? reset condition for setting (iicrsv0 bit = 1) ? setting by instruction iicrsv0 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcen0 bit only wh en the operation is stopped (iice0 bit = 0). 2. as the bus release status (iicbsy0 bit = 0) is recognized regardless of the actual bus status when the stcen0 bit = 1, when ge nerating the first start condition (stt0 bit = 1), it is necessary to verify that no third pa rty communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsv0 bit only when the operation is stopped (iice0 bit = 0).
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 869 (4) iic clock select register 0 (iiccl0) the iiccl0 register is used to set the transfer clock for the i 2 c bus. the iiccl0 register can be r ead or written in 8-bit or 1-bit units. however, the cld0 and dad0 bits are read- only. the smc0 and cl00 bits are set in comb ination with the iicx0.clx0, iicocks.iicocks1, and iicocks.iicocks0 bits (see 17.4 (7) i 2 c transfer clock setting method ). set the iiccl0 register when the iicc0.iice0 bit = 0. reset sets this register to 00h. after reset: 00h r/w note address: fffffd84h 7 6 <5> <4> 3 2 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 0 cl00 cld0 detection of scl pin level (valid only when iicc0.iice0 bit = 1) 0 the scl pin was detected at low level. 1 the scl pin was detected at high level. condition for clearing (cld0 bit = 0) condition for setting (cld0 bit = 1) ? when the scl pin is at low level ? when the iice0 bit = 1 0 (operation stop) ? reset ? when the scl pin is at high level dad0 detection of sda pin level (valid only when iice0 bit = 1) 0 the sda pin was detected at low level. 1 the sda pin was detected at high level. condition for clearing (dad0 bit = 0) condition for setting (dad0 bit = 1) ? when the sda pin is at low level ? when the iice0 bit = 1 0 (operation stop) ? reset ? when the sda pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc0 bit set/clear. the digital filter is used for noi se elimination in high-speed mode. communication clock selection cl00 normal mode high-speed mode 0 f xx /44 f xx /24 1 f xx /86 f xx /24 note bits 4 and 5 are read-only bits. remark f xx : selection clock
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 870 (5) iic function expansion register 0 (iicx0) this register sets the function expansion of i 2 c (valid only in high-speed mode). this register can be read or written in 8-bit or 1-bit units. the clx0 bit is set in combination with the iiccl0.smc0, iiccl0.cl00, iicocks.iic ocks1, and iicocks.iicocks0 bits (see 17.4 (7) i 2 c transfer clock setting method ). set the iicx0 register when the iicc0.iice0 bit = 0. reset sets this register to 00h. iicx0 after reset: 00h r/w address: fffffd85h 0 0 0 0 0 0 0 clx0 7 6 5 4 3 2 1 <0> communicate at transfer rate set by the iiccl0.cl00 bit. communicate at double transfer rate set by the iiccl0.cl00 bit in high-speed mode . clx0 0 1 clock select expansion bit (6) iicops clock select register (iicocks) this register controls the division clock of i 2 c. this register can be read or writt en in 8-bit or 1-bit units. the iicocks1 and iicocks0 bits are set in combination with the iiccl0.smc0, ii ccl0.cl00, and iicx0.clx0 bits (see 17.4 (7) i 2 c transfer clock setting method ). reset sets this register to 00h. 0 iicocks 0 0 iicocksen 0 0 iicocks1 iicocks0 after reset: 00h r/w address: fffffd90h i 2 c division clock operation stop i 2 c division clock operation enable iicocksen 0 1 specification of i 2 c division clock operation iicocks0 0 1 0 1 i 2 c division clock selection f xx /4 f xx /6 f xx /8 f xx /10 iicocks1 0 0 1 1
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 871 (7) i 2 c transfer clock setting method the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 96, 120, 144, 192, 240, 344, 352, 440, 516, 688, 860 (see table 17-2 selection clock setting .) t: 1/f xx t r : scl rise time t f : scl fall time for example, the i 2 c transfer clock frequency (f scl ) when f xx = 64 mhz, m = 192, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(192 15.6 ns + 200 ns + 50 ns) ? 308 khz m t + t r + t f m/2 t t f t r m/2 t scl scl inversion scl inversion scl inversion the selection clock is set using a combinati on of the iiccl0.smc0, ii ccl0.cl00, iicx0.clx0, iicocks.iicocks1, and iic ocks.iicocks0 bits. table 17-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 0 clx0 smc0 cl00 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode f xx /8 (when iicocks = 12h) f xx /352 32.00 mhz to 33.52 mhz 0 0 0 f xx /10 (when iicocks = 13h) f xx /440 32.00 mhz to 41.90 mhz f xx /4 (when iicocks = 10h) f xx /344 32.00 mhz to 33.52 mhz f xx /6 (when iicocks = 11h) f xx /516 32.00 mhz to 50.28 mhz f xx /8 when (iicocks = 12h) f xx /688 33.52 mhz to 64.00 mhz 0 0 1 f xx /10 (when iicocks = 13h) f xx /860 41.90 mhz to 64.00 mhz normal mode (smc0 bit = 0) f xx /4 (when iicocks = 10h) f xx /96 32.00 mhz to 33.52 mhz f xx /6 (when iicocks = 11h) f xx /144 32.00 mhz to 50.28 mhz f xx /8 (when iicocks = 12h) f xx /192 32.00 mhz to 64.00 mhz 0 1 x f xx /10 (when iicocks = 13h) f xx /240 40.00 mhz to 64.00 mhz high-speed mode (smc0 bit = 1) 1 0 x setting prohibited f xx /8 (when iicocks = 12h) f xx /96 32.00 mhz to 33.52 mhz 1 1 x f xx /10 (when iicocks = 13h) f xx /120 40.00 mhz to 41.90 mhz high-speed mode (smc0 bit = 1) remark x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 872 (8) iic shift register 0 (iic0) the iic0 shift register is used for serial transmission/re ception (shift operations) that is synchronized with the serial clock. the iic0 shift register can be read or written in 8-bit units, but data s hould not be written to the iic0 shift register during a data transfer. access (read/write) the iic0 shift regist er only during the wait period. acce ssing this register in communication states other than the wa it period is prohibited. howe ver, for the master device, the iic0 shift register can be written once only after the transmission trigger bit (iicc0.stt0 bit) has been set to 1. when the iic0 shift register is written during wait, the wait is cancelled and data transfer is started. reset sets this register to 00h. after reset: 00h r/w address: fffffd80h 7 6 5 4 3 2 1 0 iic0 (9) slave address register 0 (sva0) the sva0 register holds the i 2 c bus?s slave addresses. however, rewriting this register is prohibited when the iics0.std0 bit = 1 (start condition detection). the sva0 register can be read or written in 8-bit units, but bit 0 is fixed to 0. reset sets this register to 00h. after reset: 00h r/w address: fffffd83h 7 6 5 4 3 2 1 0 sva0 0
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 873 17.5 functions 17.5.1 pin configuration the serial clock pin (scl) and serial data bus pin (sda) are configured as follows. scl ................ this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda ................ this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 17-4. pin configuration diagram v dd scl sda scl sda v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 874 17.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication form at and the status generated by the i 2 c bus. the transfer timing for the ?start condition?, ?addre ss?, ?transfer direction spec ification?, ?data?, and ?stop condition? generated via the i 2 c bus?s serial data bus is shown below. figure 17-5. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device generates the start c ondition, slave address, and stop condition. ack can be generated by either t he master or slave device (normally, it is generated by the device t hat receives 8-bit data). the serial clock (scl) is continuously output by the master device. however, in the slave device, the scl?s low- level period can be extended and a wait can be inserted. 17.6.1 start condition a start condition is met when the scl pin is at high level and the sda pin changes from high level to low level. the start conditions for the scl pin and sda pin are generated when t he master device starts a serial transfer to the slave device. start conditions can be detected when the device is used as a slave. figure 17-6. start conditions h scl sda a start condition is generated when the iicc0.stt0 bit is set to 1 after a stop condition has been detected (iics0.spd0 bit = 1). when a start condition is detected, iics0.std0 bit is set to 1.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 875 17.6.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the sva0 register. if the address dat a matches the sva0 values, the slave device is selected and communicates with the master device until t he master device generates a start condition or stop condition. figure 17-7. address address scl 1 sda intiic note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiic ) is generated if a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in 17.6.3 transfer direction specification below, are together written to the iic0 regi ster and are then output. received addresses are written to the iic0 register. the slave address is assigned to the hi gher 7 bits of the iic0 register.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 876 17.6.3 transfer dir ection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 17-8. transfer direction specification scl 1 sda intiic 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iic) is generated if a local address or extension code is received during slave device operation.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 877 17.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is j udged as normal and processing continues. t he detection of ack is confirmed with the iics0.ackd0 bit. when the master device is the receivi ng device, after receiving the final dat a, it does not return ack and generates the stop condition. when the slave dev ice is the receiving device and does not return ack, the master device generates either a stop condition or a rest art condition, and then stops the current transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist for the specified address. when the receiving device sets the sda line to low le vel during the ninth clock, ack is generated (normal reception). when the iicc0.acke0 bit is set to 1, automatic ac k generation is enabled. trans mission of the eighth bit following the 7 address data bits causes the iics0.trc0 bit to be set. normally, set the acke0 bit to 1 for reception (trc0 bit = 0). when the slave device is receiving (when trc0 bit = 0), if the slave device cannot rece ive data or does not need to receive any more data, clear the acke0 bit to 0 to indi cate to the master that no more data can be received. similarly, when the master device is receiving (when trc0 bit = 0) and the subsequent data is not needed, clear the acke0 bit to 0 to prevent ack from being generated. th is notifies the slave device (transmitting device) of the end of the data transmissi on (transmission stopped). figure 17-9. ack scl 1 sda 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, ack is automatically generated regardless of the value of the acke0 bit. no ack is generated if the received addre ss is not a local address (nack). when receiving the extension code, set the acke0 bit to 1 in advance to generate ack. the ack generation method during data rec eption is based on the wait timing setti ng, as described by the following. ? when 8-clock wait is selected (iicc0.wtim0 bit = 0): ack is generated at the falling edge of t he scl pin?s eighth clock if the acke0 bit is set to 1 before the wait state cancellation. ? when 9-clock wait is selected (iicc0.wtim0 bit = 1): ack is generated if the acke0 bit is set to 1 in advance.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 878 17.6.5 stop condition when the scl pin is at high level, changing the sda pin from low level to high level generates a stop condition. a stop condition is generated when serial transfer from the master device to the slave device has been completed. stop conditions can be detected when the device is used as a slave. figure 17-10. stop condition h scl sda a stop condition is generated when the ii cc0.spt0 bit is set to 1. when the stop condition is detected, the iics0.spd0 bit is set to 1 and the interrupt request signal (i ntiic) is generated when the iicc0 .spie0 bit is set to 1.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 879 17.6.6 wait state the wait state is used to not ify the communication partner t hat a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave dev ices, the next data transfer can begin. figure 17-11. wait state (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: recep tion, and iicc0.acke0 bit = 1) scl 6 sda 78 9 123 scl iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 register or iicc0.wrel0 bit is set to 1. transfer lines wait state from slave wait state from master
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 880 figure 17-11. wait state (2/2) (b) when master and slave d evices both have a nine-clock wait (master: transmission, slave: reception, and acke0 = 1) scl 6 sda 789 123 scl iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke0 master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 register or wrel0 bit is set to 1. generated according to previously set acke0 bit value transfer lines wait state from master and slave wait state from slave a wait state is automatically generated after a start condition is generated. moreover, a wait stat e is automatically generated depending on the setting of the iicc0.wtim0 bit. normally, when the iicc0.wrel0 bit is set to 1 or when ffh is written to the iic0 regi ster, the wait status is canceled and the transmitting side writes data to t he iic0 register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. ? by setting the iicc0.stt0 bit to 1 ? by setting the iicc0.spt0 bit to 1
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 881 17.6.7 wait state cancellation method in the case of i 2 c, wait state can be canceled normally in the following ways. ? by writing data to the iic0 register ? by setting the iicc0.wrel0 bit to 1 (wait state cancellation) ? by setting the iicc0.stt0 bit to 1 (start condition generation) note ? by setting the iicc0.spt0 bit to 1 (stop condition generation) note note master only if any of these wait state canc ellation actions is performed, i 2 c will cancel wait state and restart communication. when canceling wait state and s ending data (including address), writ e data to the iic0 register. to receive data after canceling wait state, or to end data transmission, set the wrel0 bit to 1. to generate a restart condition after canceli ng wait state, set the stt0 bit to 1. to generate a stop condition after canceling wait state, set the spt0 bit to 1. execute cancellation only once for each wait state. for example, if data is written to t he iic0 register following wait state canc ellation by setting the wrel0 bit to 1, conflict between the sda line change timing and iic0 register write timing may result in the data output to the sda line may be incorrect. even in other operations, if communication is stopped halfway, clearing the iicc0.iice0 bit to 0 will stop communication, enabling wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iicc0.lre l0 bit to 1 causes the communication operation to be exited, enabling wait st ate to be cancelled.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 882 17.7 i 2 c interrupt request signals (intiic) the following shows the value of the iic s0 register at the intiic interr upt request signal generation timing and at the intiic signal timing. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 883 17.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iicc0.wtim0 bit = 0 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b s 3: iics0 register = 1000x000b (wtim0 bit = 1 note ) s 4: iics0 register = 1000xx00b 5: iics0 register = 00000001b note to generate a stop condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic). remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 1000xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 884 (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1 note 1 ) s 3: iics0 register = 1000xx00b (wtim0 bit = 0 note 2 ) s 4: iics0 register = 1000x110b s 5: iics0 register = 1000x000b (wtim0 bit = 1 note 3 ) s 6: iics0 register = 1000xx00b 7: iics0 register = 00000001b notes 1. to generate a start condition, set the wt im0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic). 2. clear the wtim0 bit to 0 to make the settings original. 3. to generate a stop condition, set the wt im0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic). remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000xx00b s 3: iics0 register = 1000x110b s 4: iics0 register = 1000xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 885 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim0 bit = 0 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1010x110b s 2: iics0 register = 1010x000b s 3: iics0 register = 1010x000b (wtim0 bit = 1 note ) s 4: iics0 register = 1010xx00b 5: iics0 register = 00000001b note to generate a stop condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic). remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1010x110b s 2: iics0 register = 1010x100b s 3: iics0 register = 1010xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 886 17.7.2 slave device operation (when recei ving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x100b s 3: iics0 register = 0001xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 887 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 888 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restar t, address mismatch (extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restar t, address mismatch (extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x110b s 5: iics0 register = 0010xx00b 6: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 889 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 890 17.7.3 slave device operation (w hen receiving extension code) always under communication when re ceiving the extension code. (1) start ~ code ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010x100b s 4: iics0 register = 0010xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 891 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 0001x110b s 5: iics0 register = 0001xx00b 6: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 892 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 0010x010b s 5: iics0 register = 0010x110b s 6: iics0 register = 0010xx00b 7: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 893 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 00000110b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 894 17.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 1: iics0 register = 00000001b remark : generated only when iicc0.spie0 bit = 1
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 895 17.7.5 arbitration loss operation (opera tion as slave after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iics0.msts0 bit for checking arbitration result by eac h intiic interrupt occurrence. (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0101x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0101x110b s 2: iics0 register = 0001x100b s 3: iics0 register = 0001xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 896 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0110x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x000b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0110x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010x100b s 4: iics0 register = 0010xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 897 17.7.6 operation when arbitrat ion loss occurs (no communicat ion after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iics0.msts0 bit for checking arbitration result by eac h intiic interrupt occurrence. (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iics0 register = 01000110b 2: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iics0 register = 0110x010b iicc0.lrel0 bit is set to 1 by software 2: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 898 (3) when arbitration loss o ccurs during data transfer <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 10001110b s 2: iics0 register = 01000000b 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 10001110b s 2: iics0 register = 01000100b 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 899 (4) when arbitration loss occurs due to restart condition duri ng data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 01000110b 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 0110x010b iicc0.lrel0 bit is set to 1 by software 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 900 (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 2 s 1: iics0 register = 1000x110b 2: iics0 register = 01000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 901 (6) when arbitration loss occurs due to low level of sdan pin when attempting to generate a restart condition <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000x100b (wtim0 bit = 0) s 4: iics0 register = 01000000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 iicc0.stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 01000100b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 902 (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition <1> when wtim0 bit = 0 stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000xx00b 4: iics0 register = 01000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000xx00b 3: iics0 register = 01000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 903 (8) when arbitration loss occurs due to low level of sdan pin wh en attempting to generate a stop condition <1> when wtim0 bit = 0 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000x100b (wtim0 bit = 0) s 4: iics0 register = 01000100b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 01000100b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 904 17.8 interrupt request signal (intiic) generation timing and wait control the setting of the iicc0.wtim0 bit determines the timing by which t he intiic signal is generated and the corresponding wait control, as shown below. table 17-3. intiic signal gene ration timing and wait control during slave device operation du ring master device operation wtim0 bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addre ss set to the sva0 register. at this point, ack is generated regardless of the va lue set to the iicc0.acke0 bit. for a slave device that has received an extension code, the intiic signal occurs at t he falling edge of the eighth clock. when the address does not match after restart, the intiic signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the sva0 regi ster and extensi on codes have not been received, neither the intiic signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined depending on the conditions in notes 1 and 2 above regardless of the wtim0 bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by writing data to the iic0 register ? by setting the iicc0.wrel0 bit (canceling wait state) ? by setting the iicc0.stt0 bit (generating start condition) note ? by setting the iicc0.spt0 bit (generating stop condition) note note master only when an 8-clock wait has been selected (wtim0 bit = 0), whether or not ac k has been generated must be determined prior to wait cancellation. (5) stop condition detection the intiic signal is generated w hen a stop condition is detected.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 905 17.9 address match detection method when in i 2 c bus mode, the master device can select a parti cular slave device by transmitting the corresponding slave address. address match detection is performed autom atically by hardware. an intiic interrupt request signal occurs when a local address has been set to the sva0 register and when t he address set to the sva0 register matches the slave address sent by the master device, or when an extension code has been received. 17.10 error detection in i 2 c bus mode, the status of the serial data bus (sda) during data transmission is captured by the iic0 register of the transmitting device, so the iic0 register data prio r to transmission can be compared with the transmitted iic0 register data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 17.11 extension code (1) when the higher 4 bits of the receive address are ei ther 0000 or 1111, t he extension code flag (exc0) is set for extension code reception and an in terrupt request signal (intiic) is i ssued at the falling edge of the eighth clock. the local address stored in the sva0 register is not affected. (2) if 11110xx0 is set to the sva0 register by a 10- bit address transfer and 11110xx0 is transferred from the master device, the results are as fo llows. note that the intiic signal occurs at the falling edge of the eighth clock. ? higher 4 bits of data match: iics0.exc0 bit = 1 ? 7 bits of data match: iics0.coi0 bit = 1 (3) since the processing after the intiic signal occurs diffe rs according to the data that follows the extension code, such processing is performed by software. the slav e that has received an ext ension code is always under communication, even if the addresses mismatch. for example, when operation as a slave is not desired after the ext ension code is received, set the iicc0.lrel0 bit to 1 and the cpu will enter the next communication wait state. table 17-4. bit definitions for major extension code slave address r/w bit description 0000 000 0 general call address 1111 0xx 0 10-bit slave address spec ification (upon address authentication) 1111 0xx 1 10-bit slave address specificat ion (upon read command issuance after address matches) remark for the extension codes other than above, see the i 2 c bus specifications issued by nxp semiconductors.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 906 17.12 arbitration when several master devices simultaneously generate a star t condition (when the iicc0.stt0 bit is set to 1 before the iics0.std0 bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this ki nd of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iics0.ald0 bit) is set (1) via the timing by which the arbitration loss occurred, and the scl and sda lines are both set for high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (intiic) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the ald0 bit = 1 se tting that has been made by software. for details of interrupt request timing, see 17.7 i 2 c interrupt request signals (intiic) . figure 17-12. arbitration timing example master 1 master 2 transfer lines scl sda scl sda scl sda master 1 loses arbitration hi-z hi-z
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 907 table 17-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is generated (when iicc0.spie0 bit = 1) note 2 when the sda pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie0 bit = 1) note 2 when the sda pin is at low level while attempting to generate a stop condition when the scl pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iicc0.wtim0 bit = 1, an interrupt request o ccurs at the falling edge of the ninth clock. when the wtim0 bit = 0 and the extension code?s slave addr ess is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spie0 bit = 1 for master device operation. 17.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiic) when a local address or extension code has been received. this function makes processing more efficient by prev enting unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may c hange the master device (which has generated a start condition) to a slave device. however, when a stop condition is detect ed, the iicc0.spie0 bit is set regardl ess of the wake up function, and this determines whether interrupt r equests are enabled or disabled.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 908 17.14 communication reservation 17.14.1 when communication reservation functi on is enabled (iicf0.iicrsv0 bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc0.lrel0 bit was set to ?1?). if the iicc0.stt0 bit is set (1) while the bus is not used, a start condition is automatic ally generated and wait status is set after the bus is released (after a stop condition is detected). a communication is automatically start ed as the master by setting the iicc0 .spie0 bit to 1, detecting the bus release due to an interrupt request (intiic) occurrence ( detecting a stop condition), and then writing the address to the iic0 register. before detecting a stop condition, dat a written to the iic0 register is set to invalid. when the stt0 bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been re leased .................................................. a start condition is generated if the bus has not been released (standby mode) ..................comm unication reservation to detect which operation mode has been deter mined for the stt0 bit, set the stt0 bit (1), wait for the wait period, then check the iics0.msts0 bit. wait periods, which should be set via software, are listed in table 17-6. these wait periods can be set via the settings for the iicx0.clx0, iiccl0.smc0, and iiccl0.cl00 bits. table 17-6. wait periods selection clock clx0 smc0 cl00 wait clock wait time when f xx = 64 mhz f xx /8 (iicocks = 12h) 0 0 0 23 clocks 2.88 s f xx /10 (iicocks = 13h) 0 0 0 23 clocks 3.59 s f xx /4 (iicocks = 10h) 0 0 1 43 clocks 2.69 s f xx /6 (iicocks = 11h) 0 0 1 43 clocks 4.03 s f xx /8 (iicocks = 12h) 0 0 1 43 clocks 5.38 s f xx /10 (iicocks = 13h) 0 0 1 43 clocks 6.72 s f xx /4 (iicocks = 10h) 0 1 x 15 clocks 0.94 s f xx /6 (iicocks = 11h) 0 1 x 15 clocks 1.41 s f xx /8 (iicocks = 12h) 0 1 x 15 clocks 1.88 s f xx /10 (iicocks = 13h) 0 1 x 15 clocks 2.34 s f xx /8 (iicocks = 12h) 1 1 x 9 clocks 1.13 s f xx /10 (iicocks = 13h) 1 1 x 9 clocks 1.41 s the communication reservation timing is shown below.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 909 figure 17-13. communication reservation timing 2 1 3456 2 13456 789 scl sda stt0=1 program processing hardware processing write to iic0 set spd0 and intiic communication reservation set std0 generated by master with bus access iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after the iics0.std0 bit is set to 1, a communication reservation can be made by setting the iicc0 .stt0 bit to 1 before a stop condition is detected. figure 17-14. timing for accep ting communication reservations scl sda std0 spd0 standby mode the communication reservation flowchart is illustrated below.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 910 figure 17-15. communication reservation flowchart di stt0 = 1 define communication reservation wait cancel communication reservation no yes iic0 h ei msts0 = 0? (communication reservation) note (generate start condition) ; sets stt0 flag (communication reservation). ; gets wait period set by software (see table 17-6 ). ; confirmation of communication reservation ; clear user flag. ; iic0 write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation oper ation executes a write to the iic0 register when a stop condition interrupt request occurs.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 911 17.14.2 when communication reservation functi on is disabled (iicf0.iicrsv0 bit = 1) when the iicc0.stt0 bit is set when the bus is not us ed in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc0.lrel0 bit was set to 1) to confirm whether the start conditi on was generated or request was rejected, check the iicf0.stcf0 flag. the time shown in table 17-7 is required until the stcf0 flag is set after setting the s tt0 bit = 1. therefore, secure the time by software. table 17-7. wait periods selection clock clx0 smc0 cl00 wait clock wait time when f xx = 64 mhz f xx /8 (iicocks = 12h) 0 0 0 5 clocks 0.63 s f xx /10 (iicocks = 13h) 0 0 0 5 clocks 0.78 s f xx /4 (iicocks = 10h) 0 0 1 5 clocks 0.31 s f xx /6 (iicocks = 11h) 0 0 1 5 clocks 0.47 s f xx /8 (iicocks = 12h) 0 0 1 5 clocks 0.63 s f xx /10 (iicocks = 13h) 0 0 1 5 clocks 0.78 s
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 912 17.15 cautions (1) when iicf0.stcen0 bit = 0 immediately after i 2 c operation is enabled, the bus communication st atus (iicf0.iicbsy0 bit = 1) is recognized regardless of the actual bus status. to execute master communica tion in the status where a stop condition has not been detected, gener ate a stop condition and then release t he bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl0 register. <2> set the iicc0.iice0 bit. <3> set the iicc0.spt0 bit. (2) when iicf0.stcen0 bit = 1 immediately after i 2 c operation is enabled, the bus re leased status (iicbsy0 bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iicc0.stt0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iicc0.iice0 bit of the v850e/if3 and v850e/ig3 is set to 1 while communications with other devices are in progress, the start conditi on may be detected depending on the status of the co mmunication line. be sure to set the iicc0.iice0 bit to 1 when the scl and sda lines are high level. (4) procedure for starting or stopping i 2 c operation (a) starting i 2 c operation <1> select the division clock by using the iic ocks.iicocks1 and iicocks.iicocks0 bits and set the iicocks.iicocksen bit to 1 (to enable i 2 c division clock operation). <2> specify the transfer speed by us ing the iiccl0 and iicx0 registers. <3> set the iicc0.iice0 bit to 1 (to start i 2 c operation). when changing the transfer speed for i 2 c, do so after clearing the iicc0.iice0 bit to 0. (b) stopping i 2 c operation <1> clear the iicc0.iice0 bit to 0 (to stop i 2 c operation). <2> clear the iicocks.iicocksen bit to 0 (to disable i 2 c division clock operation). (5) after the iicc0.stt0 and iicc0.spt0 bits have been set to 1, they must not be re -set without being cleared to 0 first. (6) if transmission has been reserved, set the iicc0.spie0 bi t to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt r equest has been generated, the wait state will be released by writing communication data to i 2 c, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait st ate because an interrupt r equest was not generated. however, it is not necessary to set the spie0 bit to 1 for the software to detect the iics0.msts0 bit.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 913 17.16 communication operations the following shows three operati on procedures with the flowchart. (1) master operation in single master system the flowchart when using the v850e/if3 and v850e/ig3 as the master in a single master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processi ng. execute the initial settings at startup. if communica tion with the slave is required, pr epare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the v850e/if3 and v850e/ig3 take part in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the v850e/if3 and v850e/ig3 lose in arbitration and are spec ified as the slave is omitted here, and only the processing as the master is shown. execute the initial settings at startup to take part in a communication. then, wait for the communicati on request as the master or wait for the specification as the slave. the actual communi cation is performed in the communica tion processing, and it supports the transmission/reception with the slave and the arbitration wit h other masters. (3) slave operation an example of when the v850e/if3 and v850e/ig3 are used as the slave is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at st artup, then wait for the intiic interrupt occurrence (communication waiting). when the intiic interrupt occurs, the communication status is judged and its result is pa ssed as a flag over to the main processing. by checking the flags, necessary communication processing is performed.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 914 17.16.1 master operation in single master system figure 17-16. master operati on in single master system iicx0 0xh iiccl0 xxh iicf0 0xh set stcen0, iicrsv0 = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 set ports initialize i 2 c bus note spt0 = 1 sva0 xxh write iic0 write iic0 spt0 = 1 wrel0 = 1 start end read iic0 acke0 = 0 wtim0 = wrel0 = 1 no no yes no no no yes yes yes yes stcen0 = 1? acke0 = 1 wtim0 = 0 intiic interrupt occurred? transfer ended? transfer ended? restarted? trc0 = 1? ackd0 = 1? ackd0 = 1? see table 4-14 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiic interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic interrupt occurred? yes no intiic interrupt occurred? yes no yes no yes no intiic interrupt occurred? stt0 = 1 note release the i 2 c bus (scl, sda pins = high level) in conformi ty with the specificati ons of the product in communication. for example, when the eeprom tm outputs a low level to the sda pin, set the scl pin to the output port and output clock pul ses from that output port until when the sda pin is constantly high level. remark for the transmission and reception formats, confo rm to the specifications of the product in communication.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 915 17.16.2 master operation in multimaster system figure 17-17. master operation in multimaster system (1/3) iicx0 0xh iiccl0 xxh iicf0 0xh set stcen0, iicrsv0 = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 set ports spt0 = 1 sva0 xxh spie0 = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spd0 = 1? stcen0 = 1? iicrsv0 = 0? a see table 4-14 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic interrupt occurred? intiic interrupt occurred? yes no yes no spd0 = 1? yes no slave operation no intiic interrupt occurred? yes no 1 b spie0 = 0 yes no waiting for communication request waiting for communication initial settings note confirm that the bus rel ease status (iiccl0.cld0 bit = 1, iicc l0.dad0 bit = 1) has been maintained for a certain period (1 frame, for example). when the sd a pin is constantly low le vel, determine whether to release the i 2 c bus (scl, sda pins = high level) by referri ng to the specificati ons of the product in communication.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 916 figure 17-17. master operation in multimaster system (2/3) stt0 = 1 wait slave operation yes msts0 = 1? exc0 = 1 or coi0 =1? communication start preparation (start condition generation) securing wait time by software (see table 17-6 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiic interrupt occurred? yes yes no no a c stt0 = 1 wait slave operation yes iicbsy0 = 0? exc0 = 1 or coi0 =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (see table 17-7 ) waiting for bus release stop condition detection no no intiic interrupt occurred? yes yes no yes stcf0 = 0? no b d c d communication processing communication processing
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 917 figure 17-17. master operation in multimaster system (3/3) write iic0 wtim0 = 1 wrel0 = 1 read iic0 acke0 = 1 wtim0 = 0 wtim0 = wrel0 = 1 acke0 = 0 write iic0 yes trc0 = 1? restarted? msts0 = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiic interrupt occurred? yes no transfer ended? waiting for ack detection yes no intiic interrupt occurred? waiting for data transmission not in communication yes no intiic interrupt occurred? no yes ackd0 = 1? no yes no c 2 yes msts0 = 1? no yes transfer ended? no yes ackd0 = 1? no 2 yes msts0 = 1? no 2 waiting for ack detection yes no intiic interrupt occurred? yes msts0 = 1? no c 2 yes exc0 = 1 or coi0 = 1? no 1 2 spt0 = 1 stt0 = 1 slave operation end communication processing communication processing remarks 1. conform the transmission and reception formats to the specifications of the product in communication. 2. when using the v850e/if3 and v 850e/ig3 as the master in t he multimaster system, read the iics0.msts0 bit for each intiic interrupt o ccurrence to confirm the arbitration result. 3. when using the v850e/if3 and v850e /ig3 as the slave in the mu ltimaster system, confirm the status using the iics0 and iicf0 registers for eac h intiic interrupt occurrence to determine the next processing.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 918 17.16.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-dri ven. therefore, processing by an intiic interrupt (processing requiring a significant change of the operat ion status, such as stop condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiic interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 17-18. software out line during slave operation i 2 c intiic setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiic signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiic interrupt during normal data transfer. this flag is set in the interr upt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iics0.trc0 bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 c and wait for the communication enabled status. w hen communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack. when the master device stops returning ack, transfer is end.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 919 for reception, receive the required number of data and do not return ack for the next data immediately after transfer is end. after that, the master device generates the stop conditi on or restart condition. this causes exit from communications. figure 17-19. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? read iic0 clear ready flag clear ready flag communication direction flag = 1? wrel0 = 1 ackd0 = 1? clear communication mode flag wrel0 = 1 write iic0 iicc0 xxh acke0 = wtim0 = 1 spie0 = 0, iice0 = 1 sva0 xxh local address setting iicx0 0xh iiccl0 xxh set ports transfer clock selection iicf0 0xh set iicrsv0 start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? see table 4-14 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. start initial settings communication processing
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 920 the following shows an example of the pr ocessing of the slave device by an int iic interrupt (it is assumed that no extension codes are used here). during an intiic interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 17-20 slave operation flowchart (2) . figure 17-20. slave operation flowchart (2) yes yes yes no no no intiic occurred set ready flag interrupt servicing completed spd0 = 1? std0 = 1? coi0 = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trc0 set communication mode flag clear ready flag
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 921 17.17 timing of data communication when using i 2 c bus mode, the master device generates an address vi a the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device trans mits the iics0.trc0 bit that specifies the data transfer direction and then starts serial communication with the slave device. the iic0 register?s shift operation is synchronized with the falling edge of the se rial clock (scl pin). the transmit data is transferred to the so latch and is output (msb first) via the sda pin. data input via the sda pin is captured by the iic0 register at the ri sing edge of the scl pin. the data communication timing is shown below.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 922 figure 17-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h l l acke0 msts0 stt0 spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data note 1 iic0 ffh note 2 transmit start condition receive note 2 processing by master device transfer lines processing by slave device notes 1. cancel waits during master transmission by writing data to iic0, not by setting wrel0. 2. to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 923 figure 17-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data note 1 iic0 ffh note 2 iic0 ffh note 2 iic0 data note 1 transmit receive note 2 note 2 ack ack processing by master device transfer lines processing by slave device notes 1. cancel waits during master transmission by writing data to iic0, not by setting wrel0. 2. to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 924 figure 17-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h l acke0 msts0 stt0 spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data note 1 iic0 address iic0 ffh note 2 iic0 ffh note 2 stop condition start condition note 2 note 2 (when spie0 = 1) receive (when spie0 = 1) ack transmit processing by master device (when spie0 = 1) transfer lines processing by slave device notes 1. cancel waits during master transmission by writing data to iic0, not by setting wrel0. 2. to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 925 figure 17-22. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l h l acke0 msts0 stt0 l l spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note 1 note 1 iic0 data note 2 transmit transmit receive receive ack r processing by master device transfer lines processing by slave device notes 1. to cancel master wait, write ffh to iic0 or set wrel0. 2. cancel waits during slave transmission by wr iting data to iic0, not by setting wrel0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 926 figure 17-22. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l l h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 1 89 2345678 9 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note 1 note 1 receive transmit iic0 data note 2 iic0 data note 2 iic0 ffh note 1 iic0 ffh note 1 processing by master device transfer lines processing by slave device notes 1. to cancel master wait, writ e ffh to iic0 or set wrel0. 2. cancel waits during slave transmission by writing data to iic0, not by setting wrel0.
chapter 17 i 2 c bus user?s manual u18279ej3v0ud 927 figure 17-22. example of sl ave to master communication (when 8-clock 9-clock wait for master and 9-clo ck wait for slave are selected) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l acke0 msts0 stt0 spt0 wrel0 intiic trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 scl sda 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic0 address iic0 ffh note 1 note 1 notes 1, 3 iic0 ffh note 2 receive transmit receive stop condition start condition (when spie0 = 1) nack (when spie0 = 1) iic0 ffh note 1 note 3 processing by master device transfer lines processing by slave device notes 1. to cancel master wait, writ e ffh to iic0 or set wrel0. 2. cancel waits during slave transmission by wr iting data to iic0, not by setting wrel0. 3. trc0 is cleared if waits during slave transmission are canceled by setting wrel0 .
user?s manual u18279ej3v0ud 928 chapter 18 bus control function the pd70f3454gc-8ea-a and 70f3454f1-da9-a ar e provided with an external bus interface function via which external memories such as rom and ram, and i/o devices c an be connected to areas other than the internal rom, internal ram, or on-chip peripheral i/o registers via ports 0, 1 (separate bus mo de only), 3, 4, and dl. these ports control address/data i/o, the read/write strobe signal, waits, the clock output, and the address strobe signal. the pd70f3453gc-8ea-a, gf version of the v850e/ig3, and the v850e/if3 ar e not provided with an external bus interface function. this chapter describes the pd70f3454gc-8ea-a and 70f3454f1-da 9-a as target microcontrollers. 18.1 features ? 16-bit/8-bit data bus sizing function ? 2-space chip select function ? wait function ? programmable wait function, through which up to 7 wait states can be inserted for each memory block ? address setup wait and address hold wait insertion f unctions, through which 1 wa it state can be inserted for each memory block ? external wait function via wait pin ? idle state insertion function ? a low-speed device can be connected by in serting an idle state after a read cycle. ? external device connection enabled via bus control/port alternate function pins ? separate bus mode (8-bit addr ess bus, 8-bit/16-bit data bus) ? multiplexed bus mode (16-bit address bus, 8-bit/16-bit data bus) ? support for little endian ? external bus clock frequency (f bus ): 32 mhz/16 mhz selectable function ? misaligned access is possible. ? up to 4 mb of physical memory can be connected (1 mb are shared with the internal rom area).
chapter 18 bus control function user?s manual u18279ej3v0ud 929 18.2 bus control pins the pins used to connect an external device are listed in the table below. table 18-1. bus control pins (w hen separate bus mode selected) bus control pin i/o function alternate-function pin register to switch between port mode/ alternate-function mode ad0 to ad15 i/o data bus pdl0 to pdl15 pmcdl register a0 to a7 output address bus p10 to p17 pmc1 register wait input external wait control p44 pmc4 register clkout output external bus cl ock output p07 pmc0 register cs0, cs1 output chip select p34, p32 pmc3 register wr0, wr1 output write strobe signal p46, p45 pmc4 register rd output read strobe signal p47 pmc4 register astb output address strobe signal p37 pmc3 register table 18-2. bus control pins (whe n multiplexed bus mode selected) bus control pin i/o function alternate-function pin register to switch between port mode/ alternate-function mode ad0 to ad15 i/o address/data bus pdl0 to pdl15 pmcdl register wait input external wait control p44 pmc4 register clkout output external bus cl ock output p07 pmc0 register cs0, cs1 output chip select p34, p32 pmc3 register wr0, wr1 output write strobe signal p46, p45 pmc4 register rd output read strobe signal p47 pmc4 register astb output address strobe signal p37 pmc3 register 18.2.1 pin status during internal rom, in ternal ram, and on-chip peripheral i/o access the status of each pin is as follows when the internal rom, internal ram, and on-chi p peripheral i/o is accessed. table 18-1. pin status list in internal rom, internal ram, and on-c hip peripheral i/o access access destination internal rom in ternal ram on-chip peripheral i/o address bus undefined undefined note 1 data bus hi-z hi-z hi-z external bus control signal inactive note 2 inactive note 2 inactive note 2 notes 1. while the on-chip peripheral i/o is accessed, the address the on-chip peripheral i/o accesses is also output to the external address bus. 2. the wait pin does not input any signal during this operation.
chapter 18 bus control function user?s manual u18279ej3v0ud 930 18.3 memory block function the lower 4 mb of the 64 mb memory space is reserv ed for external memory expansion and is divided into memory blocks of 2 mb and 2 mb. the bus width and pr ogrammable wait function can be independently specified for each block. 3ffffffh 3fff000h 3ffefffh 3ffc000h 00fffffh 0000000h 0000000h 01fffffh 0200000h 03fffffh 0400000h 3ffffffh on-chip peripheral i/o area (4 kb) note 1 internal ram area (12 kb note 2 ) access prohibited (16 kb) cs1 (2 mb) 03fffffh 0100000h external memory area internal rom area (1 mb note 3 ) cs0 (2 mb) 3ffbfffh 3ffc000h notes 1. addresses 3fff000h to 3ffffffh are access-proh ibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 2. pd70f3453: 8 kb pd70f3454: 12 kb 3. pd70f3453: 128 kb pd70f3454: 256 kb 18.3.1 chip select control function of the 64 mb address space (linear), the lower 4 mb (0 000000h to 03fffffh) has two ch ip select functions, cs0 and cs1. the areas selected by cs0 and cs1 are fixed. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the allocation of memory blocks is described below. chip select signal area cs0 0000000h to 01fffffh (2 mb) cs1 0200000h to 03fffffh (2 mb)
chapter 18 bus control function user?s manual u18279ej3v0ud 931 18.4 bus cycle type control function in the pd70f3454gc-8ea-a and 70f3454f1-da9-a, sram, exte rnal rom, and external i/o can be connected directly. (1) bus cycle type configuration register 0 (bct0) this register can be read or written in 16-bit units. reset sets this register to cccch. cautions 1. do not access an external memory area until the initial setting of the bct0 register is complete. however, it is possible to access external memory areas whose initialization settings are complete. 2. the set contents of each register are invalid for the csn space where operations are prohibited. 1 me1 bct0 1 1 0 0 0 0 1 me0 1 1 0 0 0 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: cccch r/w address: fffff480h csn signal csn signal cs0 cs1 men 0 1 operation disabled operation enabled memory controller operation enable for each csn space (n = 0, 1) caution be sure to set bits 0, 1, 4, 5, 8, 9, 12, and 13 to ?0?, and set bits 2, 6, 10, 11, 14, and 15 to ?1?. if they are set other than a bove, the operation is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 932 18.5 bus access 18.5.1 number of access clocks the number of base clocks (min. val ue) necessary for accessing each resource is as follows. bus cycle configuration resource (bus width) instruction fetch (normal access) instruction fetch (branch) operand data access internal rom (32 bits) 1 2 5 internal ram (32 bits) 1 note 1 1 note 1 1 on-chip peripheral i/o (16 bits) ? ? 3 note 2 separate bus mode 3 + n 3 + n 3 + n external memory (16 bits) multiplexed bus mode 3 + n 3 + n 3 + n notes 1. this value is 2 if there is conflict with data access. 2. depending on the set value of the vswc register. remarks 1. unit: clock/access 2. n: number of wait state inserted
chapter 18 bus control function user?s manual u18279ej3v0ud 933 18.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the bsc register. if a 16-bit bus width is specified, the lower 8 bits are used for even addresses and the higher 8 bits are used for odd addresses. (1) bus size configuration register (bsc) this register controls the bus width of each cs space. this register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, a nd then do not change the set value. also, when changing the initial values of th e bsc register, do not access an external memory area until the settings are complete. however, it is po ssible to access external memory areas whose initialization settings are complete. 0 0 bsc 1 1 0 0 1 1 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 5555h r/w address: fffff066h csn signal csn signal cs0 cs1 bsn0 0 1 8 bits 16 bits specification of data bus width of each csn space (n = 0, 1) caution be sure to set bits 1, 3, 5, 7, 9, 11, 13, and 15 to ?0?, and set bits 4, 6, 8, 10, 12, and 14 to ?1?. if they are set other than a bove, the operation is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 934 18.5.3 endian function the pd70f3454gc-8ea-a and 70f3454f1-da9-a support little endian. 18.5.4 bus width the pd70f3454gc-8ea-a and 70f3454f1- da9-a access on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each type of access. all data is accessed in order starting from the lower order side. (1) byte access (8 bits) (a) when the data bus width is 16 bits 8-bit data is transmitted/received via a 16-bit bus. t herefore, if an even address is specified, the lower byte of the external data bus address is accessed. if an odd address is specified, the higher byte of the external data bus address is accessed. <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 byte data 15 8 external data bus 4n address 7 0 7 0 15 8 4n + 1 address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 2 address 7 0 7 0 15 8 4n + 3 address byte data external data bus (b) when the data bus width is 8 bits 8-bit data is transmitted/received via an 8-bit bus. therefore, the specified even/odd address of the external data bus is accessed. <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 4n address byte data external data bus 7 0 7 0 4n + 1 address byte data external data bus 7 0 7 0 4n + 2 address byte data external data bus 7 0 7 0 4n + 3 address byte data external data bus
chapter 18 bus control function user?s manual u18279ej3v0ud 935 (2) halfword access (16 bits) (a) when the data bus width is 16 bits 16-bit data is transmitted/received via a 16-bit bus. t herefore, if an even address is specified, the lower and higher bytes of the external dat a bus address are accessed at the same time. if an odd address is specified, the lower byte of the dat a is transmitted/received to/from an odd address via the higher byte of the external data bus address in the first access. in the second access, the hi gher byte of the data is transmitted/received to/from an even address via the lower 8 bits of the external data bus address. <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n 4n + 1 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 15 8 external data bus 4n + 2 address halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 2 4n + 3 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 3 address 7 0 7 0 15 8 15 8 external data bus 4n + 4 address halfword data halfword data
chapter 18 bus control function user?s manual u18279ej3v0ud 936 (b) when the data bus width is 8 bits 16-bit data is transmitted/received via an 8-bit bus. therefore, the data is tr ansmitted/received in two accesses. the lower/higher byte of the data is transmitted/received to/from the corresponding lower/higher byte of the external data bus address. <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data halfword data 15 8 external data bus 4n address address 7 0 7 0 15 8 external data bus 4n + 1 7 0 7 0 15 8 external data bus 4n + 1 address address 7 0 7 0 15 8 external data bus 4n + 2 halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 2 address address 7 0 7 0 15 8 external data bus 4n + 3 halfword data halfword data 7 0 7 0 15 8 external data bus 4n + 3 address address 7 0 7 0 15 8 external data bus 4n + 4 halfword data halfword data
chapter 18 bus control function user?s manual u18279ej3v0ud 937 (3) word access (32 bits) (a) when the data bus wid th is 16 bits (1/2) 32-bit data is transmitted/received via a 16-bit bus. ther efore, if an even address is specified, the data is transmitted/received in two accesses in 16-bit units. if an odd address is specified, the lower quarter- word data is transmitted/received to/from the higher byte (first access), the middle halfword data is transmitted/received to/from the middle bytes (s econd access), and the upper quarter-word data is transmitted/received to/from the lower byte (third access), of the external data bus address. <1> access to address (4n) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n 4n + 1 7 0 7 0 15 8 15 8 16 23 16 31 24 word data external data bus address 4n + 3 4n + 2 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 1 7 0 7 0 15 8 15 8 16 23 16 31 24 word data external data bus address 4n + 3 4n + 2 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4
chapter 18 bus control function user?s manual u18279ej3v0ud 938 (a) when the data bus width is 16 bits (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 16 23 16 31 24 word data external data bus address 4n + 5 4n + 4 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 7 0 7 0 15 8 15 8 16 23 16 31 24 word data external data bus address 4n + 5 4n + 4 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 6
chapter 18 bus control function user?s manual u18279ej3v0ud 939 (b) when the data bus wid th is 8 bits (1/2) 32-bit data is transmitted/received via an 8-bit bus. t herefore, the data is trans mitted/received in four accesses. the data is transmitted/ received to/from the specified ev en/odd address of the external data bus. <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address 4n address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 1 address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 1 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4
chapter 18 bus control function user?s manual u18279ej3v0ud 940 (b) when the data bus width is 8 bits (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 6
chapter 18 bus control function user?s manual u18279ej3v0ud 941 18.6 wait function 18.6.1 programmable wait function (1) data wait control register 0 (dwc0) to facilitate interfacing with a low-sp eed memory or i/o device and creating an interface circuit, it is possible to insert up to 7 data wait st ates in the starting bus cycle note for each cs space. the number of wait states can be sp ecified by program usi ng dwc0 register. just after system reset, all blocks have 7 data wait states inserted. this register can be read or written in 16-bit units. reset sets this register to 7777h. note sram read/write cycle cautions 1. the internal rom and internal ram areas are not subject to programmable waits and ordinarily no wait access is carried out. the on-chip peripheral i/o area is not subject to programmable wait s, with wait control performed by each on-chip peripheral function only. 2. write to the dwc0 register after reset, and then do not change the set value. also, when changing the initial values of the dwc0 register, do not access an external memory area until the settings are complete. however, it is possible to access external memory areas whose initiali zation settings are complete.
chapter 18 bus control function user?s manual u18279ej3v0ud 942 0 0 dwc0 1 dw12 1 dw11 1 dw10 0 0 1 dw02 1 dw01 1 dw00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 7777h r/w address: fffff484h dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 not inserted 1 2 3 4 5 6 7 specification of number of wait states inserted in each csn space (n = 0, 1) dwn0 0 1 0 1 0 1 0 1 cs0 cs1 csn signal csn signal caution be sure to set bits 3, 7, 11, and 15 to ?0?, and set bits 8 to 10 and 12 to 14 to ?1?. if they are set other than above, th e operation is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 943 (2) address wait cont rol register (awc) this register is used to secure the setup and hold time for the address latch. the awc register can set an address set up wait state or address hold wait st ate that is to be inserted in each bus cycle. the address set up wait state is inserted before t1 st ate and the address hold wait state is inserted after t1 state. address setup wait state and address hold wait state insertion can be se t with the awc register for each cs space. this register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. the internal rom, internal ram, and on-chip peripheral i/o ar eas are not subject to address setup wait state and addr ess hold wait state insertion. 2. during address setup wait state and a ddress hold wait state, the wait pin-based external wait function is disabled. 3. write to the awc register after reset, a nd then do not change the set values. also, when changing the initial values of the awc register, do not access an external memory area until the settings are complete. 1 1 awc 1 1 1 1 1 1 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: ffffh r/w address: fffff488h cs0 cs1 csn signal csn signal ahwn 0 1 not inserted inserted specification of address hold wait state inserted in each csn space (n = 0, 1) aswn 0 1 not inserted inserted specification of address setup wait state inserted in each csn space (n = 0, 1) caution be sure to set bits 4 to 15 to ?1?. if they are set to ?0?, the ope ration is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 944 18.6.2 external wait function when a low-speed device or asynchronous system is c onnected, an arbitrary numbe r of wait states can be inserted in the bus cycle by the external wait pin (w ait) for synchronization wit h the external device. just as with programmable waits, acce ssing internal rom, internal ram, and on-chip peripheral i/o areas cannot be controlled by external waits. the external wait signal can be input asynchronously to the external bus clock frequency. 18.6.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycle specifi ed by the set value of the programmable wait and t he wait cycle controlled by the wait pin. wait control programmable wait wait by wait pin for example, if the timings of the programmable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. wait states inserted via the wait pin may be slower than the expected timing. in this case, use programmable waits to adjust the timing. figure 18-1. example of inserting wait states (1/2) (a) in separate bus mode t1 t2 tw tw tw clkout wait pin wait via wait pin programmable wait wait control remark the circle { indicates the sampling timing.
chapter 18 bus control function user?s manual u18279ej3v0ud 945 figure 18-1. example of inserting wait states (2/2) (b) in multiplexed bus mode t1 t2 tw tw tw clkout wait pin wait via wait pin programmable wait wait control t3 remark the circle { indicates the sampling timing. 18.6.4 bus cycles in which wait functi on is valid in the pd70f3454gc-8ea-a and 70f3454f1-da9-a, the number of waits can be specified for each memory block. the following shows t he bus cycles in which the wait function is valid and the re gisters used for wait setting. table 18-2. bus cycles in wh ich wait function is valid programmable wait setting bus cycle wait type register bit number of waits wait by wait pin address setup wait awc aswn 0, 1 (invalid) address hold wait awc ahwn 0, 1 (invalid) sram, external rom, external i/o cycles data wait dwc0 dwn2 to dwn0 0 to 7 (valid) remark n = 0, 1
chapter 18 bus control function user?s manual u18279ej3v0ud 946 18.7 idle state insertion function the idle state is inserted after a read cycle or a writ e cycle to the sram, external rom, or external i/o. (1) bus cycle control register (bcc) to facilitate interfacing with low-spe ed devices, an idle state (ti) can be inserted into the current bus cycle after the t2 state (after tw state if a data wait state is inserted) to secu re the data output float delay time on memory read access for each cs space. the bus cycle fo llowing the t2 state (or tw state) starts after the idle state is inserted. an idle state can be inserted after a write access by using the bus clock division control register (dvc). the idle state insertion setting can be specified by program using the bcc register. immediately after the system reset, idle state insertion is automatically programmed for all me mory blocks. for the timing when an idle state is inserted, see 18.8 bus timing . this register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, and on-chip peripher al i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, when changing the initial values of the bcc register, do not acc ess an external memory area until the settings are comple te. however, it is possible to access external memory areas whose initialization settings are complete. 3. the chip select signal (c sn) does not become active in the idle state (n = 0, 1). 1 1 bcc 0 0 1 1 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: aaaah r/w address: fffff48ah cs0 cs1 csn signal csn signal bcn1 0 1 not inserted inserted specification of idle state inserted in each csn space (n = 0, 1) insertion of an idle state can be specified for each csn space after completion of a read cycle or a write cycle. if the dvc.bcwi bit = 0, however, the idle state is inserted only after completion of a read cycle and not after completion of a write cycle. caution be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to ?0?, and set bits 5, 7, 9, 11, 13, and 15 to ?1?. if they are set other than a bove, the operation is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 947 (2) bus clock division control register (dvc) the dvc register is used to specify insertion of an idle state (ti) afte r completion of a write cycle, and an external bus clock frequency. this register can be read or written in 8-bit units. reset sets this register to 81h. cautions 1. the internal rom, internal ram, and on-chip peripher al i/o areas are not subject to idle state insertion. 2. write to the dvc register after reset once (i nitial setting), and then do not change the set value. also, do not access an external memory area until the initial setting of the dvc register is complete. however, it is possible to access external memory areas whose in itialization settings are complete. bcwi dvc 0 0 0 0 0 dvc1 dvc0 after reset: 81h r/w address: fffff48eh bcwi 0 1 not inserted inserted (only when bcc.bcn1 bit = 1) specification of idle state inserted after write cycle ends dvc1 0 0 1 1 dvc0 0 1 0 1 f clk /1 note f clk /2 setting prohibited f clk /4 specification of external bus clock frequency (f bus ) note can be set only when f clk 32 mhz. setting prohibited when 32 mhz < f clk 64 mhz cautions 1. be sure to set the clkout pin in the port mode before changing the setting of the dvc1 and dvc0 bits. changing the setting of the dvc1 and dvc0 bits while the alternate function (clkout) is used is prohibited. 2. set the external bus clock frequency (f bus ) in a range of 16 mhz f bus 32 mhz. 3. be sure to set bits 2 to 6 to ?0?. if they are set to ?1?, the ope ration is not guaranteed.
chapter 18 bus control function user?s manual u18279ej3v0ud 948 18.8 bus timing (1) read cycle (basic cycle) h t1 t2 t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note address data address wr0, wr1 (output) cs0, cs1 (output) note only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 949 (2) read cycle (when data wa it state (1 wait) insertion) h t1 t2 tw t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note address data wr0, wr1 (output) cs0, cs1 (output) address note only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 950 (3) read cycle (when idle state insertion) h t1 t2 t3 ti clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note address address data wr0, wr1 (output) cs0, cs1 (output) note only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 951 (4) read cycle (when data wait stat e (1 wait), idle state insertion) h t1 t2 tw t3 ti clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note address data address wr0, wr1 (output) cs0, cs1 (output) note only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 952 (5) read cycle (when address setup wait state, address hold wait state insertion) h tasw t1 tahw t2 t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note address data address wr0, wr1 (output) cs0, cs1 (output) note only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 953 (6) write cycle (basic cycle) h t1 t2 t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note 1 note 2 data address address wr0, wr1 (output) cs0, cs1 (output) notes 1. the levels of these signals are as follows, depending on the access data bus width. access data bus width wr1 wr0 16 bits low level low level 8 bits high level low level 2. only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 954 (7) write cycle (when data wait state (1 wait) insertion) h t2 t1 tw t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note 1 note 2 data address address wr0, wr1 (output) cs0, cs1 (output) notes 1. the levels of these signals are as follows, depending on the access data bus width. access data bus width wr1 wr0 16 bits low level low level 8 bits high level low level 2. only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 955 (8) write cycle (when idle state insertion) h t1 t2 t3 ti clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note 1 note 2 address data address wr0, wr1 (output) cs0, cs1 (output) notes 1. the levels of these signals are as follows, depending on the access data bus width. access data bus width wr1 wr0 16 bits low level low level 8 bits high level low level 2. only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 956 (9) write cycle (when data wait stat e (1 wait), idle state insertion) h t1 t2 tw t3 ti clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note 1 note 2 address address data wr0, wr1 (output) cs0, cs1 (output) notes 1. the levels of these signals are as follows, depending on the access data bus width. access data bus width wr1 wr0 16 bits low level low level 8 bits high level low level 2. only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 957 (10) write cycle (when address setup wait state, address hold wait state insertion) h tasw t1 tahw t2 t3 clkout (output) a0 to a7 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) note 1 note 2 data address address wr0, wr1 (output) cs0, cs1 (output) notes 1. the levels of these signals are as follows, depending on the access data bus width. access data bus width wr1 wr0 16 bits low level low level 8 bits high level low level 2. only the cs space that can be accessed becomes active. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 18 bus control function user?s manual u18279ej3v0ud 958 18.9 bus priority order there are two external bus cycles: inst ruction fetch and operand data access. in order of priority, operand data access is t he higher and instruction fetch is the lower. however, an instruction fetch may be inserted between a read access and write access during a read modify write access. table 18-3. bus priority order priority order external bus cycle bus master high operand data access cpu low instruction fetch cpu 18.10 boundary operation conditions 18.10.1 program space branching to the on-chip peripheral i/o ar ea is prohibited. if the above is performed, undefined data is fetched, and fetching from the external memory is not performed. 18.10.2 data space the pd70f3454gc-8ea-a and 70f3454f1-da9-a are pr ovided with an address misalign function. through this function, data can be alloca ted to all addresses, regardless of the data format (word or halfword). in the case of word data and halfword data, however, the bus cycle will be generated at least twice if data is not aligned to the boundary, which causes the bus efficiency to drop. (1) in the case of halfword-length data access when the address?s lsb is 1, a byte-len gth bus cycle will be generated 2 times. (2) in the case of word-length data access (a) when the address?s lsb is 1, bus cycles will be ge nerated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (b) when the address?s lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times.
user?s manual u18279ej3v0ud 959 chapter 19 dma functions (dma controller) the v850e/if3 and v850e/ig3 include a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfers between the intern al memory and on-chip peripheral i/o, or between on-chip peripheral i/os, based on requests by inte rrupts from the on-chip peripheral i/o (serial interface, timer, and a/d converter) or dma requests issued by software triggers. 19.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65536 (2 16 ) ? transfer type: 2-cycle transfer ? three transfer modes ? single transfer mode ? single-step transfer mode ? block transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (serial interface, timer, a/d converter) ? requests by software trigger ? transfer targets ? internal memory ? on-chip peripheral i/o ? on-chip peripheral i/o ? on-chip peripheral i/o ? next address setting function
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 960 19.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control block address control block count control block channel control block dmac v850e/if3, v850e/ig3 dma source address register ( dsanh/dsanl) dma transfer count register ( dbcn) dma destination address register ( ddanh/ddanl) dma channel control register ( dchcn) dma addressing control register ( dadcn) dma trigger factor register n ( dtfrn) remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 961 19.3 control registers 19.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma transfer source address (28 bits) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new transfer source address for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). when setting the next address, the newly set value of the dsan register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the dchcn.tcn bit is set to 1, or when the dchcn.initn bit is set to 1 (n = 0 to 3). however, the set value of the dsan register is invalid even when the dchcn.enn bit is cleared to 0 to disable dma transfer and then the dsan register is set. (1) dma source address registers 0h to 3h (dsa0h to dsa3h) the dsa0h to dsa3h registers can be read or written in 16-bit units. reset makes these registers undefined. cautions 1. when setting an a ddress of an on-chip peripheral i/o re gister for the source address, be sure to specify an address between ffff000h and fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. 2. do not set the dsanh regi ster while dma is suspended. irsn on-chip peripheral i/o internal ram irsn 0 1 san27 to san16 dma transfer source specification dsanh (n = 0 to 3) 0 0 0 san27 san26 san25 san24 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah set the dma transfer source address (a27 to a16). during dma transfer, these bits store the next dma transfer source address. 15 14 13 12 11 10 9 8 san23 san22 san21 san20 san19 san18 san17 san16 76 54 32 1 0 caution be sure to set bits 14 to 12 to ?0?. if they are set to ?1?, the ope ration is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 962 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) the dsa0l to dsa3l registers can be read or written in 16-bit units. reset makes these registers undefined. san15 san15 to san0 dsanl (n = 0 to 3) san14 san13 san12 san11 san10 san9 san8 after reset: undefined r/w address: dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h set the dma transfer source address (a15 to a0). during dma transfer, these bits store the next dma transfer source address. 15 14 13 12 11 10 9 8 san7 san6 san5 san4 san3 san2 san1 san0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 963 19.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma transfer destination address (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new transfer destination address for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). when setting the next address, the newly set value of the ddan register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the dchcn.tcn bit is set to 1, or when the dchcn.initn bit is set to 1 (n = 0 to 3). however, the set value of the ddan register is invalid even when the dchcn.enn bit is cleared to 0 to disable dma transfer and then the ddan register is set. (1) dma destination address register s 0h to 3h (dda0h to dda3h) the dda0h to dda3h registers can be read or written in 16-bit units. reset makes these registers undefined. cautions 1. when setting an address of an on-chip peripheral i/o register for the destination address, be sure to specify an address between ffff000h and fffffffh. an address of the on- chip peripheral i/o register image (3fff 000h to 3ffffffh) must not be specified. 2. do not set the ddanh regist er while dma is suspended. iran on-chip peripheral i/o internal ram iran 0 1 dan27 to dan16 dma transfer destination specification ddanh (n = 0 to 3) 0 0 0 dan27 dan26 dan25 dan24 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh set the dma transfer destination address (a27 to a16). during dma transfer, these bits store the next dma transfer destination address. 15 14 13 12 11 10 9 8 dan23 dan22 dan21 dan20 dan19 dan18 dan17 dan16 76 54 32 1 0 caution be sure to set bits 14 to 12 to ?0?. if they are set to ?1?, the ope ration is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 964 (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) the dda0l to dda3l registers can be read or written in 16-bit units. reset makes these registers undefined. dan15 dan15 to dan0 ddanl (n = 0 to 3) dan14 dan13 dan12 dan11 dan10 dan9 dan8 after reset: undefined r/w address: dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch set the dma transfer destination address (a15 to a0). during dma transfer, these bits store the next dma transfer destination address. 15 14 13 12 11 10 9 8 dan7 dan6 dan5 dan4 dan3 dan2 dan1 dan0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 965 19.3.3 dma transfer count regi sters 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer count for dma channel n (n = 0 to 3). these registers store the remaining transfer count during dma transfer. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new dma byte transfer count for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). when setting the next address, the newly se t value of the dbcn register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the dchcn.tcn bit is set to 1, or when the dchcn.initn bit is set to 1 (n = 0 to 3). however, the set value of the dbcn register is invalid even when the dchcn.enn bit is cleared to 0 to disable dma transfer and then the dbcn register is set. these registers are decremented by 1 for each tr ansfer, and transfer ends when a borrow occurs. these registers can be read or written in 16-bit units. reset makes these registers undefined. caution do not set the dbcn regi ster while dma is suspended. remark if the dbcn register is read during dma transfer afte r a terminal count has occurred without the register being overwritten, the value set immediately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). bcn15 transfer count 1 or remaining transfer count transfer count 2 or remaining transfer count : transfer count 65536 (2 16 ) or remaining transfer count bcn15 to bcn0 0000h 0001h : ffffh transfer count setting (store remaining transfer count during dma transfer) dbcn (n = 0 to 3) bcn14 bcn13 bcn12 bcn11 bcn10 bcn9 bcn8 after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h 15 14 13 12 11 10 9 8 bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 966 19.3.4 dma addressing control regi sters 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during a dma operation. these registers can be read or written in 16-bit units. reset sets these registers to 0000h. cautions 1. the dsn0 bit sets how many bits of data are to be transferred. if the transfer data size is set to 16 bits, transfer is always started from an address with the lowest bit of the address aligned to ?0?. in this case, transfer cannot be started from an odd address. 2. set the dadcn register when the target channel is in one of the following periods (the operation is not guaranteed if the regi ster is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from end of dma transfer (after termi nal count) to the generation of the next dma transfer request ? period from forced termination of dma transf er (after the dchcn.initn bit was set to 1) to the generation of the next dma transfer request 0 8 bits 16 bits dsn0 0 1 setting of transfer data size for dma transfer dadcn (n = 0 to 3) dsn0 0 0 0 0 0 0 increment decrement fixed setting prohibited sadn1 0 0 1 1 sadn0 0 1 0 1 setting of count direction of transfer source address for dma channel n increment decrement fixed setting prohibited dadn1 0 0 1 1 dadn0 0 1 0 1 setting of count direction of transfer destination address for dma channel n single transfer mode single-step transfer mode setting prohibited block transfer mode tmn1 0 0 1 1 tmn0 0 1 0 1 setting of transfer mode during dma transfer after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h 15 14 13 12 11 10 9 8 sadn1 sadn0 dadn1 dadn0 tmn1 tmn0 0 0 76 54 32 1 0 caution be sure to set bits 15, 13 to 8, 1, and 0 to ?0?. if they are set to ?1?, the operation is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 967 19.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers that co ntrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only.) reset sets these registers to 00h. cautions 1. if transfer has been ended with the mlen bit set to 1 and if the next transfer request is made by dma transfer (hardwar e dma) that is started by an inte rrupt from an on-chip peripheral i/o, the next transfer is executed with the tcn bit set to 1 (not automatically cleared to 0). 2. set the mlen bit when the target channel is in one of the following periods (the operation is not guaranteed if the bit is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from end of dma transfer (after termi nal count) to the generation of the next dma transfer request ? period from forced termination of dma transfer (after the initn bit w as set to 1) to the generation of the next dma transfer request 3. if dma transfer is forcibly terminated in the last transfer c ycle with the mlen bit set to 1, the operation is performed in the same manner as when transfer is ended (the tcn bit is set to 1). (the enn bit is cleared to 0 upon forced termination, regardless of the value of the mlen bit.) in this case, the enn bi t must be set to 1 and the tcn bit must be read (cleared to 0) when the next dma transfer request is made. 4. upon end of dma transfer (during terminal c ount), each bit is updated with the enn bit cleared to 0 and then the tcn bit set to 1. if the st atuses of the tcn bit and enn bit are polled and if the dchcn register is r ead while each bit is updated, theref ore, a value indicating the status ?transfer not ended and prohibited? (tcn bit = 0 and enn bit = 0) may be read (this is not abnormal). 5. be sure to read (clear to 0) the tcn bit after end of dma tr ansfer (after terminal count). the tcn bit does not have to be read (cleared to 0) only if the following two conditions are satisfied. ? the mlen bit is set to 1 upon end of dma transfer (during terminal count). ? the next dma transfer (hardware dma) star t factor is an interrupt from the on-chip peripheral i/o (hardware dma) if even one of these conditions is not satisfied, be sure to read (clear to 0) the tcn bit before the next dma transfer request is generated. the operation cannot be guaranteed if the n ext dma transfer request is generated while the tcn bit is set to 1. 6. do not set the enn and stgn bits while dma is suspended. otherwi se, the operation is not guaranteed. 7. do not end dma transfer by clearing the enn bit to 0. 8. the relationship between the status of dma transfer and the register value is as follows. ? dma transfer is in progress: tcn bit = 0, enn bit = 1 ? dma transfer is aborted: tcn bit = 0, enn bit = 0 ? dma transfer is stopped (ends): tcn bit = 1
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 968 tcn dma transfer has not ended. dma transfer has ended. tcn note 1 0 1 mlen status bit that indicates whether dma transfer via dma channel n has ended or not dchcn (n = 0 to 3) 0 0 0 mlen initn stgn enn after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h when this bits is set (1) at dma transfer end (at the terminal count output), the enn bit is not cleared (0) and the dma transfer enabled state is retained. if the next dma transfer start factor is input from an on-chip peripheral i/o (hardware dma), the dma transfer request is acknowledged even if the tcn bit is not read. if the next dma transfer start factor is input by setting the stgn bit to 1 (software dma), the dma transfer request is acknowledged if the tcn bit is read and cleared (0). when this bit is cleared (0) at dma transfer end (at the terminal count output), the enn bit is cleared (0) and the dma transfer disabled state is entered. at the next dma transfer request, the tcn bit must be read and the enn bit must be set (1). initn note 2 if this bit is set (1) during dma transfer or while dma is suspended, dma transfer is forcibly terminated. stgn note 2 if this bit is set (1) in the dma transfer enabled state (tcn bit = 0, enn bit = 1), dma transfer is started. <7> 6 5 4 <3> <2> <1> <0> this bit is set (1) at the last dma transfer and cleared (0) when it is read. if dma transfer is executed to transfer data from the internal ram, this bit is set (1) 4 clocks after end of the last transfer. dma transfer disabled dma transfer enabled enn 0 1 setting whether dma transfer via dma channel n is to be enabled or disabled ? this bit is cleared (0) when dma transfer ends. it is also cleared (0) when dma transfer is forcibly terminated by setting (1) the initn bit. ? if the enn bit is set (1), do not set it until dma transfer has been ended the number of times set by the dbcn register or dma transfer is forcibly terminated by the initn bit. notes 1. tcn bit is read-only. 2. initn and stgn bits are write-only. if these bits are read, 0 is read. caution be sure to set bits 6 to 4 to ?0?. if they are set to ?1?, the ope ration is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 969 19.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that c ontrol the dma transfer start trigger via interrupt requests from on-chip peripheral i/o. the interrupt requests set by these regist ers serve as dma transfer start factors. these registers can be read or written in 8-bit or 1-bit unit s. however, only bit 7 (dfn) can be read or written in 1- bit units; bits 5 to 0 (ifcn5 to ifcn0) can only be read or written in 8-bit units. reset sets these registers to 00h. cautions 1. be sure to follow the steps be low when changing the dtfrn register settings. ? when the values to be set to the ifcn5 to ifcn0 bits are not set to the ifcm5 to ifcm0 bits of another channel (n = 0 to 3, m = 0 to 3, n m) <1> follow steps <3> to <5> when the dchcn.enn bi t is cleared to 0, and follow steps <2> to <5> when the enn bit is set to 1. <2> stop the dman operation of the channel to be rewr itten (dchcn.initn bit = 1). <3> change the dtfrn register settings. (be sure to set dfn bit = 0 and change the settings in the 8-bit manipulation.) <4> to clear a dma transfer request, clear the dma transfer request flag (dtfrn.dfn) to 0. <5> enable the dman operation (enn bit = 1). ? when the values to be set to the ifcn5 to ifcn 0 bits are set to the ifcm5 to ifcm0 bits of another channel (n = 0 to 3, m = 0 to 3, n m) <1> follow steps <4> to <6> when the dchcn.enn bi t is cleared to 0, and follow steps <2> to <6> when the enn bit is set to 1. <2> stop the dman operation of the channel to be rewr itten (dchcn.initn bit = 1). <3> stop the dmam operation of the channel where the same values are set to the ifcm5 to ifcm0 bits as th e values to be used to rewr ite the ifcn5 to ifcn0 bits (dchcm.initm bit = 1). <4> change the dtfrn register settings. (be sure to set the dfn bit = 0 and change the settings in the 8-bit manipulation.) <5> to clear a dma transfer request, clear the dma transfer request flag (dtfrn.dfn) to 0. <6> enable the dman operation (enn and emm bits = 1). 2. an interrupt request from an on-chip periphe ral i/o input in the standby mode (idle or stop mode) is held pending as a dma transfer start f actor. the held dma start factor is executed after restoring to the normal operation mode. 3. if the start factor of dma transfer is change d using the ifcn5 to ifcn0 bits, be sure to set (0) the dfn bit by instruct ion immediately after.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 970 dma transfer not requested dma transfer requested dfn note 0 1 dma transfer request flag dtfrn (n = 0 to 3) after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 <7>6543210 note do not set the dfn bit to ?1? by software. if the interrupt specified as the dma transfer start fa ctor occurs and it is necessary to clear the dma transfer request while dma transfer is disabled (including when it is forcibly terminated by software), stop the operation of the source causing the interrupt, and then write 0 to the dfn bit (for example, disable reception in the case of serial reception). if it is clear that the interrupt will not occur until dma transfer is resumed next, it is not necessary to stop the operation of the source causing the interrupt. cautions 1. for the ifcn5 to ifcn0 bits, see table 19-1 dma transfer start factors. 2. be sure to set bit 6 to ?0?. if it is set to ?1?, the operat ion is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 971 table 19-1. dma transfer start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intlvil 0 0 0 0 1 0 intlvih 0 0 0 0 1 1 intp11 0 0 0 1 0 0 intp12 0 0 0 1 0 1 intp13 0 0 0 1 1 0 intp15 0 0 0 1 1 1 inttb0ov_base note 0 0 1 0 0 0 inttb1ov_base note 0 0 1 0 0 1 intcmp0l 0 0 1 0 1 0 intcmp0f 0 0 1 0 1 1 intcmp1l 0 0 1 1 0 0 intcmp1f 0 0 1 1 0 1 inttb0cc0 0 0 1 1 1 0 inttb0cc1 0 0 1 1 1 1 inttb0cc2 0 1 0 0 0 0 inttb0cc3 0 1 0 0 0 1 inttb1cc0 0 1 0 0 1 0 inttb1cc1 0 1 0 0 1 1 inttb1cc2 0 1 0 1 0 0 inttb1cc3 0 1 0 1 0 1 inttteqc00 0 1 0 1 1 0 inttteqc01 0 1 0 1 1 1 inttteqc10 0 1 1 0 0 0 inttteqc11 0 1 1 0 0 1 intta0cc0 0 1 1 0 1 0 intta0cc1 0 1 1 0 1 1 intta1cc0 0 1 1 1 0 0 intta1cc1 0 1 1 1 0 1 intta2cc0 0 1 1 1 1 0 intta2cc1 0 1 1 1 1 1 intta3cc0 1 0 0 0 0 0 intta3cc1 1 0 0 0 0 1 intta4cc0 1 0 0 0 1 0 intta4cc1 1 0 0 0 1 1 intdma0 1 0 0 1 0 0 intdma1 1 0 0 1 0 1 intdma2 1 0 0 1 1 0 intdma3 remark n = 0 to 3 note inttbaov_base is an interrupt signal before inttbao v is culled by the tmqa option in the 6-phase pwm output mode (a = 0, 1). the inttbacc0 is also an interrupt signal before culling. for details, see figure 10-2 tmqn option .
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 972 table 19-1. dma transfer start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 0 1 1 1 intubtir 1 0 1 0 0 0 intubtit 1 0 1 0 0 1 intubtif 1 0 1 0 1 0 intua0r 1 0 1 0 1 1 intua0t 1 0 1 1 0 0 intcb0r 1 0 1 1 0 1 intcb0t 1 0 1 1 1 0 intua1r 1 0 1 1 1 1 intua1t 1 1 0 0 0 0 intcb1r 1 1 0 0 0 1 intcb1t 1 1 0 0 1 0 intua2r 1 1 0 0 1 1 intua2t 1 1 0 1 0 0 intcb2r 1 1 0 1 0 1 intcb2t 1 1 0 1 1 0 intiic 1 1 0 1 1 1 intad0 1 1 1 0 0 0 intad1 1 1 1 0 0 1 intad2 1 1 1 0 1 0 inttm0eq0 1 1 1 0 1 1 inttm1eq0 1 1 1 1 0 0 inttm2eq0 1 1 1 1 0 1 inttm3eq0 other than above setting prohibited remark n = 0 to 3 the relationship between the interrupt source and the dma transfer trigger is as follows (n = 0 to 3). ifcn0 to ifcn5 internal dma request signal interrupt source selector cautions 1. dma transfer starts when an interrupt fa ctor set by the ifcn5 to if cn0 bits occur. to prevent interrupt servicing from being executed, mask the interrupt by setting the interrupt control register. dma transfer starts even if an interrupt is masked. 2. if the frequency of the cpu clock falls be low the clock of each on-ch ip peripheral i/o because of the setting of prescaler 2 of the clock genera tor, the dma transfer start factor may not be acknowledged.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 973 19.4 transfer modes 19.4.1 single transfer mode in single transfer mode, the dmac releases the bus at eac h byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. if another dma trans fer request with a lower priority occurs one clock after single transfer has been completed, however, this request does not take precedence even if the previous dma transfer request signal with a higher priority remains acti ve. dma transfer with the newly requested lower priority request is executed after the cpu bus has been released. figures 19-1 to 19-4 show examples of single transfer. figure 19-1. single transfer example 1 cpu dmarq3 (internal signal) cpu dma3 cpu dma3 cpu dma3 cpu cpu cpu cpu cpu cpu dma3 cpu dma3 cpu cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 19-2 shows an example of a single transfer in which a higher priority dma request is issued. dma channels 0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode. figure 19-2. single transfer example 2 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dma1 cpu dma2 dma2 cpu dma3 cpu dma3 dmarq3 (internal signal) dmarq2 (internal signal) dmarq1 (internal signal) dmarq0 (internal signal) dma channel 3 terminal count dma channel 0 terminal count dma channel 2 terminal count note note note note dma channel 1 terminal count note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 974 figure 19-3 is an example of single transfer where a dma transfer request with a lower priority is issued one clock after single transfer has been completed. dma channels 0 and 3 are used for single transfer. if two dma transfer request signals become active at the same time, tw o dma transfer operations are alternately executed. figure 19-3. single transfer example 3 cpu cpu cpu dma0 dma0 cpu dma0 cpu dma0 cpu dma0 cpu cpu cpu dma0 cpu dma3 cpu dma3 dma channel 3 terminal count dma channel 0 terminal count dmarq3 (internal signal) dmarq0 (internal signal) note note note note note note note note the bus is always released. figure 19-4 is an example of single transfer where two or more dma transfer requests with a lower priority are issued one clock after single transfer has been completed. dma channels 0, 2, and 3 are used for single transfer. if three or more dma transfer request signals become active at the same time, two dma transfer operations are alternately executed, starting from the one with the highest priority. figure 19-4. single transfer example 4 cpu dma3 cpu dma3 cpu dma2 cpu dma2 cpu dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 cpu dma0 dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dmarq2 (internal signal) dmarq3 (internal signal) dmarq0 (internal signal) note note note note note note note note note note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 975 19.4.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. if there is a subsequent dma transfer request signal, transfer is performed again. th is operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows an example of a single-step transfer. figure 19-6 shows an example of single-step transfer made in which a higher priority dma request is issued. dma channels 0 and 1 are in t he single-step transfer mode. figure 19-5. single-step transfer example 1 cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu cpu dma channel 1 terminal count dmarq1 (internal signal) note note note note the bus is always released. figure 19-6. single-step transfer example 2 cpu cpu cpu dma1 cpu dma1 cpu dma0 cpu dma0 cpu dma0 cpu dma1 cpu dma1 cpu dma channel 0 terminal count dma channel 1 terminal count dmarq1 (internal signal) dmarq0 (internal signal) note note note note note note note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 976 19.4.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases the bus, another dma transfer can be acknowledged. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 2 and 3 are in the block transfer mode. figure 19-7. block transfer example cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma3 dma3 cpu dma2 dma2 dma2 dma2 dma2 dma channel 3 terminal count the bus is always released. dmarq3 (internal signal) dmarq2 (internal signal)
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 977 19.5 transfer types 19.5.1 2-cycle transfer in 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. caution an idle cycle of 1 to 2 clocks is always inserted between a read cycle and a write cycle. 19.6 transfer target 19.6.1 transfer type and transfer target table 19-2 lists the relationship between the tran sfer type and transfer target. the mark ? ? means ?transfer possible?, and the mark ? ? means ?transfer impossible?. table 19-2. relationship between tran sfer type and transfer target destination internal rom on-chip peripheral i/o note internal ram on-chip peripheral i/o note internal ram source internal rom note if the transfer target is the on-chip peripher al i/o, only the single transfer mode can be used. cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with ? ? in table 19-2. 2. addresses between 3fff000h and 3ffffffh cannot be specified for the source and destination address of dma transfer. be sure to specify an a ddress between ffff 000h and fffffffh. remark if dma transfer is executed to transfer data of an on-ch ip peripheral i/o register (as a transfer source or destination), be sure to specify the same transfer size as the register size. for example, to execute dma transfer of an 8-bit register, be sure to specify byte (8-bit) transfer. 19.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 in the block transfer mode, the channel used for transfer is never switched. in the single-step transfer mode, if a hi gher priority dma transfer request is issued while the bus is released, the higher priority dma transfer request is acknowledged.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 978 19.8 next address setting function the dsanh, dsanl, ddanh, ddanl, and dbcn registers are two-stage fifo buffer registers consisting of a master register and a slave register (n = 0 to 3). when the terminal count is issued, these registers ar e automatically rewritten wit h the value that was set immediately before. if new dma transfer setting is made to these registers duri ng dma transfer, therefore, t he values of the registers are automatically updated to the new value after completion of transfer note . note to make new dma transfer setting, confirm that dm a transfer has been started. if a new setting is made before the start of dma transfer, t he set value is overwritten to bot h the master and slave registers. figure 19-8 shows the configur ation of the buffer register. figure 19-8. buffer register configuration data read data write master register slave register address/ count controller internal bus the actual dma transfer is executed in accor dance with the contents of the slave register. the set value to be reflected upon the master register and slave register differs as follows, depending on the timing (period) of setting. (1) period from system reset to the genera tion of the first dma transfer request the set values are reflected on bot h the master and slave registers. (2) during dma transfer (period fr om the generation of dma transfer request to completion of dma transfer) the set value is reflected only on the master register an d not on the slave register (the slave register holds the set value for the next dma transfer). after completion of dma transfer, however, the contents of the master register are aut omatically overwritten to the slave register. if the value of a register is read during this perio d, the value of the slave register is read. to check that dma transfer has been started, confirm that the first transfer has been executed by reading the dbcn register (n = 0 to 3). (3) period from completion of dma tran sfer to start of next dma transfer the set value is reflected on both the master and slave registers. remark ?completion of dma transfer? means either of the following cases. ? end of dma transfer (terminal count) ? forced termination of dma transfer (setting dchcn.initn bit to 1).
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 979 19.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. cautions 1. do not use both start factors ((1) and (2 )) in combination for the same channel (if both start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified). the operation is not guara nteed if both start factors are used in combination. 2. if dma transfer is started via software and if the software does not correctly detect whether the expected dma tr ansfer operation has been ended thr ough manipulation (setting to 1) of the dchcn.stgn bit, it cannot be guaranteed wh ether the next (second) manipulation of the stgn bit corresponds to the start of ?the next dma transfer expected by software? (n = 0 to 3). for example, suppose single transfer is starte d by manipulating the stgn bit. even if the stgn bit is manipulated next (the second time) without checking by software whether the single transfer has actually b een executed, the next (second) dma transfer is not always executed. this is because the stgn bit may be manipulated th e second time before the first dma transfer is started or ended because, for example, dma transfer with a higher priority had already been started wh en the stgn bit was manipu lated for the first time. it is therefore necessary to manipulate the stgn bit the n ext time (the second time) after checking whether dma transfer started by the fi rst manipulation of th e stgn bit has been ended. end of dma transfer can be checked by checking the contents of the dbcn register. (1) transfer start triggered by software if the dchcn.stgn, dchcn.enn, and dchcn.tcn bits are set as follows, dma transfer is started by software request (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (2) transfer start triggered by re quest from on-chip peripheral i/o if, when the dchcn.enn and dchcn.tcn bits are set as show n below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 980 19.10 forcible termination dma transfer can be forcibly terminated by the dchcn.initn bit (n = 0 to 3). an example of forcible termination by the dchcn .initn bit is illustrated below (n = 0 to 3). figure 19-9. example of forcible termination of dma transfer (a) block transfer via dma channel 3 is st arted during block transfer via dma channel 2 cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu dmarq2 (internal signal) dmarq3 (internal signal) dma channel 3 transfer start dma channel 3 terminal count forcible termination of dma channel 2 transfer, bus released dsa2, dda2, dbc2, dadc2, dchc2 register set dchc2 (init2 bit = 1) register set dsa3, dda3, dbc3, dadc3, dchc3 register set e22 bit = 1 tc2 bit = 0 e22 bit 0 tc2 bit = 0 e33 bit = 1 tc3 bit = 0 e33 bit 0 tc3 bit 1 (b) when transfer is suspended during dma channel 1 block transf er, and transfer under another condition is executed cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (internal signal) forcible termination of dma channel 1 transfer, bus released dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 0 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark the values of the dsan, ddan, and dbcn registers (n = 0 to 3) are retained even when dma transfer is forcibly terminated, because these regist ers are fifo-format buffer registers. the next transfer condition can be set to these registers even while dma transfer is in progress. on the other hand, the setting of the dadcn an d dchcn registers is invalid during dma transfer because these registers are not buffer registers (see 19.8 next address setting function , 19.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) , and 19.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ).
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 981 19.11 times related to dma transfer the overhead before and after dma transfer and minimum ex ecution clock for dma transfer are shown below. table 19-3. number of minimu m execution clocks in dma cycle dma cycle minimum number of execution clocks <1> response time to dma request 4 clocks note 1 internal ram access 2 clocks note 2 <2> memory access on-chip peripheral i/o register acce ss 4 clocks + number of wait cycles specified by vswc register notes 1. if an external interrupt (intpn) is specified as t he dma transfer start factor, noise elimination time is added (n = 11 to 13, 15, 17, 18). 2. two clocks for the dma cycle the minimum number of execution clocks during the dma cycle in each mode is as follows. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) block transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) number of transfers note one clock is always insert ed between the read cycl e and write cycle of dma transfer. 19.12 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma targets (internal ram or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not su pported. if the source or the destination address is set to an odd address, the lsb of the address is forcibly handled as ?0?. (3) bus arbitration for cpu because the dma controller has a higher priority bus ma stership than the cpu, a cpu access that takes place during dma transfer is held pending unt il the dma transfer cycle is complete d and the bus is released to the cpu. however, the cpu can access the internal rom and ram to/from which dma transfer is not being executed. ? the cpu can access the internal rom when dma transfer is being executed between the on-chip peripheral i/o and internal ram. ? the cpu can access the internal rom and internal ram when dma transfer is being executed between on- chip peripheral i/os.
chapter 19 dma functions (dma controller) user?s manual u18279ej3v0ud 982 (4) dma start factors note with caution when setting two or more dma channels with the same factor. if two or more dma channels are started with the same factor, the dma channel with a lower priority may be acknowledged before the dma channel with a higher priority. (5) program execution and dma transfer with internal ram do not execute dma transfer to/from the internal ram a nd an instruction in the internal ram simultaneously. (6) timing of setting dchcn.tcn bit the dchcn.tcn bit is usually set to 1 at the end of dma trans fer. in the case of dma transfer that is initiated from the internal ram, however, it is set 4 cl ocks after end of the last transfer (n = 0 to 3). (7) read values of dsan and ddan registers if the values of the dsan and ddan registers are read during dma transfer, values in the middle of being updated may be read (n = 0 to 3). for example, if the dsanh register and the dsanl register are read in that order when the value of the dma transfer source address (dsan regist er) is ?0000ffffh? and the counting di rection is incremental (when the sadn1 and sadn0 bits of the dadcn register = 00), the value of the dsanl register differs as follows depending on whether dma transfer is executed immedi ately after the dsanh register has been read. (a) if dma transfer does not occur while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> reading dsanl register: dsanl = ffffh (b) if dma transfer occurs while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00010000h <4> reading dsanl register: dsanl = 0000h (8) clr1, not1, and set1 instructions write the clr1, not1, and set1 instructions after reading a register and then manipulating the target bit. to set the dchcn.enn bit to 1 by using the set1 instructi on, therefore, the tcn bit is cleared to 0 when the dchcn.tcn bit = 1 (n = 0 to 3). 19.13 dma transfer end when dma transfer ends and the dchcn.tcn bit is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3).
user?s manual u18279ej3v0ud 983 chapter 20 interrupt/exception processing function the v850e/if3 and v850e/ig3 are provided with a dedicated interrupt controller (intc) for interrupt servicing and can process a total of 89 to 96 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on program execution. the v850e/if3 and v850e/ig3 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception proce ssing can be started by the trap instru ction (software exception) or by generation of an exception event (i.e. fetc hing of an illegal opcode) (exception trap). 20.1 features { interrupts ? non-maskable interrupts: 1 source (external: none, internal: 1 source) ? maskable interrupts (the number of maskable in terrupt sources differs depending on the product) v850e/if3: 88 sources (external: 15 sources, internal: 73 sources) v850e/ig3: 95 sources (external: 21 sources, internal: 74 sources) ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt contro l according to priority ? masks can be specified for each maskable interrupt request. ? noise elimination, edge detection, and valid edge specification for ex ternal interrupt request signals. { exceptions ? software exceptions: 32 sources ? exception traps: 2 sources ( illegal opcode exception and debug trap) interrupt sources are listed in table 20-1.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 984 table 20-1. interrupt source list (1/4) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc ? reset pin input pin reset interrupt reset ? wdt overflow (wdtres) wdt ? 0000h 00000000h undefined non-maskable interrupt intwdt ? wdt overflow wdt ? 0010h 00000010h nextpc exception trap0n note 1 ? trap instruction ? ? 004nh 00000040h nextpc software exception exception trap1n note 1 ? trap instruction ? ? 005nh 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal instruction code/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intlvil lvilic lvi low level voltage detection lvi 0 0080h 00000080h nextpc interrupt intlvih lvihic lvi high level voltage detection lvi 1 0090h 00000090h nextpc interrupt intp00 pic00 intp00 pin valid edge input pin 2 00a0h 000000a0h nextpc interrupt intp01 pic01 intp01 pin valid edge input pin 3 00b0h 000000b0h nextpc interrupt intp02 note 2 pic02 note 2 intp02 pin valid edge input pin 4 00c0h 000000c0h nextpc interrupt intp03 note 2 pic03 note 2 intp03 pin valid edge input pin 5 00d0h 000000d0h nextpc interrupt intp04 note 2 pic04 note 2 intp04 pin valid edge input pin 6 00e0h 000000e0h nextpc interrupt intp05 note 2 pic05 note 2 intp05 pin valid edge input pin 7 00f0h 000000f0h nextpc interrupt intp06 note 2 pic06 note 2 intp06 pin valid edge input pin 8 0100h 00000100h nextpc interrupt intp07 note 2 pic07 note 2 intp07 pin valid edge input pin 9 0110h 00000110h nextpc interrupt intp08 pic08 intp08 pin valid edge input pin 10 0120h 00000120h nextpc interrupt intp09 pic09 intp09 pin valid edge input pin 11 0130h 00000130h nextpc interrupt intp10 pic10 intp10 pin valid edge input pin 12 0140h 00000140h nextpc interrupt intp11 pic11 intp11 pin valid edge input pin 13 0150h 00000150h nextpc interrupt intp12 pic12 intp12 pin valid edge input pin 14 0160h 00000160h nextpc interrupt intp13 pic13 intp13 pin valid edge input pin 15 0170h 00000170h nextpc interrupt intp14 pic14 intp14 pin valid edge input pin 16 0180h 00000180h nextpc interrupt intp15 pic15 intp15 pin valid edge input pin 17 0190h 00000190h nextpc interrupt intp16 pic16 intp16 pin valid edge input pin 18 01a0h 000001a0h nextpc interrupt intp17 pic17 intp17 pin valid edge input pin 19 01b0h 000001b0h nextpc interrupt intp18 pic18 intp18 pin valid edge input pin 20 01c0h 000001c0h nextpc interrupt intcmp0l cmpic0l adc0 overvoltage detection l (comparator output) adc0 (comparator) 21 01d0h 000001d0h nextpc interrupt intcmp0f cmpic0f adc0 overvoltage detection f (comparator output) adc0 (comparator) 22 01e0h 000001e0h nextpc interrupt intcmp1l cmpic1l adc1 overvoltage detection l (comparator output) adc1 (comparator) 23 01f0h 000001f0h nextpc maskable interrupt intcmp1f cmpic1f adc1 overvoltage detection f (comparator output) adc1 (comparator) 24 0200h 00000200h nextpc notes 1. n = 0 to fh 2. v850e/ig3 only
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 985 table 20-1. interrupt source list (2/4) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc interrupt inttb0ov tb0ovic tab0 overflow note 2 tab0 25 0210h 00000210h nextpc interrupt inttb0cc0 tb0cci c0 tab0ccr0 capture input/ compare match note 3 tab0 26 0220h 00000220h nextpc interrupt inttb0cc1 tb0cci c1 tab0ccr1 capture input/ compare match tab0 27 0230h 00000230h nextpc interrupt inttb0cc2 tb0cci c2 tab0ccr2 capture input/ compare match tab0 28 0240h 00000240h nextpc interrupt inttb0cc3 tb0cci c3 tab0ccr3 capture input/ compare match tab0 29 0250h 00000250h nextpc interrupt inttb1ov tb1ovic tab1 overflow note 2 tab1 30 0260h 00000260h nextpc interrupt inttb1cc0 tb1cci c0 tab1ccr0 capture input/ compare match note 3 tab1 31 0270h 00000270h nextpc interrupt inttb1cc1 tb1cci c1 tab1ccr1 capture input/ compare match tab1 32 0280h 00000280h nextpc interrupt inttb1cc2 tb1cci c2 tab1ccr2 capture input/ compare match tab1 33 0290h 00000290h nextpc interrupt inttb1cc3 tb1cci c3 tab1ccr3 capture input/ compare match tab1 34 02a0h 000002a0h nextpc interrupt intttiov0 tt0ovic tmt0 overflow tmt0 35 02b0h 000002b0h nextpc interrupt inttteqc00 tt0ccic0 tt0ccr0 capture input note 4 / compare match tmt0 36 02c0h 000002c0h nextpc interrupt inttteqc01 tt0ccic1 tt0ccr1 capture input note 4 / compare match tmt0 37 02d0h 000002d0h nextpc interrupt inttiec0 note 1 tt0iecic note 1 encoder input interrupt 0 tmt0 38 02e0h 000002e0h nextpc interrupt intttiov1 tt1ovic tmt1 overflow tmt1 39 02f0h 000002f0h nextpc interrupt inttteqc10 tt1ccic0 tt1ccr0 capture input/ compare match tmt1 40 0300h 00000300h nextpc interrupt inttteqc11 tt1ccic1 tt1ccr1 capture input/ compare match tmt1 41 0310h 00000310h nextpc interrupt inttiec1 tt1iecic encoder input in terrupt 1 tmt1 42 0320h 00000320h nextpc maskable interrupt intta0ov ta0ovic taa0 overflow taa0 43 0330h 00000330h nextpc notes 1. v850e/ig3 only 2. when tabm is used in the 6-phas e pwm output mode, it functions as inttbmov (trough interrupt) from the tmqm option (tmqopm) (m = 0, 1). 3. when tabm is used in the 6-phase pwm output mode, it functions as inttbmcc0 (peak interrupt) from the tmqm option (tmqopm) (m = 0, 1). 4. v850e/ig3 only in the v850e/if3, compare match only
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 986 table 20-1. interrupt source list (3/4) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc interrupt intta0cc0 ta0ccic0 ta0ccr0 com pare match taa0 44 0340h 00000340h nextpc interrupt intta0cc1 ta0ccic1 ta0ccr1 com pare match taa0 45 0350h 00000350h nextpc interrupt intta1ov ta1ovic taa1 overflow taa1 46 0360h 00000360h nextpc interrupt intta1cc0 ta1ccic0 ta1ccr0 com pare match taa1 47 0370h 00000370h nextpc interrupt intta1cc1 ta1ccic1 ta1ccr1 com pare match taa1 48 0380h 00000380h nextpc interrupt intta2ov ta2ovic taa2 overflow taa2 49 0390h 00000390h nextpc interrupt intta2cc0 ta2cci c0 ta2ccr0 capture input/ compare match taa2 50 03a0h 000003a0h nextpc interrupt intta2cc1 ta2cci c1 ta2ccr1 capture input/ compare match taa2 51 03b0h 000003b0h nextpc interrupt intta3ov ta3ovic taa3 overfl ow taa3 52 03c0h 000003c0h nextpc interrupt intta3cc0 ta3ccic0 ta3ccr0 capture input note / compare match taa3 53 03d0h 000003d0h nextpc interrupt intta3cc1 ta3ccic1 ta3ccr1 capture input note / compare match taa3 54 03e0h 000003e0h nextpc interrupt intta4ov ta4ovic taa4 overfl ow taa4 55 03f0h 000003f0h nextpc interrupt intta4cc0 ta4cci c0 ta4ccr0 capture input/ compare match taa4 56 0400h 00000400h nextpc interrupt intta4cc1 ta4cci c1 ta4ccr1 capture input/ compare match taa4 57 0410h 00000410h nextpc interrupt intdma0 dmaic0 dma channel 0 tr ansfer end dma0 58 0420h 00000420h nextpc interrupt intdma1 dmaic1 dma channel 1 tr ansfer end dma1 59 0430h 00000430h nextpc interrupt intdma2 dmaic2 dma channel 2 tr ansfer end dma2 60 0440h 00000440h nextpc interrupt intdma3 dmaic3 dma channel 3 tr ansfer end dma3 61 0450h 00000450h nextpc interrupt intubtire ureic uartb reception error uartb 62 0460h 00000460h nextpc interrupt intubtir uric uartb reception end uart b 63 0470h 00000470h nextpc interrupt intubtit utic uartb transmission enable ua rtb 64 0480h 00000480h nextpc interrupt intubtif uific uartb fifo transmission end uartb 65 0490h 00000490h nextpc interrupt intubtito utoic uartb reception timeout uartb 66 04a0h 000004a0h nextpc interrupt intua0re ua0reic uarta0 recepti on error uarta0 67 04b0h 000004b0h nextpc interrupt intua0r ua0ric uarta0 recepti on end uarta0 68 04c0h 000004c0h nextpc interrupt intua0t ua0tic uarta0 transmissi on enable uarta0 69 04d0h 000004d0h nextpc interrupt intcb0re cb0reic csib0 recepti on error csib0 70 04e0h 000004e0h nextpc interrupt intcb0r cb0ric csib0 recepti on end csib0 71 04f0h 000004f0h nextpc interrupt intcb0t cb0tic csib0 transmissi on enable csib0 72 0500h 00000500h nextpc interrupt intua1re ua1reic uarta1 recept ion error uarta1 73 0510h 00000510h nextpc interrupt intua1r ua1ric uarta1 recept ion end uarta1 74 0520h 00000520h nextpc maskable interrupt intua1t ua1tic uarta1 transmi ssion enable uarta1 75 0530h 00000530h nextpc note v850e/ig3 only in the v850e/if3, compare match only
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 987 table 20-1. interrupt source list (4/4) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc interrupt intcb1re cb1reic csib1 recept ion error csib1 76 0540h 00000540h nextpc interrupt intcb1r cb1ric csib1 recept ion end csib1 77 0550h 00000550h nextpc interrupt intcb1t cb1tic csib1 transmissi on enable csib1 78 0560h 00000560h nextpc interrupt intua2re ua2reic uarta2 recept ion error uarta2 79 0570h 00000570h nextpc interrupt intua2r ua2ric uarta2 recept ion end uarta2 80 0580h 00000580h nextpc interrupt intua2t ua2tic uarta2 transmi ssion enable uarta2 81 0590h 00000590h nextpc interrupt intcb2re cb2reic csib2 recept ion error csib2 82 05a0h 000005a0h nextpc interrupt intcb2r cb2ric csib2 rec eption end csib2 83 05b0h 000005b0h nextpc interrupt intcb2t cb2tic csib2 transmi ssion enable csib2 84 05c0h 000005c0h nextpc interrupt intiic iicic iic serial transfer end iic 85 05d0h 000005d0h nextpc interrupt intad0 ad0ic adc0 conversion end adc0 86 05e0h 000005e0h nextpc interrupt intad1 ad1ic adc1 conver sion end adc1 87 05f0h 000005f0h nextpc interrupt intad2 ad2ic adc2 conver sion end adc2 88 0600h 00000600h nextpc interrupt inttm0eq0 tm0eqic0 tm0cmp0 com pare match tmm0 89 0610h 00000610h nextpc interrupt inttm1eq0 tm1eqic0 tm1cmp0 com pare match tmm1 90 0620h 00000620h nextpc interrupt inttm2eq0 tm2eqic0 tm2cmp0 com pare match tmm2 91 0630h 00000630h nextpc interrupt inttm3eq0 tm3eqic0 tm3cmp0 com pare match tmm3 92 0640h 00000640h nextpc interrupt intadt0 adt0ic adtrg0 pin valid edge input pin 93 0650h 00000650h nextpc maskable interrupt intadt1 adt1ic adtrg1 pin valid edge input pin 94 0660h 00000660h nextpc remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of t he program counter (pc) saved to eipc, fepc, or dbpc of cpu when interrupt servicing is started. no te, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being exec uted does not become the nextp c. (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished. in this case, the address of the aborted instruction is the restore pc.) ? load instructions (sld.b, sld. bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 988 20.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged unc onditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. the non-maskable interrupt signals of the v850e/if3 and v850e/ig3 are the non-maskable interrupt request signals generated by the overflow of the watchdog timer (intwdt). intwdt functions when the wdtm.wdm1 and wdtm.wdm0 bits are set to ?01?.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 989 20.2.1 operation if a non-maskable interrupt request signal (intwdt) is generated, the cpu performs t he following processing, and transfers control to the handler routine. (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes the exception code (0010h) to the higher halfword (fecc) of ecr. (4) sets the psw.np and psw.id bits (1) and clears the psw.ep bit (0). (5) loads the handler address (00000010h) of the non-maskable in terrupt routine to the pc, and transfers control. the following shows the non-mask able interrupt servicing. figure 20-1. non-maskable interrupt servicing intwdt input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 00000010h intc acknowledged cpu processing psw. np 1 0
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 990 figure 20-2. acknowledging non -maskable interrupt request (a) if a new intwdt request is generated while an intwdt service program is being executed main routine intwdt request intwdt request (psw.np bit = 1) intwdt request is held pending regardless of the value of the psw.np bit. pending intwdt request serviced (b) if a new intwdt request is generated twice while an intwdt service program is being executed main routine intwdt request intwdt request held pending because intwdt service program is being serviced only one intwdt request is acknowledged even though two or more nmi requests are generated intwdt request held pending because intwdt service program is being serviced
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 991 20.2.2 restore execution is restored from non-maskable interr upt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and f epsw because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. the following illustrates how the reti instruction is processed. figure 20-3. reti instruction processing caution when the ep and np bits are change d by the ldsr instruction during non-maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set ep back to 0 and np back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 992 20.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that indicates that non-maskabl e interrupt (intwdt) servici ng is in progress. the np flag is allocated to the psw. this flag is set when an intwdt interrupt request si gnal has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. the flag is cleared to 00000020h after reset. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt servicing in progress np 0 1 non-maskable interrupt (intwdt) servicing status after reset: 00000020h
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 993 20.3 maskable interrupts maskable interrupt request signals can be masked by inte rrupt control registers. the v850e/if3 and v850e/ig3 have 95 maskable interrupt sources. if two or more maskable interrupt request signals ar e generated at the same ti me, they are acknowledged according to the default priority. in addition to the default prio rity, eight levels of prioriti es can be specified by using the interrupt control registers (p rogrammable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt service routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt reques t signal in progress (specified by the interrupt control register). note t hat only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be serviced as multiple interrupts. to enable multiple interrupt servicing, however, save ei pc and eipsw to memory or registers before executing the ei instruction, and ex ecute the di instruction before the reti instruction to restor e the original values of eipc and eipsw. 20.3.1 operation if a maskable interrupt occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by interrupt controller (intc) and the maskable interrupt request signal generated while another interrupt is being serviced (while psw.np bit = 1 or id bit = 1) are held pending inside the intc. in this case, servicing a new maskable interrupt is started in accordance wit h the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or np and id bits are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 994 figure 20-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for details of the ispr register, see 20.3.6 in-service prio rity register (ispr) .
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 995 20.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. <1> loads the values of the pc and the psw from eipc and eipsw because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 20-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 20.3.6 in-service prio rity register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during non-maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set ep back to 0 and np back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 996 20.3.3 priorities of maskable interrupts the intc provides multiple interrupt servicing in wh ich an interrupt is acknowl edged while another interrupt is being serviced. multiple interrupts c an be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request signal type (default priority level) beforehand. for more information, see table 20-1 interrupt source list . programmable priority control customizes interrupt request signals into eight levels by the setting of the priority level specification flag. note that when an interrupt request signal is acknowledged, the psw.id flag is aut omatically set to 1. therefore, when multiple interrupts are to be used, cl ear the id flag to 0 beforehand (for exampl e, by placing the ei instruction in the interrupt servicing program) to set the interrupt enabled mode. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 997 figure 20-6. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even though interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even though interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 998 figure 20-6. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 999 figure 20-7. example of servicing interrupt request signals genera ted simultaneously default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are assumed names given to interrupt request signals for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1000 20.3.4 interrupt control registers (xxicn) an xxicn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 47h. cautions 1. disable interrupts (di) to read the xxicn.xxifn bit. if the xxifn bit is read while interrupts are enabled (ei), the correct value may not be r ead when acknowledging an interrupt and reading the bit conflict. 2. when manipulating the xxicn.xxmkn bit wh ile interrupt requests m ay occur (including the state in which interrupts are disabled (di)), be sure to use a bit manipulation instruction or use the imrm.xxmkn bit (m = 0 to 5).
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1001 xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff1cch <6> <7> note the flag xxlfn is reset automatically by the har dware if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 ) the addresses and bits of the interrupt control registers are as follows.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1002 table 20-2. addresses and bits of interrupt control registers (1/3) bit address register <7> <6> 5 4 3 2 1 0 fffff110h lvilic lvilif lvilmk 0 0 0 lvilpr2 lvilpr1 lvilpr0 fffff112h lvihic lvihif lvihmk 0 0 0 lvihpr2 lvihpr1 lvihpr0 fffff114h pic00 pif00 pmk00 0 0 0 ppr002 ppr001 ppr000 fffff116h pic01 pif01 pmk01 0 0 0 ppr012 ppr011 ppr010 fffff118h pic02 note pif02 pmk02 0 0 0 ppr022 ppr021 ppr020 fffff11ah pic03 note pif03 pmk03 0 0 0 ppr032 ppr031 ppr030 fffff11ch pic04 note pif04 pmk04 0 0 0 ppr042 ppr041 ppr040 fffff11eh pic05 note pif05 pmk05 0 0 0 ppr052 ppr051 ppr050 fffff120h pic06 note pif06 pmk06 0 0 0 ppr062 ppr061 ppr060 fffff122h pic07 note pif07 pmk07 0 0 0 ppr072 ppr071 ppr070 fffff124h pic08 pif08 pmk08 0 0 0 ppr082 ppr081 ppr080 fffff126h pic09 pif09 pmk09 0 0 0 ppr092 ppr091 ppr090 fffff128h pic10 pif10 pmk10 0 0 0 ppr102 ppr101 ppr100 fffff12ah pic11 pif11 pmk11 0 0 0 ppr112 ppr111 ppr110 fffff12ch pic12 pif12 pmk12 0 0 0 ppr122 ppr121 ppr120 fffff12eh pic13 pif13 pmk13 0 0 0 ppr132 ppr131 ppr130 fffff130h pic14 pif14 pmk14 0 0 0 ppr142 ppr141 ppr140 fffff132h pic15 pif15 pmk15 0 0 0 ppr152 ppr151 ppr150 fffff134h pic16 pif16 pmk16 0 0 0 ppr162 ppr161 ppr160 fffff136h pic17 pif17 pmk17 0 0 0 ppr172 ppr171 ppr170 fffff138h pic18 pif18 pmk18 0 0 0 ppr182 ppr181 ppr180 fffff13ah cmpic0l cmpif0l cmpmk 0l 0 0 0 cmppr0l2 cmppr0l1 cmppr0l0 fffff13ch cmpic0f cmpif0f cmpmk0f 0 0 0 cmppr0f2 cm ppr0f1 cmppr0f0 fffff13eh cmpic1l cmpif1l cmpmk 1l 0 0 0 cmppr1l2 cmppr1l1 cmppr1l0 fffff140h cmpic1f cmpif1f cmpmk1f 0 0 0 cmppr1f2 cm ppr1f1 cmppr1f0 fffff142h tb0ovic tb0ovif tb0ovmk 0 0 0 tb0ovpr2 tb0ovpr1 tb0ovpr0 fffff144h tb0ccic0 tb0ccif0 tb0ccmk0 0 0 0 tb0ccpr02 tb0ccpr01 tb0ccpr00 fffff146h tb0ccic1 tb0ccif1 tb0ccmk1 0 0 0 tb0ccpr12 tb0ccpr11 tb0ccpr10 fffff148h tb0ccic2 tb0ccif2 tb0ccmk2 0 0 0 tb0ccpr22 tb0ccpr21 tb0ccpr20 fffff14ah tb0ccic3 tb0ccif3 tb0ccmk3 0 0 0 tb0ccpr32 tb0ccpr31 tb0ccpr30 fffff14ch tb1ovic tb1ovif tb1ovmk 0 0 0 tb1ovpr2 tb1ovpr1 tb1ovpr0 fffff14eh tb1ccic0 tb1ccif0 tb1ccmk0 0 0 0 tb1ccpr02 tb1ccpr01 tb1ccpr00 fffff150h tb1ccic1 tb1ccif1 tb1ccmk1 0 0 0 tb1ccpr12 tb1ccpr11 tb1ccpr10 fffff152h tb1ccic2 tb1ccif2 tb1ccmk2 0 0 0 tb1ccpr22 tb1ccpr21 tb1ccpr20 fffff154h tb1ccic3 tb1ccif3 tb1ccmk3 0 0 0 tb1ccpr32 tb1ccpr31 tb1ccpr30 fffff156h tt0ovic tt0ovif tt0ovmk 0 0 0 tt0ovpr2 tt0ovpr1 tt0ovpr0 fffff158h tt0ccic0 tt0ccif0 tt0ccmk0 0 0 0 tt0ccpr02 tt0ccpr01 tt0ccpr00 fffff15ah tt0ccic1 tt0ccif1 tt0ccmk1 0 0 0 tt0ccpr12 tt0ccpr11 tt0ccpr10 fffff15ch tt0iecic note tt0iecif tt0iecmk 0 0 0 tt0ie cpr2 tt0iecpr1 tt0iecpr0 fffff15eh tt1ovic tt1ovif tt1ovmk 0 0 0 tt1ovpr2 tt1ovpr1 tt1ovpr0 fffff160h tt1ccic0 tt1ccif0 tt1ccmk0 0 0 0 tt1ccpr02 tt1ccpr01 tt1ccpr00 fffff162h tt1ccic1 tt1ccif1 tt1ccmk1 0 0 0 tt1ccpr12 tt1ccpr11 tt1ccpr10 note v850e/ig3 only
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1003 table 20-2. addresses and bits of interrupt control registers (2/3) bit address register <7> <6> 5 4 3 2 1 0 fffff164h tt1iecic tt1iecif tt1iecmk 0 0 0 tt1iecpr2 tt1iecpr1 tt1iecpr0 fffff166h ta0ovic ta0ovif ta0ovmk 0 0 0 ta0ovpr2 ta0ovpr1 ta0ovpr0 fffff168h ta0ccic0 ta0ccif0 ta0ccmk0 0 0 0 ta0ccpr02 ta0ccpr01 ta0ccpr00 fffff16ah ta0ccic1 ta0ccif1 ta0ccmk1 0 0 0 ta0ccpr12 ta0ccpr11 ta0ccpr10 fffff16ch ta1ovic ta1ovif ta1ovmk 0 0 0 ta1ovpr2 ta1ovpr1 ta1ovpr0 fffff16eh ta1ccic0 ta1ccif0 ta1ccmk0 0 0 0 ta1ccpr02 ta1ccpr01 ta1ccpr00 fffff170h ta1ccic1 ta1ccif1 ta1ccmk1 0 0 0 ta1ccpr12 ta1ccpr11 ta1ccpr10 fffff172h ta2ovic ta2ovif ta2ovmk 0 0 0 ta2ovpr2 ta2ovpr1 ta2ovpr0 fffff174h ta2ccic0 ta2ccif0 ta2ccmk0 0 0 0 ta2ccpr02 ta2ccpr01 ta2ccpr00 fffff176h ta2ccic1 ta2ccif1 ta2ccmk1 0 0 0 ta2ccpr12 ta2ccpr11 ta2ccpr10 fffff178h ta3ovic ta3ovif ta3ovmk 0 0 0 ta3ovpr2 ta3ovpr1 ta3ovpr0 fffff17ah ta3ccic0 ta3ccif0 ta3ccmk0 0 0 0 ta3ccpr02 ta3ccpr01 ta3ccpr00 fffff17ch ta3ccic1 ta3ccif1 ta3ccmk1 0 0 0 ta3ccpr12 ta3ccpr11 ta3ccpr10 fffff17eh ta4ovic ta4ovif ta4ovmk 0 0 0 ta4ovpr2 ta4ovpr1 ta4ovpr0 fffff180h ta4ccic0 ta4ccif0 ta4ccmk0 0 0 0 ta4ccpr02 ta4ccpr01 ta4ccpr00 fffff182h ta4ccic1 ta4ccif1 ta4ccmk1 0 0 0 ta4ccpr12 ta4ccpr11 ta4ccpr10 fffff184h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff186h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff188h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff18ah dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff18ch ureic ureif uremk 0 0 0 urepr2 urepr1 urepr0 fffff18eh uric urif urmk 0 0 0 urpr2 urpr1 urpr0 fffff190h utic utif utmk 0 0 0 utpr2 utpr1 utpr0 fffff192h uific uifif uifmk 0 0 0 uifpr2 uifpr1 uifpr0 fffff194h utoic utoif utomk 0 0 0 utopr2 utopr1 utopr0 fffff196h ua0reic ua0reif ua0remk 0 0 0 ua0repr2 ua0repr1 ua0repr0 fffff198h ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff19ah ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff19ch cb0reic cb0reif cb0remk 0 0 0 cb0repr2 cb0repr1 cb0repr0 fffff19eh cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff1a0h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff1a2h ua1reic ua1reif ua1remk 0 0 0 ua1repr2 ua1repr1 ua1repr0 fffff1a4h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff1a6h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff1a8h cb1reic cb1reif cb1remk 0 0 0 cb1repr2 cb1repr1 cb1repr0 fffff1aah cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff1ach cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff1aeh ua2reic ua2reif ua2remk 0 0 0 ua2repr2 ua2repr1 ua2repr0 fffff1b0h ua2ric ua2rif ua2rmk 0 0 0 ua2rpr2 ua2rpr1 ua2rpr0 fffff1b2h ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff1b4h cb2reic cb2reif cb2remk 0 0 0 cb2repr2 cb2repr1 cb2repr0 fffff1b6h cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff1b8h cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1004 table 20-2. addresses and bits of interrupt control registers (3/3) bit address register <7> <6> 5 4 3 2 1 0 fffff1bah iicic iicif iicmk 0 0 0 iicpr2 iicpr1 iicpr0 fffff1bch ad0ic ad0if ad0mk 0 0 0 ad0pr2 ad0pr1 ad0pr0 fffff1beh ad1ic ad1if ad1mk 0 0 0 ad1pr2 ad1pr1 ad1pr0 fffff1c0h ad2ic ad2if ad2mk 0 0 0 ad2pr2 ad2pr1 ad2pr0 fffff1c2h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff1c4h tm1eqic0 tm1eqif0 tm1eqmk0 0 0 0 tm1eqpr02 tm1eqpr01 tm1eqpr00 fffff1c6h tm2eqic0 tm2eqif0 tm2eqmk0 0 0 0 tm2eqpr02 tm2eqpr01 tm2eqpr00 fffff1c8h tm3eqic0 tm3eqif0 tm3eqmk0 0 0 0 tm3eqpr02 tm3eqpr01 tm3eqpr00 fffff1cah adt0ic adt0if adt0mk 0 0 0 adt0pr2 adt0pr1 adt0pr0 fffff1cch adt1ic adt1if adt1mk 0 0 0 adt1pr2 adt1pr1 adt1pr0
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1005 20.3.5 interrupt mask register s 0 to 5 (imr0 to imr5) the imr0 to imr5 registers set the interrupt mask st ate for the maskable interrupt s. the imr0.xxmkn to imr3.xxmkn bits are equivalent to the xxicn.xxmkn bit. the imrm register can be read or wr itten in 16-bit units (m = 0 to 5). if the higher 8 bits of the imrm regi ster are used as the im rmh register and the lowe r 8 bits as the imrml register, these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to ffffh. caution the device file defines the xxicn.xxmkn bit as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of th e xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten).
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1006 (1/2) after reset: ffffh r/w address: after reset: ffffh r/w address: ta1ccmk0 tt1ovmk imr2 (imr2h note 1 ) ta0ccmk1 tt0ccmk1 ta1ovmk tt0iecmk note 2 ta0ccmk0 tt0ccmk0 ta0ovmk tt0ovmk tt1iecmk tb1ccmk3 tt1ccmk1 tb1ccmk2 tt1ccmk0 tb1ccmk1 urmk ta4ovmk imr3 (imr3h note 1 ) (imr3l) (imr2l) uremk ta3ccmk1 dmamk3 ta3ccmk0 dmamk2 ta3ovmk dmamk1 ta2ccmk1 dmamk0 ta2ccmk0 ta4ccmk1 ta2ovmk ta4ccmk0 ta1ccmk1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr3 fffff106h imr3l fffff106h, imr3h fffff107h imr2 fffff104h imr2l fffff104h, imr2h fffff105h after reset: ffffh r/w address: ua2remk cb0rmk imr4 (imr4h note 1 ) (imr4l) cb1tmk cb0remk cb1rmk ua0tmk cb1remk ua0rmk ua1tmk ua0remk ua1rmk utomk ua1remk uifmk cb0tmk utmk 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr4 fffff108h imr4l fffff108h, imr4h fffff109h after reset: ffffh r/w address: 1 ad1mk imr5 (imr5h note 1 ) (imr5l) adt1mk ad0mk adt0mk iicmk tm3eqmk0 cb2tmk tm2eqmk0 cb2rmk tm1eqmk0 cb2remk tm0eqmk0 ua2tmk ad2mk ua2rmk 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr5 fffff10ah imr5l fffff10ah, imr5h fffff10bh tb1ccmk0 cmpmk1l tb1ovmk cmpmk0f tb0ccmk3 cmpmk0l tb0ccmk2 pmk18 tb0ccmk1 pmk17 tb0ccmk0 pmk16 tb0ovmk pmk15 cmpmk1f pmk14 after reset: ffffh r/w address: imr1 (imr1h note 1 ) (imr1l) 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr1 fffff102h imr1l fffff102h, imr1h fffff103h imr0 (imr0h note 1 ) (imr0l) pmk13 pmk05 note 2 pmk12 pmk04 note 2 pmk11 pmk03 note 2 pmk10 pmk02 note 2 pmk09 pmk01 pmk08 pmk00 pmk07 note 2 lvihmk pmk06 note 2 lvilmk after reset: ffffh r/w address: 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr0 fffff100h imr0l fffff100h, imr0h fffff101h notes 1. when reading/writing bits 15 to 8 of the imr0 to im r5 registers in 8-bit or 1-bit units, specify these bits as bits 7 to 0 of the imr0h to imr5h registers. 2. these bits are valid only in the v850e/ig3. be sure to set these bits to 1 in the v850e/if3. caution set bit 15 of the imr5 register (bit 7 of im r5h register) to 1. the operation when these settings are changed is not guaranteed.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1007 (2/2) xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled interrupt mask flag setting remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1008 20.3.6 in-service priori ty register (ispr) the ispr register holds the priority level of the maskable interrupt curr ently acknowledged. when an interrupt request signal is acknowledged, the bit of th is register corresponding to the priority level of that interrupt signal request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is execut ed, the bit corresponding to the inte rrupt request signal having the highest priority is automatically cleared to 0 by hardware. however, it is not cleared to 0 when exec ution is returned from non- maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. caution in the interrupt enabled (ei) state, if an interrupt is acknowle dged during the reading of the ispr register, the value of the ispr register may be read after the bit is set (1) by this interrupt acknowledgment. to read the value of the ispr register properly before interrupt acknowledgment, read it in the interrupt disabled (di) state. ispr7 interrupt request signal with priority n is not acknowledged interrupt request signal with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n: 0 to 7 (priority level)
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1009 20.3.7 maskable interrupt status flag (id) the id flag controls the maskable in terrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. t he id flag is allocated to the psw. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled (pending) id 0 1 maskable interrupt servicing specification note after rest: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by t he ei instruction. its val ue is also modified by the reti instruction or ldsr inst ruction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, t he id flag is automatically set (1) by hardware. an interrupt request signal generated during the a cknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is se t (1), and the id flag is cleared (0).
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1010 20.4 external interrupt request input pins (intp00 to intp18, intadt0, intadt1) 20.4.1 noise elimination (1) noise elimination of intp00, intp01, intpa (v850e/ig3 only), intp08 to intp13, intp17, intp18, intadt0, and intadt1 pins the intp00, intp01, intpa (v850e/ig3 only), intp08 to intp13, intp17, intp18, intadt0, and intadt1 pins incorporate a noise eliminator t hat uses analog filter (a = 02 to 07). unless, therefore, the input level of each pin is held for a certain time, an edge cannot be detec ted. an edge is detected after a certain time has elapsed. (2) noise elimination of intp14 to intp16 pins the intp14 to intp16 pins incorporate a digital noise eliminator. the sampling clock that performs digital sampli ng can be selected by the intnfcm.intnfcm2 to intnfcm.intnfcm0 bits (m = 14 to 16). the system clock stops in the idle and stop modes, so the intp14 to intp16 pins cannot be used to cancel the idle and stop modes. 20.4.2 edge detection the valid edges of the intn pin can be selected by program (v850e/if3: n = p 00, p01, p08 to p18, adt0, adt1, v850e/ig3: n = p00 to p18, adt0, adt1). the edge that can be selected as the valid edge is one of the following. ? rising edge ? falling edge ? both the rising and falling edges the edge-detected intn signal bec omes an interrupt source. the valid edge is specified by the intr0 to in tr2, adtr, intf0 to in tf2, and adtf registers.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1011 (1) external interrupt rising edge specification register 0 (intr0), external interrupt falling edge specification register 0 (intf0) the intr0 and intf0 registers are used to specify the trigger mode of the intp00, intp01, and intpa (v850e/ig3 only) pins and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges) (a = 02 to 07). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the exter nal interrupt function (alt ernate function) to the port mode, an edge may be detect ed. therefore, be sure to cl ear the intf0n and intr0n bits to 00, and then set the port mode (v850e/if3: n = 0, 1, v850e/ig3: n = 0 to 7). <7> intf07 note intf0 <6> intf06 note <5> intf05 note <4> intf04 note <3> intf03 note <2> intf02 note <1> intf01 <0> intf00 after reset: 00h r/w address: fffffc00h <7> intr07 note intr0 <6> intr06 note <5> intr05 note <4> intr04 note <3> intr03 note <2> intr02 note <1> intr01 <0> intr00 after reset: 00h r/w address: fffffc20h note valid only in the v850e/ig3. in the v850e/if3, be sure to set these bits to 0. remark for the valid edge specification, see table 20-3 . table 20-3. valid edge specification of intp00 to intp07 pins intf0n intr0n valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using these pins as the intp0n pins, be sure to set the intf0 n and intr0n bits to 00. remark v850e/if3: n = 0, 1 v850e/ig3: n = 0 to 7
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1012 (2) external interrupt rising edge specification register 1 (intr1), external interrupt falling edge specification register 1 (intf1) the intr1 and intf1 registers are used to specify t he trigger mode of the intp08 to intp13, intp17, and intp18 pins and can specify the va lid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the exter nal interrupt function (alt ernate function) to the port mode, an edge may be detect ed. therefore, be sure to cl ear the intfn and intrn bits to 00, and then set the port mode (n = 08 to 13, 17, 18). <7> intf18 intf1 <6> intf17 <5> intf13 <4> intf12 <3> intf11 <2> intf10 <1> intf09 <0> intf08 after reset: 00h r/w address: fffffc02h <7> intr18 intr1 <6> intr17 <5> intr13 <4> intr12 <3> intr11 <2> intr10 <1> intr09 <0> intr08 after reset: 00h r/w address: fffffc22h remark for the valid edge specification, see table 20-4 . table 20-4. valid edge specification of intp08 to intp13, intp17, and intp18 pins intfn intrn valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using these pins as the intpn pins , be sure to set the intfn and intrn bits to 00. remark n = 08 to 13, 17, 18
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1013 (3) external interrupt rising edge specification register 2 (intr2), external interrupt falling edge specification register 2 (intf2) the intr2 and intf2 registers are used to specify t he trigger mode of the intp14 to intp16 pins and can specify the valid edge independently for each pin (risi ng edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the exter nal interrupt function (alt ernate function) to the port mode, an edge may be detect ed. therefore, be sure to cl ear the intf1n and intr1n bits to 00, and then set the port mode (n = 4 to 6). 7 0 intf2 6 0 5 0 4 0 3 0 <2> intf16 <1> intf15 <0> intf14 after reset: 00h r/w address: fffffc04h 7 0 intr2 6 0 5 0 4 0 3 0 <2> intr16 <1> intr15 <0> intr14 after reset: 00h r/w address: fffffc24h remark for the valid edge specification, see table 20-5 . table 20-5. valid edge specification of intp14 to intp16 pins intf1n intr1n valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using these pins as the intp1n pins, be sure to set the intf1 n and intr1n bits to 00. remark n = 4 to 6
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1014 (4) a/d trigger rising edge , falling edge specification registers (adtr, adtf) the adtr and adtf registers are registers that s pecify the trigger mode of the adtrg0/intadt0 and adtrg1/intadt1 pins and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is change d from the external trigger input of the a/d converter n (alternate function)/external interrupt func tion (alternate function) to th e port mode, an edge may be detected. therefore, be sure to set the adtfn and adtrn bits to 00, and then set the port mode. 0 adtf 0 0 0 0 0 adtf1 adtf0 after reset: 00h r/w address: fffff2f0h 0 adtr 0 0 0 0 0 adtr1 adtr0 after reset: 00h r/w address: fffff2f2h remark for the valid edge specification, see table 20-6 . table 20-6. valid edge specification of adtrg0/intadt0 and adtrg1/intadt1 pins adtfn adtrn valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using these pins as the adtrgn/in tadtn pins, be sure to set the adtfn and adtrn bits to 00. remark n = 0, 1
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1015 20.5 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can always be acknowledged. 20.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits (1). <5> sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. the processing of a software exception is shown below. figure 20-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1016 20.5.2 restore execution is restored from software excepti on processing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 20-9. reti instruction processing caution when the psw.ep and psw.np bits are ch anged by the ldsr instruction during software exception processing, in order to restore the pc and psw correct ly during restoring by the reti instruction, it is necessary to set the ep bit back to 1 and cl ear the np bit to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1017 20.5.3 exception status flag (ep) the ep flag is a status flag used to indi cate that exception processing is in progress. this flag is set when an exception occurs. the ep flag is allocated to the psw. this flag is set to 00000020h after reset. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h 20.6 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instructi on takes place. in the v850e/if3 and v850e/ig3, an illegal opcode trap (ilgop: illegal opcode trap) is considered as an exception trap. 20.6.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible that th is instruction may be assigned to an illegal opcode in th e future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits (1). <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. the processing of the exception trap is shown below.
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1018 figure 20-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from an except ion trap by the dbret instruction. when the dbret instruction is executed, the cpu performs the followi ng processing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address of the restored pc and psw. caution dbpc and dbpsw can be accessed only dur ing the period between when the illegal opcode is executed and when the dbret instruction is executed. the restore processing from an exception trap is shown below. figure 20-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1019 20.6.2 debug trap the debug trap is an exception that can be acknowledged anytime and is gener ated by execution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep and psw.id bits (1). <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. the processing of the debug trap is shown below. figure 20-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1020 (2) restore execution is restored from a debug trap by the dbret in struction. when the dbret instruction is executed, the cpu performs the following processing and transfe rs control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address of the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the period between when the dbtrap is executed and when the dbret instruction is executed. the restore processing from a debug trap is shown below. figure 20-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1021 20.7 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request signal with a higher pr iority level, and the higher priority interrupt request signal is acknowledged and serviced first. if there is an interrupt request signal with a lower priority level than the interrupt r equest currently being serviced, that interrupt request signal is held pending. multiple interrupt servicing control of maskable interrupts is executed when interrupts are enabled (psw.id bit = 0). thus, to execute multiple interrupts, it is necessary to set the interrupt enabled state (psw.id bit = 0) even in an interrupt servicing routine. if maskable interrupts are enabled or a software excepti on is generated in a maskable interrupt or software exception servicing program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgment of maskable inte rrupt signals in servicing program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (interr upt acknowledgment enabled) ... ... maskable interrupt acknowledgment ... ... ? di instruction (interr upt acknowledgment disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1022 (2) generation of exception in servicing program servicing program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interrupt servicing cont rol has 8 levels, from 0 to 7 for each maskable interrupt request signal (0 is the highest priority), but it can be set as desired via software. the priority order is set using the xxprn0 to xxprn2 bits of the interrupt control request register (xxlcn), provided for each maskable interrupt request signal. after system reset, an interr upt request signal is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request signal is acknowledged after the current interrupt servicing has been completed and the reti instructi on has been executed. caution in a non-maskable interrupt servicing routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1023 20.8 interrupt response time of cpu except the following cases, the interrupt response time of the cpu is 4 clocks minimum. to input interrupt request signals successively, input the next interrupt request si gnal at least 4 clocks after the preceding interrupt. ? in idle/stop mode ? when interrupt request non-sampling inst ructions are successively executed (see 20.9 periods in which cpu does not acknowledge interrupts .) ? when an on-chip peripheral i/o register is accessed figure 20-14. pipeline operation at inte rrupt request acknowledgment (outline) if if id ex df wb ifx ifx idx 4 system clocks if if if id int1 int2 int3 int4 internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt servicing routine) interrupt request interleave access note note for interleave accesses, refer to 8.1.2 2-clock branch in v850e1 architecture user?s manual (u14559e) . remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt latency time (internal system clock) external interrupt internal interrupt intp00, intp01, intpa note 1 , intp08 to intp13, intp17, intp18, intadt0, intadt1 intp14 to intp16 conditions minimum 4 4 + analog filter time 4 + note 3 + digital noise filter maximum 7 note 2 7 + analog filter time 7 + note 3 + digital noise filter the following cases are exceptions. ? in idle/stop mode ? access to external bus ? two or more interrupt request non-sample instructions are executed in succession ? access to on-chip peripheral i/o register notes 1. v850e/ig3 only 2. when ld instruction is executed to internal rom (during align access) 3. for the number of internal system clocks, see 4.6 (1) digital noise elimination 0 control register n (intnfcn) . remark a = 02 to 07
chapter 20 interrupt/exception processing function user?s manual u18279ej3v0ud 1024 20.9 periods in which cpu does not acknowledge interrupts the cpu acknowledges an interrupt wh ile an instruction is being execut ed. however, no interrupt will be acknowledged between an interrupt request non- sample instruction and the next instru ction (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? store instruction for t he command register (prcmd). ? store instructions or bit manipulat ion instructions excluding tst1 inst ruction for the following registers. ? interrupt-related registers: interrupt control register (xxicn) and interr upt mask registers 0 to 5 (imr0 to imr5) ? power save control register (psc) remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 ) 20.10 caution note that if a port is set to external interrupt input (i ntpn), the timer/counter-relat ed interrupt, serial interface- related interrupt, and a/d converter-related interrupt, which are alternate functions, do not occur (v850e/if3: n = 00, 01, 08 to 18, adt0, adt1, v850e/ig3 : n = 00 to 18, adt0, adt1).
user?s manual u18279ej3v0ud 1025 chapter 21 standby function 21.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 21-1. table 21-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuit except the oscillator, pll, csib in the slave mode, clock monitor, low-voltage detector (lvi), power-on-clear circuit (poc) stop mode mode to stop all the operations of the internal circuit except the csib in the slave mode, low-voltage detector (lvi), power-on-clear circuit (poc)
chapter 21 standby function user?s manual u18279ej3v0ud 1026 figure 21-1. status transition normal operation mode wait for stabilization of (oscillation) and pll wait for stabilization of oscillation and pll note 6 note 6 note 6 note 7 setting of halt mode setting of stop mode idle mode halt mode stop mode system reset note 4 system reset note 4 interrupt request note 1 interrupt request note 5 system reset note 2 wait for stabilization of (oscillation) and pll setting of idle mode interrupt request note 3 notes 1. non-maskable interrupt request signal (intwd t) or unmasked maskable interrupt request signal 2. reset pin input, reset signal (wdtres) generation by watchdog timer overflow, reset signal (lvires) generation by low-voltage detector (lvi ), or reset signal (pocres) generation by power- on-clear circuit (poc) 3. unmasked external interrupt request signal (intp00, intp01, intp02 to intp07 (v850e/ig3 only), intp08 to intp13, intp17, intp18, intadt0, or in tadt1) or unmasked internal interrupt request signal from (csib-related interrupt request signal in the slave mode) peripheral functions operable in stop mode 4. reset pin input, reset signal (lvi res) generation by low-voltage detector (lvi), or reset signal (pocres) generation by power-on-clear circuit (poc) 5. unmasked external interrupt r equest signal (intp00, intp01, intp02 to intp07 (v850e/ig3 only), intp08 to intp13, intp17, intp18, intadt0, or in tadt1) or unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode) from peripheral functions operable in idle mode 6. oscillation stabilization time count by o scillation stabilization time wait control (ost) the oscillation stabilization time is necessary after release of reset because the pll is initialized by a reset. the stabilization time is the time determined by default. 7. oscillation stabilization time count by o scillation stabilization time wait control (ost) the stabilization time is determined by the setting of the osts register.
chapter 21 standby function user?s manual u18279ej3v0ud 1027 21.2 control registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby function. the stb bit of this register is used to specify the standby mode. this re gister is a special register (see 3.4.8 special registers ). this register can be written only by a combinat ion of specific sequences. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc 0 0 intm 0 0 stb 0 standby mode release by intxx request enabled standby mode release by intxx request disabled intm 0 1 standby mode control note 2 by maskable interrupt request (intxx note 1 ) normal mode standby mode stb 0 1 sets operation mode after reset: 00h r/w address: fffff1feh < > < > notes 1. for details, see table 20-1 interrupt source list . 2. the setting is valid only in the idle mode and stop mode. cautions 1. be sure to set bits 0, 2, 3, and 5 to 7 to ?0?. 2. before setting a standby mode by setting the st b bit to 1, be sure to set the pcc register to 03h and then set the stb bit to 1. othe rwise, the standby mode may not be set or released. after releasing the standby mode, ch ange the value of the pcc register to the desired value. 3. to set the idle mode or stop mode, set the pcc register to 03h, and the psmr.psm0 bit in that order and then set the stb bit to 1.
chapter 21 standby function user?s manual u18279ej3v0ud 1028 (2) power save mode register (psmr) the psmr register is an 8-bit register that contro ls the operation in the software standby mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle mode stop mode psm0 0 1 operation in software standby mode specification psmr 0 0 0 0 0 0 psm0 after reset: 00h r/w address: fffff820h < > cautions 1. be sure to set bits 1 to 7 to ?0?. 2. the psm0 bit is valid only when the psc.stb bit is 1.
chapter 21 standby function user?s manual u18279ej3v0ud 1029 21.3 halt mode 21.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. when halt mode is set, clock supply is stopped to the cpu only. the clock generator and pll continue operating. clock supply to the other on- chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 21-3 shows the operation status in the halt mode. the average power consumpti on of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an interrupt request is being held pending, the halt mode is set but is released immediat ely by the pending interrupt request. 21.3.2 releasing halt mode the halt mode is released by a non-maskable inte rrupt request signal (intwdt), an unmasked maskable interrupt request signal, and a reset signal (reset pin input, reset signal (wdtres) generation by watchdog timer overflow, reset signal (lvires) generation by low-voltage detector (lvi), or reset signal (pocres) generation by power-on-clear circuit (poc)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal (intwdt) or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt r equest that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than or same as the interrupt currently being serviced is generated, the halt mode is re leased, but the newly generated interrupt request signal is not acknowledged. the interrupt request signal itself is retained. theref ore, execution starts at the next instruction after the halt instruction. (b) if an interrupt request signal with a priority higher than that of the interrupt currently being serviced is issued (including a non-maskable interrupt request signa l), the halt mode is released and that interrupt request signal is acknowledged. therefore, execution branches to the handler address. table 21-2. operation after releasing ha lt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address unmasked maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed
chapter 21 standby function user?s manual u18279ej3v0ud 1030 (2) releasing halt mode by reset pin input or by wd tres, lvires, or pocres signal generation the same operation as the normal reset operation is performed. table 21-3. operation status in halt mode setting of halt mode item operation status clock generator, pll operates system clock (f xx ) supply cpu stops operation external bus interface note see table 2-2 pin operation status in operation modes . dma operable interrupt controller operable taa0 to taa4 operable tab0, tab1 operable tmt0, tmt1 operable timer tmm0 to tmm3 operable watchdog timer operable csib0 to csib2 operable uarta0 to uarta2 operable uartb operable serial interface i 2 c operable a/d converters 0 to 2 operable clock monitor operable low-voltage detector operable power-on-clear circuit operable port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 21 standby function user?s manual u18279ej3v0ud 1031 21.4 idle mode 21.4.1 setting and operation status the idle mode is set by clearing (0) the psmr.psm0 bit and setting (1) the psc.stb bit in the normal operation mode. in the idle mode, the clock generator and pll continue ope ration but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on- chip peripheral functions that can operate with an exter nal clock continue operating. table 21-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the clock generator and pll do not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. 21.4.2 releasing idle mode the idle mode is released by an unmasked external inte rrupt request signal (intp00, intp01, intp02 to intp07 (v850e/ig3 only), intp08 to intp13, intp17, intp18, inta dt0, or intadt1 pin input ), an unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode) from the peripheral functions operable in the idle mode, or a reset signal (reset pi n input, reset signal (lvires) generation by low-voltage detector (lvi), or reset signal (pocres) generation by power-on-clear circuit (poc)). after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by unmasked maskable interrupt request signal the idle mode is released by an unmasked maskable inte rrupt request signal, regardless of the priority of the interrupt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. caution when psc.intm bit = 1, the idle mode cannot be released by the unmasked maskable interrupt request signal. (a) if an interrupt request with a priority lower than or same as the interrupt request signal currently being serviced is generated, the idle mode is released, but the newly generated interrupt is not acknowledged. the interrupt request signal itself is retained. therefore, execution star ts at the next instruction after the idle instruction. (b) if an interrupt request signal with a priority higher th an that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. ther efore, execution branche s to the handler address.
chapter 21 standby function user?s manual u18279ej3v0ud 1032 table 21-4. operation after releasing id le mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status unmasked maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing idle m ode by reset pin input or by lvires or pocres signal generation the same operation as the normal reset operation is performed. table 21-5. operation status in idle mode setting of idle mode item operation status clock generator, pll operates system clock (f xx ) stops supply cpu stops operation external bus interface note see table 2-2 pin operation status in operation modes . dma stops operation interrupt controller stops operation taa0 to taa4 stops operation tab0, tab1 stops operation tmt0, tmt1 stops operation timer tmm0 to tmm3 stops operation watchdog timer stops operation csib0 to csib2 operable when sckbn input clock is selected as count clock (in slave mode) (n = 0 to 2) uarta0 to uarta2 stops operation uartb stops operation serial interface i 2 c stops operation a/d converters 0 to 2 stops operation clock monitor operable low-voltage detector operable power-on-clear circuit operable port function retains status before idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 21 standby function user?s manual u18279ej3v0ud 1033 21.5 stop mode 21.5.1 setting and operation status the stop mode is set by setting (1) the psmr.psm0 bit and setting (1) the psc.stb bit in the normal operation mode. in the stop mode, the clock generator stops operation. clock supply to the cpu and the on-chip peripheral functions is stopped. as a result, program execution is st opped, and the contents of the inter nal ram before the stop mode was set are retained. the cpu and other on-chip peripheral functi ons stop operating. however, the on-chip peripheral functions that can operate with an ex ternal clock continue operating. table 21-7 shows the operation status in the stop mode. because the stop stops operation of the clock generator, it reduces the power consumption to a level lower than the idle mode. when the external clock is not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the stop mode. 21.5.2 releasing stop mode the stop mode is released by an unmasked external interrupt request signal (intp00, intp01, intp02 to intp07 (v850e/ig3 only), intp08 to intp13, intp17, in tp18, intadt0, or intadt1 pin input), an unmasked internal interrupt request signal (csib-related interrupt signal in the slave mode) from the peripheral functions operable in the stop mode, or a reset signal (reset pin in put, reset signal (lvires) generation by low-voltage detector (lvi), or reset signal (pocres) generation by power-on-clear circuit (poc)). after the stop mode has been released, the normal operation mode is restor ed after the oscillation stabilization time has been secured. (1) releasing stop mode by unmasked maskable interrupt request signal the stop mode is released by an unmasked maskable inte rrupt request signal, regardless of the priority of the interrupt request. if the stop mode is set in an inte rrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. caution when psc.intm bit = 1, the stop mode cannot be released by the unmasked maskable interrupt request signal. (a) if an interrupt request with a priority lower than or same as the interrupt request currently being serviced is generated, the stop mode is releas ed, but the newly generated interru pt is not acknowledged. the interrupt request itself is retained. therefore, execution starts at the next instruction after the stop instruction. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued, the stop mode is released and that interr upt request is acknowledged. therefore, execution branches to the handler address.
chapter 21 standby function user?s manual u18279ej3v0ud 1034 table 21-6. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status unmasked maskable interrupt request execution branches to the handler address or the next instruction is executed after securing oscillation stabilization time the next instruction is executed after securing oscillation stabilization time (2) releasing stop mode by reset pin input or by lvires or pocres signal generation the same operation as the normal reset operation is performed. table 21-7. operation status in stop mode setting of stop mode item operation status clock generator, pll stops operation system clock (f xx ) stops supply cpu stops operation external bus interface note see table 2-2 pin operation status in operation modes . dma stops operation interrupt controller stops operation taa0 to taa4 stops operation tab0, tab1 stops operation tmt0, tmt1 stops operation timer tmm0 to tmm3 stops operation watchdog timer stops operation csib0 to csib2 operable when sckbn input clock is selected as count clock (in slave mode) (n = 0 to 2) uarta0 to uarta2 stops operation uartb stops operation serial interface i 2 c stops operation a/d converters 0 to 2 stops operation clock monitor stops operation low-voltage detector operable power-on-clear circuit operable port function retains status before stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 21 standby function user?s manual u18279ej3v0ud 1035 21.6 securing oscillation stabilization time when the stop mode is released, the oscillation stabilization time set by the osts register elapses. the oscillation stabilization time is the reset value of the osts register, 2 14 /f x (2.048 ms at f x = 8 mhz), if the stop mode is released by reset pin input. however, the actual oscillation stabilizati on time is half this value (after reset: 2 13 /f x (1.024 ms at f x = 8 mhz), and the other half is the stabilization time of the pll. set an oscillation stabilization time d ouble that of the oscillation stabilization time of the oscillator us ed when the stop mode is released. in addition, when releasing the mode by reset pin input, be sure to secure the os cillation stabilizati on time by outputting the reset signal at low level for the time longer than the oscillation stabilization time of the used resonator minus the fixed oscillation stabilization time. the timer for counting the oscillation stabilization time secures oscillation stabilization time equal to the overflow time of the watchdog timer. the operation performed when the stop mode is releas ed by an interrupt request signal is shown below. figure 21-2. oscillation stabilization time oscillated waveform clock generator stops oscillation stabilization time count f clk stop mode status interrupt request caution for details of the osts register, see 5.3 (5 ) oscillation stabilization time select register (osts).
user?s manual u18279ej3v0ud 1036 chapter 22 reset functions 22.1 overview ? system reset by reset pin input ? system reset signal (wdtres) generation by watchdog timer (wdt) overflow ? system reset signal (lvires) generat ion by low-voltage detector (lvi) ? system reset signal (pocres) generation by power-on-clear circuit (poc) ? forced reset by on-chip debug function (dcu) and reset mask function (see chapter 26 on-chip debug function .) 22.2 control register (1) reset source flag register (resf) the resf register is an 8-bit register that indicate s occurrence of a reset request from the watchdog timer (wdt) or low-voltage detector (lvi). the wdtrf or lvirf bit of this register is set to 1 when the internal reset source signal from wdt or lvi is asserted. the wdtrf or lvirf bit is cleared by a re set signal (the one generated by inputting the reset pin, the pocres signal generated by the power-on-clear circui t (poc), or the forced reset signal generated by the on-chip debug function), a bit manipulation instruction, or a store instruction (writing 0 to the wdtrf or lvirf bit). the resf register is a special register and can be wr itten only in a combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. however, bits 0 and 4 can only be cleared (0) by writing. this register is set to 00h by reset pin input, a reset by the power-on-clear circuit (poc), or a forced reset by the on-chip debug function. the reset value differs if th e source of reset is other than those sources. for details on reset conflict, see cautions on the next page.
chapter 22 reset functions user?s manual u18279ej3v0ud 1037 0 wdtrf 0 1 read: no reset request, write: clear reset request occurrence of reset signal from watchdog timer (wdt) resf 0 0 wdtrf 0 0 0 livrf livrf 0 1 read: no reset request, write: clear reset request occurrence of reset signal from low-voltage detector (lvi) after reset: 00h note r/w address: fffff888h note after a reset by reset pin input or the power-on-cl ear circuit (poc), or after a forced reset by the on- chip debug function: 00h after a reset due to a watchdog timer overflow: 10h after a reset by the low-voltage detector (lvi): 01h cautions 1. if setting (occurrence of reset of set source) and clearing (occurrence of system reset or writing 0 to the wdtrf or lvirf bit) of the resf register conflict, the priorities are as follows. <1> a reset by reset pin input or the power-on- clear circuit (poc), or a forced reset by the on-chip debug function (th at clears the resf register) <2> a reset by wdt or lvi (that sets the resf register) <3> writing 0 to the wdtrf or lvirf bit by a bit manipulation or store instruction (that clears the resf register) 2. even if reset masking was specified when a flag setting sour ce occurred, the flag is set. (reset masking does not affect setting the flag.)
chapter 22 reset functions user?s manual u18279ej3v0ud 1038 22.3 operation (1) reset operation by reset pin input when a low level is input to the reset pin, the v8 50e/if3 and v850e/ig3 are reset, and each hardware unit is initialized to a specific status. the oscillator continues oscillation even while a low leve l is input to the reset pin but the oscillation mode is initialized to the clock-through mode (pllc tl register = 01h) and the cpu clock (f cpu ) division to f xx /8 (pcc register = 03h). the reset status is released when t he reset pin input goes from low to high. after the reset status is released, the oscillation stabilization time of the osci llator and lockup time of pll (default value of osts register for the total time: 2 14 /f x (2.05 ms (f x = 8 mhz)) elapse, and then the cpu starts program execution. after release of reset, therefore, the operation is started in the clock-through mode and at f xx /8. the status of each hardware unit during the reset period and after the reset status is released is shown below. hardware during reset period after reset is released clock generator: oscillator (f x ) internal system clock (f clk ) cpu clock (f cpu ) external bus clock (f bus ) note oscillation/supply continues however, the cpu clock (f cpu ) is initialized to f xx /8. clock generator: peripheral clock (f xx to f xx /4096) oscillation/supply stops oscillation/supply starts after securing of oscillation stabilization time clock generator: watchdog timer clock (f xx /1024) oscillation/supply stops oscillation/supply starts cpu initialized program execution starts after securing of oscillation stabilization time internal ram retains value imm ediately before reset input only in the stop mode during reset input. otherwise, undefined. ports (including alternate- function pins) high impedance on-chip peripheral i/o registers (other than ports) initialized to specific status on-chip peripheral functions other than above stops operation can start operation note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 22 reset functions user?s manual u18279ej3v0ud 1039 the reset operation by reset pin input is illustrated below. figure 22-1. reset operation by reset pin input f x operation at f xx operation at f x /8 oscillation stabilization time + pll lockup time reset (input) f xx f cpu analog delay (eliminated as noise) analog delay analog delay analog delay (eliminated as noise) caution after release of reset, make sure that the oscillation stabilization time (1.024 ms (at f x = 8 mhz)) and pll lockup time (1.024 ms (at f x = 8 mhz)) elapse. if an oscillation stabilization time of 1.024 ms is not sufficient to secure stable oscillation, keep the reset pin low for the deficient time. remark the relationship between f xx and f x in the above timing chart is f xx = 8 f x . the operation after release of reset is the same in both the pll mode and clock-through mode and is started in the clock-through mode. set the pll mode by software control (setting pllctl.selpll bit to 1). to improve noise immunity, it is recommended to set the pll mode and then speed up the cpu clock (example: pcc register = 00h (f xx operation)).
chapter 22 reset functions user?s manual u18279ej3v0ud 1040 (2) reset operation (wdtres) by overflow of watchdog timer (wdt) if the reset mode is set to reset upon overflow of the watchdog timer (wdt) (wdtm.wdm1 and wdtm.wdm0 bits = 10 or 11), the system is reset and each hardware is initialized to a specific state when wdt overflows (wdtres). if the wdtres signal is generated, the resf.wdtrf bit is set to 1, indicating that internal reset has occurred. the operations during the reset period and after rel ease of reset, other than the operation of the resf register, are the same as the rese t operation by reset pin input (see (1) reset operation by reset pin input ). (3) reset operation (lvires) by low-voltage detector (lvi) when lvi operation is enabled, the supply voltage (v dd0 , v dd1 ) and detection voltage (v lv i ) are compared and if the supply voltage drops below the det ection voltage, the system is reset (when the lvim.lvimd bit is set to ?1?) and each hardware is initialized to a specific state. the system is reset when the supply voltage drops belo w the detection voltage and the reset is released when the supply voltage is equal to or exceeds the detection voltage. after a reset is released, when the oscillation stabilization time (default value of the osts register: 2 14 /f x ) of the oscillator has elapsed, the cpu starts executing the program. the status of each hardware during the reset period and after reset release is the same as the reset operation by the reset pin (see (1) reset operation by reset pin input ). for details of the reset operation by low-voltage detector (lvi), see chapter 23 low-voltage detector . (4) reset operation (pocres) by power-on-clear circuit (poc) when the supply voltage (v dd0 , v dd1 ) and detection voltage (v poc0 ) are compared and if the supply voltage drops below the detection voltage (including at power appli cation), the system is reset and each hardware is initialized to a specific state. the system is reset when the supply voltage drops belo w the detection voltage and the reset is released when the supply voltage is equal to or exceeds the detection voltage. after a reset is released, when the oscillation stabilization time (default value of the osts register: 2 14 /f x ) of the oscillator has elapsed, the cpu starts executing the program. the status of each hardware during the reset period and after reset release is the same as the reset operation by the reset pin (see (1) reset operation by reset pin input ). for details of the reset operation by power-on-clear circuit (poc), see chapter 24 power-on-clear circuit .
user?s manual u18279ej3v0ud 1041 chapter 23 low-voltage detector 23.1 functions the low-voltage detector (lvi) has the following functions. ? compares the supply voltage (v dd0 , v dd1 ) and detection voltage (v lv i ) and generates an interrupt request signal (intlvil, intlvih) or internal reset signal (lvires) w hen the supply voltage drops below the detection voltage. ? the level of the supply voltage to be detec ted can be changed by software (in two steps). ? an interrupt request signal (intlvil, intlvih) or internal reset signal (lvires) can be selected. ? can operate in stop mode. ? operation can be stopped by software. if the low-voltage detector is used to generate a reset signal, the resf.lvirf bit is set to 1 when the reset signal is generated. for details of resf register, see chapter 22 reset functions . 23.2 configuration the block diagram is shown below. figure 23-1. block diagram of low-voltage detector lvis0 lvion ? + detection voltage source (v lvi ) v dd0 , v dd1 v dd0 , v dd1 intlvih internal bus low voltage detection level selector n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvimd lvif intlvil internal reset signal selector
chapter 23 low-voltage detector user?s manual u18279ej3v0ud 1042 23.3 control registers (1) low-voltage detection register (lvim) the lvim register is used to enable or disable low voltag e detection, and to set the operation mode of the low- voltage detector. the lvim register is a special register. it can be written only by a combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read-only. reset other than reset by the low-voltage det ector (lvi) sets this register to 00h. after reset: 00h r/w address: fffff890h <7> 6 5 4 3 2 <1> <0> lvim lvion 0 0 0 0 0 lvimd lvif lvion low voltage detection operation enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low voltage detection 0 generate interrupt request signal intlvil when supply voltage < detection voltage. generate interrupt request signal intlvih when supply voltage > detection voltage. 1 generate internal reset signal lvires when supply voltage < detection voltage. lvif low voltage detection flag 0 when supply voltage > detection voltage, or when operation is disabled 1 supply voltage < detection voltage cautions 1. after setting the lvion bit to 1, wait for 0.1 ms or more before checking the voltage using the lvif bit. 2. the value of the lvif flag is output as the output signals intlvil or intlvih when the lvion bit = 1 and lvimd bit = 0. 3. if the lvion bit = 1 and lvimd bit = 1, the low-voltage detector (lvi) cannot be stopped until a reset request other than that of by the lvi is generated. 4. be sure to set bits 2 to 6 to ?0?.
chapter 23 low-voltage detector user?s manual u18279ej3v0ud 1043 (2) low-voltage detection level select register (lvis) the lvis register is used to select t he level of low voltage to be detected. this register can be read or written in 8-bit units. reset other than reset by the low-voltage det ector (lvi) sets this register to 00h. after reset: 00h r/w address: fffff891h 7 6 5 4 3 2 1 0 lvis 0 0 0 0 0 0 0 lvis0 lvis0 detection level 0 4.4 v 0.2 v 1 4.2 v 0.2 v cautions 1. the lvis register cannot be wri tten until a reset request due to something other than the low-voltage detector (lvi) is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 1 to 7 to ?0?.
chapter 23 low-voltage detector user?s manual u18279ej3v0ud 1044 23.4 operation depending on the setting of the lvim.lvimd bit, an interrupt request signal (intlvil, intlvih) or an internal reset signal (lvires) is generated. 23.4.1 to use for inte rnal reset signal <1> mask the interrupt of the low-voltage detector (lvi). <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim. lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.1 ms or more by software. <5> by using the lvim.lvif bit, check if the supply voltage > detection voltage. <6> set the lvim.lvimd bit to 1 (to generate an internal reset signal). caution if the lvimd bit is set to 1, the contents of the lvim and lvis registers cannot be changed until a reset request other than the low-volt age detector (lvi) is generated.
chapter 23 low-voltage detector user?s manual u18279ej3v0ud 1045 figure 23-2. operation timing of low- voltage detector (lvimd bit = 1) supply voltage (v dd0 , v dd1 ) lvi detection voltage poc detection voltage lvion bit lvi detection signal lvirf bit note 1 poc reset request signal internal reset signal (active low) lvi reset request signal delay time delay delay delay delay delay delay delay set (by instruction, see <3> above) clear (by poc reset request signal) cleared by instruction note 2 notes 1. the lvirf bit is bit 0 of the reset source fl ag register (resf). for details of resf, see chapter 22 reset functions . 2. during the period in which the supply voltage is the set voltage or lower, the internal reset signal is retained (internal reset state).
chapter 23 low-voltage detector user?s manual u18279ej3v0ud 1046 23.4.2 to use for interrupt <1> mask the interrupt of the low-voltage detector (lvi). <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim.lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.1 ms or more by software. <5> by using the lvim.lvif bit, check if the supply voltage > detection voltage. <6> clear the interrupt request flag of lvi. <7> unmask the interrupt of lvi. set the lvion bit to 0. figure 23-3. operation timing of low- voltage detector (lvimd bit = 0) analog delay supply voltage (v dd0 , v dd1 ) lvi detection voltage poc detection voltage lvion bit lvi detection signal intlvih signal poc reset request signal lvif flag intlvil signal time delay delay set (by instruction, see <3> above) clear (by poc reset request signal) delay analog delay analog delay delay delay delay
user?s manual u18279ej3v0ud 1047 chapter 24 power-on clear circuit 24.1 function functions of the power-on-clear circuit (poc) are shown below. ? generates a reset signal (pocres) upon power application. ? compares the supply voltage (v dd0 , v dd1 ) and detection voltage (v poc0 ), and generates a reset signal when the supply voltage drops below the detection voltage (detection voltage (v poc0 ): 3.7 v 0.2 v). remark the v850e/if3 and v850e/ig3 have the reset source fl ag register (resf) that i ndicates generation of a reset signal (wdtres) by watchdog timer overflow and a reset signal (lvires) by low-voltage detector (lvi). the resf register is not cleared to 00h when a re set signal (wdtres or lvires) is generated, and its flag corresponding to the reset source is set to 1. the resf register is cleared (00h) when a reset si gnal (pocres) by power-on-clear circuit (poc) is generated. for details of the resf register, see chapter 22 reset functions . 24.2 configuration the block diagram is shown below. figure 24-1. block diagram of power-on-clear circuit reset detection voltage source (v poc0 ) internal reset signal v dd0 , v dd1
chapter 24 power-on clear circuit user?s manual u18279ej3v0ud 1048 24.3 operation when the supply voltage and detection voltage are compared and if the supply voltage drops below the detection voltage (including at power application), the system is reset and each hardware is initialized to the specific status. the system is reset from when low vo ltage is detected until the supply voltage becomes higher than the detection voltage. after a reset is released, when the oscillation stabilization time (default va lue of the osts register: 2 14 /f x ) of the oscillator has elapsed, the cp u starts executing the program. the status of each hardware during the reset period and after reset release is the same as the reset operation by the reset pin (see 22.3 (1) reset operation by reset pin input ). the following shows the timing chart. figure 24-2. timing of reset signal generation by power-on-clear circuit time delay supply voltage (v dd0 , v dd1 ) poc detection voltage (v poc0 ) internal reset signal poc detection signal reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time)
user?s manual u18279ej3v0ud 1049 chapter 25 regulator 25.1 overview the v850e/if3 and v850e/ig3 have an internal regulator to realize a 5 v single power supply operation. this regulator supplies a stepped-down v dd0 and v dd1 power supply voltage to the oscillation block and internal logic circuits (except the a/d converters 0 to 2 and i/o buffers). the regulator output voltage (regc0, regc1 pins) is set to 1.5 v (typ.). figure 25-1. regulator ev dd i/o buffer a/d converter 0 a/d converter 1 a/d converter 2 av ss0 av ss1 av refp0 av refp1 av dd0 ev ss0 ev dd0 av dd1 av ss2 v ss0 ev dd2 note ev ss2 note av dd2 v dd0 regc0 v ss1 ev dd1 ev ss1 v dd1 regc1 oscillator internal digital circuit 1.5 v (typ.) bidirectional level shifter regulator regulator note v850e/ig3 only caution use the regulator with a setting of v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 (v850e/ig3 only) = av dd0 = av dd1 = av dd2 = av ref0 = av ref1 .
chapter 25 regulator user?s manual u18279ej3v0ud 1050 25.2 operation the regulator of this product always operates in any mode (normal operation mode, halt mode, idle mode, stop mode, or during reset). be sure to connect a capacitor (4.7 f (recommended value)) note to the regc0 and regc1 pins to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. note use the low-esr (0.5 or lower) of the series resistance component esr. caution the v850e/if3 and v850e/ig3 have two regulator s each. therefore, c onnect a capacitor to each of the regc0 and regc1 pins. figure 25-2. connection of regc0 and regc1 pins reg input voltage 3.5 to 5.5 v voltage supply to oscillator/internal logic 1.5 v (typ.) v dd0 , v dd1 v ss0 , v ss1 regc0, regc1 4.7 f (recommended)
user?s manual u18279ej3v0ud 1051 chapter 26 on-chip debug function the on-chip debug function of the v850e/if3 and v850e/ig3 can be re alized in the following two ways. ? debugging using dcu (debug control unit) (using minicube) by using the drst, dck, dms, ddi, and ddo pins as d ebug interface pins, on-chip debugging is realized by the internal dcu of the v850e/ig3 note . ? debugging without using dcu (using minicube2) on-chip debugging is realized by minicube2 witho ut using the dcu but by us ing the user resources. note the v850e/if3 does not have an internal dcu. the following table shows the features of the two on-chip debug functions. table 26-1. on-chip debug function features debugging using dcu debugging without using dcu target product v850e/ig3 v850e/if3, v850e/ig3 debug interface pins drst, dck, dms, ddi, ddo ? when uarta0 is used rxda0, txda0 ? when csib0 is used sib0, sob0, sckb0, hs (p43) securing of user resources not required required hardware break function 2 point s 2 points (v850e/ig3 only) internal rom area 4 points 4 points software break function ram area 2000 points 2000 points real-time ram monitor function note 1 available available dynamic memory modification (dmm) function note 2 available available mask function reset, intwdt, wait note 3 reset, wait note 3 rom security function 10-byte id code aut hentication 10-byte id code authentication hardware used minicube minicube2 trace function not supported not supported debug interrupt interface function (dbint) not supported not supported notes 1. this is a function which reads out memo ry contents during program execution. 2. this is a function which rewrites ra m contents during program execution. 3. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1052 26.1 debugging using dcu the program can be debugged by using the debug in terface pins (drst, dck, dms, ddi, and ddo) and connecting an on-chip debug simulator (minicube). caution only the v850e/ig3 has a dcu. 26.1.1 circuit connection examples when the minicube is used, use of the fo llowing kel connector is recommended. part number ? 8830e-026-170s: straight type ? 8830e-026-170l: right-angle type it is necessary to mount an emulator and circuit for connection on the target system. figure 26-1. connection example of on-chip debug emulator (minicube) s t a t u s t a r g e t p o w e r usb interface cable v850e/ig3 minicube ocd cable kel adapter kel connector target system host machine
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1053 (1) pin configuration the following figure shows the pin configuration of t he emulator connector (on the target system side). figure 26-2. pin configuration of emulat or connector (on target system side) board edge (top view) b12 a12 b2 a2 b13 a13 b1 a1 caution design the board based on the dimensions of the connector when actually mounting the connector on the board.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1054 (2) pin functions the following table shows the pin functions of the emulator connector (on the target system side). table 26-2. pin functions of emulator connector (on target system side) pin no. pin name i/o pin function a1 (reserved 1) ? (connect to gnd) a2 (reserved 2) ? (connect to gnd) a3 (reserved 3) ? (connect to gnd) a4 (reserved 4) ? (connect to gnd) a5 (reserved 5) ? (connect to gnd) a6 (reserved 6) ? (connect to gnd) a7 ddi output data output for debug serial interface a8 dck output clock output for debug serial interface a9 dms output transfer mode select output for debug serial interface a10 ddo input data input for debug serial interface a11 drst output dcu reset output a12 (reserved 7) ? (leave open) a13 flmd0 output control signal for flash memory downloading b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 port0_in ? (connect to gnd) b12 port1_in ? (connect to gnd) b13 v dd ? 5 v input (for monitoring power application to target) cautions 1. the connection of the pins not supported in the v850e /ig3 depends on the emulator used. 2. the pattern on the target board must satisfy the fo llowing conditions. ? keep the pattern length to within 100 mm. ? shield the clock signal with gnd. remark input/output is as viewed from the emulator side.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1055 (3) recommended circuit example the following figure shows an example of the recommend ed circuit of the emulator connector (on the target system side). figure 26-3. example of recommended connection of emulator v850e/ig3 flmd0 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst (reserved 7) flmd0 v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd port0_in port1_in note 1 note 1 note 1 note 1 note 1 (open) 1 to 10 k (open) (open) note 2 5 v 5 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 ddi dck dms ddo drst note 4 kel connector 8830e-026-170s notes 1 . keep the pattern length to within 100 mm. 2. shield the dck signal with gnd. 3. for detecting power supply to the target board. 4. when drst pin is high level: on-chip debug mode when drst pin is low level: normal operation mode the drst pin is internally pulled down in the v850e/ig3. caution the ddo signal is 5 v output, and the input level of the ddi, dck, dms, and drst signals is ttl level.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1056 26.1.2 interface signals the interface signals on the v850e/ig3 side are described below. (1) drst this is a reset input signal for the on-chip debug un it. it is a negative-logic signal that asynchronously initializes the debug control unit (dcu). minicube changes the level of the drs t signal from low to high for output and starts the on-chip debug unit of the v850e/ig3 when it detects vdd of the target system after the integr ated debugger is started. if vdd is not detected from the tar get system, the output signals (drst, dck, dms, ddi, and flmd0 pins) from the minicube go into a high-impedance state. when the drst signal goes high, a reset sig nal is also generated in the v850e/ig3. when starting debugging by starting the integrated debugger, a reset signal is always generated. (2) dck this is a clock input signal. it supplies a 20 mhz cl ock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at the rising edge of the dck signal, and the data ddo is output at its falling edge. (3) dms this is a transfer mode select signal. the transfer st atus in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) flmd0 the flash self programming function is used for the function to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin of the v850e/ig3. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to th e high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin of the v850e/ig3. the same port as the one used by t he user program to realize the fl ash self programming function may be used. on the console of the integrat ed debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. for details, refer to the id850qb integrated debugger operation user?s manual .
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1057 26.1.3 maskable functions reset, intwdt, and wait note signals can be masked. the maskable functions with the debugger (id850qb) and the corresponding functions are shown below. note pd70f3454gc-8ea-a and 70f3454f1-da9-a only table 26-3. maskable functions maskable functions with debugger (id850qb) corresponding function of v850e/ig3 nmi0 non-maskable interrupt request signal (intwdt) generation nmi1 nmi2 stop hold reset reset pin input, reset signal (wdtres) generation by watchdog timer overflow, reset signal (lvires) generation by low-voltage detector (lvi), reset signal (pocres) generation by power-on-clear circuit (poc) wait wait pin note input note pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1058 26.1.4 cautions (1) if a reset signal is input (from the target system or due to the execution of an internal reset) while the program is running, the software breaks specified for the on-ch ip flash memory area will no longer occur. use hardware breaks to avoid this problem. the disabled software breaks can be enabled again by generating a forcible break or a hardware break. (2) pin reset during a break is masked and the cpu and perip heral i/o are not reset. if pi n reset or internal reset is generated as soon as the flash memo ry is rewritten by dma or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (3) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. (4) the flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. therefore, do not use the device used in debugging for a mass production product. (5) because the ddi and dck pins func tion alternately as the csib0 i/o pi ns (sob0, sckb0), uarta0 output pin (txda0), and external interrupt pin (intp13), csib0, uarta0, and intp13 cannot be used while the on- chip debug function is being used. (6) when the on-chip debug function is used, the clock generator and pll continue operating even if the stop mode is set.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1059 26.2 debugging without using dcu the following describes how to implement an on-chip debug function using minicube2 with the uarta0 pins (rxda0, txda0) or csib0 pins (sib0, sob0, sckb0, hs (p43)) as debug interfaces, without using the dcu. 26.2.1 circuit connection examples figure 26-4. circuit connection example when ua rta0/csib0 is used for communication interface qb-mini2 v850e/if3, v850e/ig3 gnd 5 v 5 v reset_out rxd/si note 1 vdd txd/so note 1 sck hs clk flmd1 note 2 flmd0 note 2 reset_in note 3 note 4 txda0/sob0 note 5 rxda0/sib0 sckb0 flmd1 reset circuit flmd0 port x 100 10 k 1 to 10 k 1 k reset signal 10 k 1 to 10 k 1 to 10 k 3 to 10 k 1 to 10 k 5 v note 6 5 v 5 v p43 reset minicube2 notes 1. connect txda0/sob0 (transmit side) of the v850e /if3 and v850e/ig3 to rxd/si (receive side) of the target connector, and txd/so (transmit side) of the target connector to rxda0/sib0 (receive side) of the v850e/if3 and v850e/ig3. 2. the v850e/if3, v850e/ig3-side pin connected to this pin (flmd0 , flmd1) can be used as an alternate-function pin other than while the memory is rewritten during a break in debugging, because this pin is in a hi-z state. 3. this connection is designed assuming that the reset signal is output from the n-ch open-drain buffer (output resistance: 100 or less). 4. ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), v ss0 , v ss1 , av ss0 , av ss1 , av ss2 5. ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), v dd0 , v dd1 , av dd0 , av dd1 , av dd2 6. the circuit enclosed by broken lines is designed for flash self programming, which controls the flmd0 pin via ports. use the port for inputting or outputting the high level. when flash self programming is not performed, a pull-down resistanc e for the flmd0 pin can be within 1 to 10 k . remark see table 26-4 for pins used when uarta0 or csib0 is used for communication interface.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1060 table 26-4. wiring between v850e /if3, v850e/ig3, and minicube2 (1/2) pin configuration of minicube2 (qb-mini2) when uarta0 used pin no. if3 ig3 signal name i/o pin function pin name gc gc gf f1 si/r x d input pin to receive commands and data from v850e/if3 and v850e/ig3 txda0 39 48 76 n12 so/t x d output pin to transmit commands and data to v850e/if3 and v850e/ig3 rxda0 38 47 75 p12 sck output clock output pin for 3-wire serial communication not needed not needed not needed not needed not needed clk output clock output pin to v850e/if3 and v850e/ig3 not needed not needed not needed not needed not needed reset_out output reset output pin to v850e/if3 and v850e/ig3 reset 35 40 68 p9 flmd0 output output pin to set v850e/if3 and v850e/ig3 to debug mode or programming mode flmd0 37 46 74 n9 flmd1 output output pin to set programming mode flmd1 60 76 4 a12 hs input handshake signal for csi0 + hs communication not needed not needed not needed not needed not needed v ss0 32 37 65 n7, p7 v ss1 66 85 13 a9, b9 av ss0 6 7 35 e1, e2 av ss1 11 12 40 h1, h2 av ss2 22 27 55 p1, n2, m3, l4 ev ss0 54 64 92 a14, g13, g14 ev ss1 79 1 29 a1, b1, c1, c2, d3, e4 gnd ? ground ev ss2 not needed 42 70 n11, p11, p14 reset_in input reset input pin on the target system
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1061 table 26-4. wiring between v850e /if3, v850e/ig3, and minicube2 (2/2) pin configuration of minicube2 (qb-mini2) when csib0-hs used pin no. if3 ig3 signal name i/o pin function pin name gc gc gf f1 si/r x d input pin to receive commands and data from v850e/if3 and v850e/ig3 sob0 39 48 76 n12 so/t x d output pin to transmit commands and data to v850e/if3 and v850e/ig3 sib0 38 47 75 p12 sck output clock output pin for 3-wire serial communication sckb0 40 49 77 m14 clk output clock output pin to v850e/if3 and v850e/ig3 not needed not needed not needed not needed not needed reset_out output reset output pin to v850e/if3 and v850e/ig3 reset 35 40 68 p9 flmd0 output output pin to set v850e/if3 and v850e/ig3 to debug mode or programming mode flmd0 37 46 74 n9 flmd1 output output pin to set programming mode flmd1 60 76 4 a12 hs input handshake signal for csi0 + hs communication p43 41 50 78 m13 v ss0 32 37 65 n7, p7 v ss1 66 85 13 a9, b9 av ss0 6 7 35 e1, e2 av ss1 11 12 40 h1, h2 av ss2 22 27 55 p1, n2, m3, l4 ev ss0 54 64 92 a14, g13, g14 ev ss1 79 1 29 a1, b1, c1, c2, d3, e4 gnd ? ground ev ss2 not needed 42 70 n11, p11, p14 reset_in input reset input pin on the target system
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1062 26.2.2 maskable functions reset signal can only be masked. the maskable functions with the debugger (id850qb) and the corresponding functions are shown below. table 26-5. maskable functions maskable functions with debugger (id850qb) corresponding function of v850e/if3, v850e/ig3 nmi0 nmi1 nmi2 stop hold reset reset signal generation by reset pin input wait wait pin note input note pd70f3454gc-8ea-a and 70f3454f1-da9-a only 26.2.3 securing of user resources the user must prepare the following to perform communication between mini cube2 and the v850e/if3, v850e/ig3 and implement each debug func tion. these items need to be set in the user program or using the compiler options. (1) securement of memory space the shaded portions in figure 26-5 are the areas rese rved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces. these spaces must be secured so as not to be used by the user program.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1063 figure 26-5. memory spaces where de bug monitor programs are allocated uart0/csib0 interrupt vector (4 bytes) reset vector (4 bytes) interrupt vector for debugging (4 bytes) (2 kb) security id area (10 bytes) : debugging area 00fffffh note 1 0000060h note 2 0000070h 0000000h access-prohibited area internal rom (16 bytes) note 3 3ffc000h access-prohibited area internal ram internal rom area internal ram area notes 1. address values vary depending on the product. internal rom size debugging area pd70f3451 (v850e/if3) pd70f3453 (v850e/ig3) 128 kb 001f800h to 001ffffh pd70f3452 (v850e/if3) pd70f3454 (v850e/ig3) 256 kb 003f800h to 003ffffh 2. start address values when uarta0 and csib0 are used are as follows. target serial interface interrupt name start address intua0re 000004b0h intua0r 000004c0h uarta0 intua0t 000004d0h intcb0re 000004e0h intcb0r 000004f0h csib0 intcb0t 00000500h 3. address values vary depending on the product. internal ram size debugging area pd70f3451 (v850e/if3) pd70f3453 (v850e/ig3) 8 kb 3ffdff0h to 3ffdfffh pd70f3452 (v850e/if3) pd70f3454 (v850e/ig3) 12 kb 3ffeff0h to 3ffefffh
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1064 ? security id setting the id code must be embedded in the area between 0000070h and 0000079h in figure 26-5, to prevent the memory from being read by an unauthorized person. for details, see 26.3 rom security function . (2) reset vector a reset vector includes the jump in struction for the debug monitor program. [how to secure areas] it is not necessary to secure this area intentionally. when downloading a program, however, the debugger rewrites the reset vector in accordance with the followin g cases. if the rewritt en pattern does not match the following cases, the debugger generates an error (f0c34 when using the id850qb). (a) when two nop instructions ar e placed in succession from address 0 before rewriting after rewriting 0x0 nop jumps to debug monitor program at 0x0 0x2 nop 0x4 xxxx 0x4 xxxx (b) when two 0xffff are successi vely placed from address 0 (already era sed device) before rewriting after rewriting 0x0 0xffff jumps to debug monitor program at 0x0 0x2 0xffff 0x4 xxxx 0x4 xxxx (c) the jr instruction is placed at address 0 (when using ca850) before rewriting after rewriting 0x0 jr disp22 jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using iar compiler iccv850) before rewriting after rewriting 0x0 mov imm32,reg1 jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) the jump instruction for the debug monitor program is placed at address 0 before rewriting after rewriting jumps to debug monitor program at 0x0 no change
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1065 (3) securement of area for debug monitor program the shaded portions in figure 26-5 are the areas where the debug monitor program is allocated. the monitor program performs initialization processing for debug commu nication interface and run or break processing for the cpu. the internal rom area mu st be filled with 0xff. this area mu st not be rewritten by the user program. [how to secure areas] it is not necessarily required to secure this area if the user program does not use this area. to avoid problems that may occur during the debugger st artup, however, it is recommended to secure this area in advance, using the compiler. the following shows examples for securing the area, using the nec electronics compiler ca850. add the assemble source file and link directive code, as shown below. ? assemble source (add the following code as an assemble source file.) -- secures 2 kb space for monitor rom section .section "monitorrom", const .space 0x800, 0xff -- secures interrupt vector for debugging .section "dbg0" .space 4, 0xff -- secures interrupt vector for serial communication -- change the section name according to the serial communication mode used .section "intcb0re" .space 4, 0xff .section "intcb0r" .space 4, 0xff .section "intcb0t" .space 4, 0xff -- secures 16-byte space for monitor ram section .section "monitorram", bss .lcomm monitorramsym, 16, 4; -- defines symbol monitorramsym ? link directive (add the following code to the link directive file.) the following shows an example when the intern al rom has 256 kb (end address is 003ffffh) and internal ram has 12 kb (end address is 3ffefffh). mromseg : !load ?r v0x03f800{ monitorrom = $progbits ?a monitorrom; }; mramseg : !load ?rw v0x03ffeff0{ monitorram = $nobits ?aw monitorram; };
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1066 (4) securement of communication serial interface uarta0 or csib0 is used for communication betwe en minicube2 and the v850e/if3, v850e/ig3. the settings related to the serial interface modes are perfo rmed by the debug monitor prog ram, but if the setting is changed by the user program, a communication error may occur. to prevent such a problem from occurring, communica tion serial interface must be secured in the user program. [how to secure communica tion serial interface] ? serial interface registers do not set the registers related to uarta0 and csib0 in the user program. ? interrupt mask register when uarta0 is used, do not mask the reception end interrupt (intua0r). w hen csib0 is used, do not mask the reception end interrupt (intcb0r). (a) when uarta0 is used ua0ric 0 6543210 7 (b) when csib0 is used cb0ric 0 6543210 7 remark : don?t care ? port registers when uarta0 is used when uarta0 is used for communication, port registers are set to make the txda0 and rxda0 pins valid by the debug monitor program. do not change the follow ing register settings with the user program during debugging. (the same value can be overwritten.) pmc4 11 6543210 7 pfc4 11 6543210 7 pfce4 00 6543210 7 remark : don?t care
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1067 ? port registers when csib0 is used when csib0 is used, port registers are set to make the sib0, sob0, sckb0, and hs (p43) pins valid by the debug monitor program. do not change the following register settings with the user program during debugging. (the same value can be overwritten.) (a) sib0, sob0, and sckb0 settings pmc4 111 6543210 7 pfc4 000 6543210 7 pfce4 000 6543210 7 (b) hs (p43 pin) settings p4 note 6543210 7 pm4 0 6543210 7 pmc4 0 6543210 7 note writing to this bit is prohibited. the values corresponding to the hs pin are changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1068 26.2.4 cautions (1) handling of device that was used for debugging do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewr ites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. (2) when breaks cannot be executed forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the v850e/if3, v850e/ig3, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and t he v850e/if3, v850e/ig3 is uarta0, and the peripheral clock has been stopped (3) when pseudo real-ti me ram monitor (rrm) function and dmm function do not operate the pseudo rrm function and dmm function do not operat e if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the v850e/if3, v850e/ig3, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and t he v850e/if3, v850e/ig3 is uarta0, and the peripheral clock has been stopped ? mode for communication between minicube2 and the v850e/if3, v850e/ig3 is uarta0, and a clock different from the one specified in t he debugger is used for communication (4) standby release with pseudo rrm and dmm functions enabled the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the v850e/if3, v850e/ig3 is csib0 ? mode for communication between minicube2 and t he v850e/if3, v850e/ig3 is uarta0, and the peripheral clock has not stopped. (5) writing to peripheral i/o re gisters that requires a specifi c sequence, using dmm function peripheral i/o registers that re quires a specific sequence cannot be written with the dmm function. (6) flash self programming if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1069 26.3 rom security function 26.3.1 security id the flash memory versions of the v850e/if3 and v850e/ig3 perform authentic ation using a 10-byte id code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte on-chip flash memory area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading fl ash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. figure 26-6. security id area 0000079h 0000070h 0000000h security id (10 bytes) caution after the flash memory is erased , 1 is written to the entire area.
chapter 26 on-chip debug function user?s manual u18279ej3v0ud 1070 26.3.2 setting the following shows how to set the id code as shown in table 26-6. when the id code is set as shown in table 26-6, the id code input in the configuration dialog box of the id850qb is ?123456789abcdef123d4? (the id code is case-insensitive). table 26-6. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified in the compiler common opti ons dialog box in pm+ if a device file that supports ca850 ver. 2.60 and later and the security id is used.
user?s manual u18279ej3v0ud 1071 chapter 27 flash memory the v850e/if3 and v850e/ig3 have a 128 kb or 256 kb on-chip flash memory. ? pd70f3451 (v850e/if3), 70f3453 (v850e/ig3): 128 kb on-chip flash memory version ? pd70f3452 (v850e/if3), 70f3454 (v850e/ig3): 256 kb on-chip flash memory version flash memory can be rewritten with the flash memory programmer or using the self programming mode. writing to the flash memory programmer can be performed wit h the flash memory programmer that is connected to the target system. writing in the self programming mode can be performed with an application program, without using the flash memory programmer. flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the v850e/if3 and v850e/ig3 is soldered onto the target system. { for differentiating software according to the specif ication in small scale production of various models. { for data adjustment when starting mass production. 27.1 features { all area batch erase or erase in block units (2 kb) { communication through serial interface from the flash memory programmer { erase/write voltage: erase/write is possible with a single power supply { on-board programming { flash memory self programming possible { secure rewriting of entire flash memory area by self programming using boot swap function { rewriting method ? rewriting by communication with flash memory programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { rewriting flash memory and read disable function supported (security enforced) { interrupts can be acknowledged during self programming.
chapter 27 flash memory user?s manual u18279ej3v0ud 1072 27.2 memory configuration the internal flash memory area of the v850e/if3 and v850e/ig3 is divided into 64 or 128 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory located at the addresses of blocks 0 to 31 is replaced by the physical memory located at the addresses of bloc ks 32 to 63. for details of the boot swap function, see 27.9 rewriting by self programming . figure 27-1. flash memory mapping block 0 (2 kb) block 1 (2 kb) block 31 (2 kb) block 33 (2 kb) block 63 (2 kb) block 32 (2 kb) block 125 (2 kb) block 127 (2 kb) block 126 (2 kb) block 0 (2 kb) block 1 (2 kb) block 31 (2 kb) block 33 (2 kb) block 63 (2 kb) block 32 (2 kb) 00007ffh 0000800h 0000fffh 0001000h 00107ffh 0010800h 0010fffh 0011000h 001f7ffh 001f800h 001ffffh 0020000h 003ffffh 003f800h 003f7ffh 003f000h 003efffh 003e800h 003e7ffh 000f7ffh 000f800h 000ffffh 0010000h 0000000h 128 kb 256 kb note 1 note 2 notes 1. area to be replaced with the boot area by the boot swap function 2. boot area
chapter 27 flash memory user?s manual u18279ej3v0ud 1073 27.3 functional overview the internal flash memory of the v850e/if3 and v850e/ig3 can be rewritten by using t he rewrite function of the dedicated flash programmer, regardless of whether the v850e/if3 and v850e/ig3 have already been mounted on the target system or not (off- board/on-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten und er various conditions, such as while communicating with an external device. table 27-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. (during self programming, instructions cannot be fetched from or data access cannot be made to the on-chip flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd.
chapter 27 flash memory user?s manual u18279ej3v0ud 1074 table 27-2. basic functions support ( : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. chip erasure the contents of the entire memory area are erased all at once. (supported by specifying area for block erasure) write writing to specified addresses, and a verify check to see if write level is secured are performed. verify/checksum data read from the flash memory is compared with data transferred from the flash memory programmer. (can be read by user program) blank check the erasure status of the entire memory is checked. security setting use of the block erase command, chip erase command, program command, and read command can be prohibited. (only values set by on- board/off-board programming can be retained) table 27-3. security functions support function function outline on-board/off-board programming self programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. chip erase command prohibit execution of block erase and chip erase commands on all blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. program command prohibit write and block erase commands on all blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. read command prohibit read command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. for details, see 27.3.2 security function .
chapter 27 flash memory user?s manual u18279ej3v0ud 1075 27.3.1 erase units (1) all area batch erase flash memory area 128 kb or 256 kb can be erased at the same time. (2) erase in block units can be erased in block units. ? pd70f3451 (v850e/if3), 70f3453 (v850e/ig3): block 0 to block 63: each 2 kb ? pd70f3452 (v850e/if3), 70f3454 (v850e/ig3): block 0 to block 127: each 2 kb 27.3.2 security function the commands and functions can be secured when the flash memory is rewritten. as a factory-set condition in the v850e/if3 and v850e/ig3, ?all enabled? is selected and the flash memory to which nothing has been written is secured. (1) in flash memory programming mode security setting (flag) command all enabled reading prohibited writing prohibited chip erase prohibited block erase prohibited boot block cluster rewriting prohibited read write u chip erase block erase u changing of security setting note 1 note 1 note 1 note 1 notes 1, 2 other commands (such as blank check and verify) : command can be accepted. u : command can be accepted in areas other than boot block cluster. : protect error notes 1. enabled setting can be disabled. however, a protect error occurs if disabled setting is enabled. to enable security that has been disabled, the chip must be erased. if chip erase prohibition or boot block cluster rewriting prohibition is select ed, the security setting cannot be enabled. 2. if boot block cluster rewriting prohibition is set, the boot block cluster last block number (128 kb version: 63, 256 kb version: 127) cannot be changed.
chapter 27 flash memory user?s manual u18279ej3v0ud 1076 (2) in self programming mode security setting (flag) command all enabled reading prohibited writing prohibited chip erase prohibited block erase prohibited boot block cluster rewriting prohibited flashwordread flashwordwrite u flashblockerase u flashbootswap flashsetinfo note 1 note 1 note 1 note 1 notes 1, 2 other functions (such as flashblockblankcheck and flashblockverify) : command can be accepted. u : function can be executed in an area other than boot block cluster. : protect error notes 1. enabled setting can be disabled. however, a protect error occurs if disabled setting is enabled. to enable security that has been disabled, the chip must be erased in the flash self programming mode. if chip erase prohibition is selected, the security setting cannot be enabled. 2. if boot block cluster rewriting prohibition is set, the boot block cluster last block number (128 kb version: 63, 256 kb version: 127) and boot swap cluster setting flag cannot be changed.
chapter 27 flash memory user?s manual u18279ej3v0ud 1077 27.4 writing with flash memory programmer writing can be performed either on-boar d or off-board using a flash memory programmer (pg-fp4, pg-fp5, fl- pr4, or fl-pr5) and minicube2. (1) on-board programming the contents of the flash memory ar e rewritten after the v850e/if3 or v850e/ig3 is mounted on the target system. mount connectors, etc., on the target syst em to connect the flash memory programmer. (2) off-board programming writing to a flash memory is performed before m ounting the v850e/if3 or v850e/ig3 on the target system. remark fl-pr4 and fl-pr5 are products of naito densei machida mfg. co., ltd.
chapter 27 flash memory user?s manual u18279ej3v0ud 1078 27.5 flash memory programming environment the following shows the environment r equired for writing programs to the flash memory of the v850e/if3 and v850e/ig3. v850e/if3, v850e/ig3 uarta0/csib0 reset reset rs-232c/usb, etc. flash memory programmer host machine v dd note 2 flmd1 flmd1 note 1 gnd flmd0 flmd0 notes 1. v dd0 , v dd1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av refp0 , av refp1 2. v ss0 , v ss1 , ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av ss0 , av ss1 , av ss2 a host machine is required for controlling the flash memory programmer. uarta0 or csib0 is used for t he interface between the flash memo ry programmer and the v850e/if3 or v850e/ig3 to perform writing, erasing, etc. supply the operating clock of the v850e/if3 or v850e/ig3 via the oscillator configured on the v850e/if3 or v8 50e/ig3 board using a resonator and a capacitor. table 27-4. environment and communication mode communication mode environment uarta0 csib0 csib0 for handshake flash memory programmer (pg-fp4, pg-fp5, fl-pr4, and fl-pr5) minicube2 remark : supported, : not supported
chapter 27 flash memory user?s manual u18279ej3v0ud 1079 27.6 communication method of flash memory programming (1) uart0 communication method transfer rate: 9600 to 153,600 bps (lsb first) v850e/if3, v850e/ig3 flash memory programmer reset reset txda0 rxd rxda0 txd v dd note 2 flmd1 flmd1 note 1 gnd flmd0 flmd0 notes 1. v dd0 , v dd1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av refp0 , av refp1 2. v ss0 , v ss1 , ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av ss0 , av ss1 , av ss2 cautions 1. supply the operating clock of the v 850e/if3 or v850e/ig3 via the oscillator configured on the v850e/if3 or v850e/ig3 board us ing a resonator and a capacitor. 2. for details, refer to the u ser?s manual of each programmer.
chapter 27 flash memory user?s manual u18279ej3v0ud 1080 table 27-5. wiring correspondence between dedicated flash memory programmer and v850e/if3, v850e/ig3 v850e/if3, v850e/ig3 pin no. v850e/if3 v850e/ig3 pin no. dedicated flash memory programmer (pg-fp4 or pg-fp5) i/o (pg-fp4 or pg- fp5 side) pin name gc gc gf f1 v ss0 32 37 65 n7, p7 v ss1 66 85 13 a9, b9 ev ss0 54 64 92 a14, g13, g14 ev ss1 79 1 29 note 1 ev ss2 ? 42 70 n11, p11, p14 av ss0 6 7 35 e1, e2 av ss1 11 12 40 h1, h2 1 gnd ? av ss2 22 27 55 l4, m3, n2, p1 2 reset output reset 35 40 68 p9 3 si/rxd input txda0 39 48 76 n12 v dd0 30 35 63 n5, p5 v dd1 68 87 15 a7, b7 ev dd0 55 65 93 f13, f14 ev dd1 80 100 28 a3, b2 ev dd2 ? 41 69 n10, p10 av dd0 8 9 37 f1 av dd1 9 10 38 g1 av dd2 21 26 54 m1, m2 av refp0 7 8 36 f2 4 v dd ? av refp1 10 11 39 g2 5 so/txd output rxda0 38 47 75 p12 6 v pp nc ? ? ? ? 7 sck nc ? ? ? ? 8 h/s nc ? ? ? ? 9 clk note 2 output x1 note 2 33 38 66 p8 10 vde nc ? ? ? ? 11 v dd2 ? nc ? ? ? ? 12 flmd1 output note 3 60 76 4 a12 13 rfu-1 nc ? ? ? ? 14 flmd0 output flmd0 37 46 74 n9 15 not used nc ? ? ? ? 16 not used nc ? ? ? ? notes 1. a1, b1, c1, c2, d3, and e4 2. in the v850e/if3 and v850e/ig3, external clock inpu t is prohibited. mount the resonator on board. 3. connect to flmd1 or gnd via a resistor. remark nc: no connection gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 27 flash memory user?s manual u18279ej3v0ud 1081 (2) csib0 communication method transfer rate: up to 2.5 mbps (msb first) reset reset v850e/if3, v850e/ig3 flash memory programmer sob0 si sib0 so sckb0 sck v dd note 2 flmd1 flmd1 note 1 gnd flmd0 flmd0 notes 1. v dd0 , v dd1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av refp0 , av refp1 2. v ss0 , v ss1 , ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av ss0 , av ss1 , av ss2 cautions 1. supply the operating clock of the v 850e/if3 or v850e/ig3 via the oscillator configured on the v850e/if3 or v850e/ig3 board us ing a resonator and a capacitor. 2. for details, refer to the u ser?s manual of each programmer. the flash memory programmer outputs (master) trans fer clocks and the v850e/if3 or v850e/ig3 operates as a slave.
chapter 27 flash memory user?s manual u18279ej3v0ud 1082 table 27-6. wiring correspondence between dedicated flash memory programmer and v850e/if3, v850e/ig3 v850e/if3, v850e/ig3 pin no. v850e/if3 v850e/ig3 pin no. flash memory programmer (pg-fp4 or pg-fp5) i/o (pg-fp4 or pg- fp5 side) pin name gc gc gf f1 v ss0 32 37 65 n7, p7 v ss1 66 85 13 a9, b9 ev ss0 54 64 92 a14, g13, g14 ev ss1 79 1 29 note 1 ev ss2 ? 42 70 n11, p11, p14 av ss0 6 7 35 e1, e2 av ss1 11 12 40 h1, h2 1 gnd ? av ss2 22 27 55 l4, m3, n2, p1 2 reset output reset 35 40 68 p9 3 si/rxd input sob0 39 48 76 n12 v dd0 30 35 63 n5, p5 v dd1 68 87 15 a7, b7 ev dd0 55 65 93 f13, f14 ev dd1 80 100 28 a3, b2 ev dd2 ? 41 69 n10, p10 av dd0 8 9 37 f1 av dd1 9 10 38 g1 av dd2 21 26 54 m1, m2 av refp0 7 8 36 f2 4 v dd ? av refp1 10 11 39 g2 5 so/txd output sib0 38 47 75 p12 6 v pp nc ? ? ? ? 7 sck output sckb0 40 49 77 m14 8 h/s nc ? ? ? ? 9 clkz note 2 output x1 note 2 33 38 66 p8 10 vde nc ? ? ? ? 11 v dd2 ? nc ? ? ? ? 12 flmd1 output note 3 60 76 4 a12 13 rfu-1 nc ? ? ? ? 14 flmd0 output flmd0 37 46 74 n9 15 not used nc ? ? ? ? 16 not used nc ? ? ? ? notes 1. a1, b1, c1, c2, d3, and e4 2. in the v850e/if3 and v850e/ig3, external clock inpu t is prohibited. mount the resonator on board. 3. connect to flmd1 or gnd via a resistor. remark nc: no connection gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 27 flash memory user?s manual u18279ej3v0ud 1083 (3) csib0 communication method supporting handshake transfer rate: up to 2.5 mbps (msb first) reset reset v850e/if3, v850e/ig3 flash memory programmer sob0 si sib0 so sckb0 sck p43 hs v dd note 2 flmd1 flmd1 note 1 gnd flmd0 flmd0 notes 1. v dd0 , v dd1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av refp0 , av refp1 2. v ss0 , v ss1 , ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av ss0 , av ss1 , av ss2 cautions 1. supply the operating clock of the v 850e/if3 or v850e/ig3 via the oscillator configured on the v850e/if3 or v850e/ig3 board us ing a resonator and a capacitor. 2. for details, refer to the u ser?s manual of each programmer. the flash memory programmer outputs t he transfer clock, and the v850e/if3 or v850e/ig3 operates as a slave. when the pg-fp4 or pg-fp5 is used, it sends the following signals to the v850e/if3 or v850e/ig3. for details, refer to the pg-fp4 user?s manual (u15260e) or pg-fp5 user?s manual (u18865e) .
chapter 27 flash memory user?s manual u18279ej3v0ud 1084 table 27-7. wiring correspondence between dedicated flash memory programmer and v850e/if3, v850e/ig3 v850e/if3, v850e/ig3 pin no. v850e/if3 v850e/ig3 pin no. flash memory programmer (pg-fp4 or pg-fp5) i/o (pg-fp4 or pg- fp5 side) pin name gc gc gc f1 v ss0 32 37 65 n7, p7 v ss1 66 85 13 a9, b9 ev ss0 54 64 92 a14, g13, g14 ev ss1 79 1 29 note 1 ev ss2 ? 42 70 n11, p11, p14 av ss0 6 7 35 e1, e2 av ss1 11 12 40 h1, h2 1 gnd ? av ss2 22 27 55 l4, m3, n2, p1 2 reset output reset 35 40 68 p9 3 si/rxd input sob0 39 48 76 n12 v dd0 30 35 63 n5, p5 v dd1 68 87 15 a7, b7 ev dd0 55 65 93 f13, f14 ev dd1 80 100 28 a3, b2 ev dd2 ? 41 69 n10, p10 av dd0 8 9 37 f1 av dd1 9 10 38 g1 av dd2 21 26 54 m1, m2 av refp0 7 8 36 f2 4 v dd ? av refp1 10 11 39 g2 5 so/txd output sib0 38 47 75 p12 6 v pp nc ? ? ? ? 7 sck output sckb0 40 49 77 m14 8 h/s input p43 41 50 78 m13 9 clk note 2 output x1 note 2 33 38 66 p8 10 vde nc ? ? ? ? 11 v dd2 ? nc ? ? ? ? 12 flmd1 output note 3 60 76 4 a12 13 rfu-1 nc ? ? ? ? 14 flmd0 output flmd0 37 46 74 n9 15 not used nc ? ? ? ? 16 not used nc ? ? ? ? notes 1. a1, b1, c1, c2, d3, and e4 2. in the v850e/if3 and v850e/ig3, external clock inpu t is prohibited. mount the resonator on board. 3. connect to flmd1 or gnd via a resistor. remark nc: no connection gc (v850e/if3): 80-pin plastic lqfp (14 14) gc (v850e/ig3): 100-pin plastic lqfp (fine pitch) (14 14) gf (v850e/ig3): 100-pin plastic lqfp (14 20) f1 (v850e/ig3): 161-pin plastic fbga (10 10)
chapter 27 flash memory user?s manual u18279ej3v0ud 1085 27.7 pin processing during flash memory programming when performing on-board programming, mount a connector on the target system to connect to the flash memory programmer. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset in the normal oper ation mode. therefore, because all the ports become high- impedance status, pin processing is requ ired when the external device does not acknowledge the high-impedance status. 27.7.1 power supply supply the same power supplies (v dd0 , v dd1 , v ss0 , v ss1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av ss0 , av ss1 , av ss2 , av refp0 , and av refp1 ) as in the normal operation mode. connect v dd and gnd of the flash memory programmer to v dd0 , v dd1 , v ss0 , v ss1 , ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only), av dd0 , av dd1 , av dd2 , av ss0 , av ss1 , av ss2 , av refp0 , and av refp1 . (v dd of the flash memory programmer is provid ed with a power supply monitoring function.) in the flash memory programming mode (including flash memory self programming), insert capacitors between v dd0 , v dd1 pins and v ss0 , v ss1 pins, and between ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only) pins and ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only) pins to stabilize the power supply voltage. 27.7.2 pins used the following shows the pins used by each interface. communication mode pins used uarta0 txd0, rxd0 csib0 sob0, sib0, sckb0 csib0 for handshake sob0, sib0, sckb0, p43 when connecting a flash memory programmer to an interface pin that is connected to other devices on-board, care should be taken to avoid a conflict of signals or the malfunction of other devices.
chapter 27 flash memory user?s manual u18279ej3v0ud 1086 (1) conflict of signals when the flash memory programmer (output) is connect ed to an interface pin (in put) that is connected to another device (output), a conflic t of signals occurs. to avoid the conf lict of signals, isolate the connection to the other device or set the other dev ice to the output high-impedance status. output pin other device flash memory programmer connection pin conflict of signals input pin in the flash memory programming mode, the signal that the flash memory programmer sends out conflicts wi th signals another device outputs. therefore, isolate the signals on the other device side. v850e/if3, v850e/ig3
chapter 27 flash memory user?s manual u18279ej3v0ud 1087 (2) malfunction of other device when the flash memory programmer (output or input) is co nnected to an interface pin (input or output) that is connected to another device (input), t he signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input si gnal to the other device is ignored. input pin other device flash memory programmer connection pin pin in the flash memory programming mode, if the signal that the v850e/if3, v850e/ig3 output affects the other device, isolate the signal on the other device side. v850e/if3, v850e/ig3 input pin other device flash memory programmer connection pin pin in the flash memory programming mode, if the signal that the flash memory programmer outputs affects the other device, isolate the signal on the other device side. v850e/if3, v850e/ig3
chapter 27 flash memory user?s manual u18279ej3v0ud 1088 27.7.3 reset pin when the reset signal of the flash memory programmer is connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not in put signals other than the reset signals from the flash memory programmer. output pin reset signal generator flash memory programmer connection pin conflict of signals reset in the flash memory programming mode, the signal that the reset signal generator outputs conflicts wi th the signal the flash memory programmer outputs. therefore, isolate the signals on the reset signal generator side. v850e/if3, v850e/ig3 27.7.4 flmd0 and flmd1 pins (1) flmd0 pin in the normal operation mode, input a voltage of ev ss0 , ev ss1 , or ev ss2 (v850e/ig3) level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only) level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the se lf programming mode, a voltage of ev dd0 , ev dd1 , or ev dd2 (v850e/ig3 only) level must be supplied to the fl md0 pin via port control, etc., before writing to the flash memory. for details, see 27.9.5 (1) flmd0 pin . v850e/if3, v850e/ig3 flmd0 flash memory programmer connection pin pull-down resistor (r flmd0 )
chapter 27 flash memory user?s manual u18279ej3v0ud 1089 (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when ev dd0 , ev dd1 , or ev dd2 (v850e/ig3 only) is supplied to the fl md0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. flmd1 pull-down resistor (r flmd1 ) other device v850e/if3, v850e/ig3 caution if the ev dd0 , ev dd1 , or ev dd2 (v850e/ig3 only) signal is input to the flmd1 pin from another device during on-board programming and immediat ely after reset, isolate this signal. table 27-8. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode ev dd 0 flash memory programming mode ev dd ev dd setting prohibited remark ev dd : ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only) 27.7.5 port pins when the flash memory programming mode is set, all the port pins except the pin that communicates with the flash memory programmer change to the high-impedance status. these port pins need not be processed. if problems such as disabling of the high-impedance status should occur to the external devices connected to the ports, connect them to ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only), or ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only) via resistors. 27.7.6 other signal pins connect x1 and x2 in the same status as in the normal operation mode.
chapter 27 flash memory user?s manual u18279ej3v0ud 1090 27.8 flash memory programming mode 27.8.1 flash memory control the following shows the procedure for manipulating the flash memory. start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode
chapter 27 flash memory user?s manual u18279ej3v0ud 1091 27.8.2 selection of communication mode in the v850e/if3 and v850e/ig3, the communication mode is selected by inputting pulses (11 pulses max.) to the flmd0 pin after switching to the flash memory program ming mode. the flmd0 pulse is generated by the flash memory programmer. the following shows the relationship between the number of pulses and the communication mode. v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) v ss ev dd ev ss ev dd ev ss ev dd ev ss ev dd ev ss ev dd ev ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uarta0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 v850e/if3 and v850e/ig3 perform slave operation, msb first 11 csib0 for handshake v850e/if3 and v850e/ig3 perform slave operation, msb first other rfu setting prohibited caution when uarta0 is selected , the receive clock is calculate d based on the reset command sent from the flash memory programme r after receiving the flmd0 pulse. remark v dd : v dd0 , v dd1 ev dd : ev dd0 , ev dd1 , ev dd2 (v850e/ig3 only) ev ss : ev ss0 , ev ss1 , ev ss2 (v850e/ig3 only)
chapter 27 flash memory user?s manual u18279ej3v0ud 1092 27.8.3 communication commands the v850e/if3 and v850e/ig3 communicate with a flas h memory programmer by means of commands. the commands sent from the flash memory programmer to t he v850e/if3 or v850e/ig3 are called ?commands?. the response signals sent from the v850e/if3 or v850e/ig3 to the flash memory programmer are called ?response commands?. v850e/if3, v850e/ig3 command response command flash memory programmer the following shows the commands for flash memory c ontrol in the v850e/if3 and v850e/ig3. all of these commands are issued from the dedicated flash memory programmer, and the v850e /if3 and v850e/ig3 perform the processing corresponding to the commands. table 27-9. flash memory control commands support classification command name uarta0 csib0 note function verify block verify command compares the contents of the specified block and the input data chip erase command erases the contents of the entire flash memory erase block erase command erases the specified block contents. blank check block blank check command checks the erase state of the specified block. data write write command writes data to the specified block. data read read command reads out data of the specified block. status command obtains the status of operations. oscillation frequency setting command sets the oscillation frequency. baud rate setting command changes the baud rate when uart0 is selected. silicon signature command reads out the silicon signature information. version acquisition command reads out the device version and firmware version. security setting command sets the security information and the boot block size. checksum command sends the checksum value of the specified block data. system setting and control reset command used for communication synchronization detecting. note csib0 for handshake
chapter 27 flash memory user?s manual u18279ej3v0ud 1093 the v850e/if3 and v850e/ig3 send back response commands for the commands issued from the flash memory programmer. the response commands sent from the v850e/if3 and v850e/ig3 are listed below. table 27-10. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal frame, etc. command number error acknowledges illegal command/data, etc. parameter error acknowledges illegal parameter, etc. checksum error acknowledges checksum of frame protect error acknowledges when protection is in effect during processing (busy) acknowledges during processing other than above error
chapter 27 flash memory user?s manual u18279ej3v0ud 1094 27.9 rewriting by self programming 27.9.1 overview the v850e/if3 and v850e/ig3 support a flash macro service t hat allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrite the flash memory with a user application progra m, the flash memory can be rewritten by a us er application transferred in advance to the internal ram or external memory. consequently, the user program can be upgraded and constant data note can be rewritten in the field. for details about self programming, see flash memory self programming library user?s manual . note be sure not to allocate the program code to the block w here the constant data of rewriting target is allocated. see 27.2 memory configuration for the block configuration. figure 27-2. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write
chapter 27 flash memory user?s manual u18279ej3v0ud 1095 27.9.2 features (1) flash memory self programming flash memory self programming is used to erase or write the flash memory by calling the flash function from a program stored in an area other than the flash memory area to be erased or written. to store the program that implements self programming in the area to be erased or written, copy the program to the internal ram area, execute the program at the copy dest ination, and call the flash function. to call the flash function, change t he mode from the normal operation mode to the self programming mode by using the flash programming mode control register. figure 27-3. self programming boot block cluster 256 kb 3ffffh 3ffffh 007ffh 0ffffh 1ffffh boot swap cluster (64 kb) boot swap cluster (64 kb) flmd0 pin high level input boot program (self program, communication driver, etc.) 00000h 00000h flash memory flash memory normal operation mode self programming mode : : : block 127 ( 2kb ) 10000h block 64 ( 2kb ) block 63 ( 2kb ) block 32 ( 2kb ) block 31 ( 2kb ) block 0 ( 2kb ) (a) boot swap cluster the contents of the boot swap cluster of the lower address side (00000h to 0ffffh) and the boot swap cluster of the higher address side (10000h to 1ffffh) can be interchanged while flash memory programming is performed. (b) boot block cluster by specifying the boot block cluster from 00000h in 2 kb units, the contents of the boot block cluster can be protected from rewriting.
chapter 27 flash memory user?s manual u18279ej3v0ud 1096 (2) interrupt support a user handler written to the flash memory cannot be used even if an interrupt occurred during flash function execution. therefore, in the v850e/if3 and v850e/ig3, to use an in terrupt during flash function execution, processing transits to the specific address note in the internal ram. allocate the ju mp instruction that transits processing to the user interrupt servicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses 27.9.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 27-4. standard self programming flow flash environment initialization processing erase processing write processing internal verify processing flash memory manipulation flash environment end processing end of processing all blocks end? ? disable accessing flash area ? disable stopping clock ? disable setting of an standby mode other than the halt mode ? disable dma transfer yes no
chapter 27 flash memory user?s manual u18279ej3v0ud 1097 27.9.4 flash functions table 27-11. flash function list type function name abbr. function initialize flashenv fle initializes flash control. erase flashblockerase flbe erases the specified block. write flashwordwrite flww successively writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. flashblockblankcheck flbbc checks the erase status of the specified block. flashblockiverify flbiv perform internal verify for the specified block. check flashflmdcheck flfc inputs flmd0 pin and checks flmd0 setting register value. obtain information flashgetinfo flgi reads out information about the flash memory. flashsetinfo flsi sets the flash information. flashbootswap flbs interchanges the contents of the boot swap cluster. setting flashwordread flwr reads out the data from the specified address. 27.9.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is executed. it is also necessary to apply a voltage of ev dd0 , ev dd1 , and ev dd2 (v850e/ig3 only) level to the flmd0 pin dur ing the self programming mode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 27-5. mode change timing reset signal flmd0 pin ev dd 0 v ev dd 0 v self programming mode normal operation mode normal operation mode remark ev dd : ev dd0 , ev dd1 , and ev dd2 (v850e/ig3 only) caution make sure that the flmd0 pin is at 0 v when reset is released.
chapter 27 flash memory user?s manual u18279ej3v0ud 1098 27.9.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 27-12. internal resources used resource name description stack area an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code note program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in the user application ex ecution status or flash function execution status. to use this interrupt in the flash function ex ecution status, since the processing transits to the address of the internal ram start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal ram start address + 4 addresses in advance. nmi interrupt can be used in the user application execution status or flash function execution status. to use this interrupt in the flash function ex ecution status, since the processing transits to the address of the internal ram start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal ram start address in advance. note about resources used, refer to the flash memory self-progra mming library user?s manual .
user?s manual u18279ej3v0ud 1099 chapter 28 electrical specifications 28.1 v850e/if3 28.1.1 absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v v ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v ev dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v ev ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v av dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v supply voltage av ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v v i1 note 1 ? 0.5 to ev dd + 0.5 note 2 v input voltage v i2 x1, x2 ? 0.5 to v ro + 0.35 v per pin 4 ma output current, low i ol all pins total of all pins 42 ma per pin ? 4 ma output current, high i oh all pins total of all pins ? 42 ma analog input voltage v ian p70/ani20 to p73/ani23, ani00 to ani05, ani10 to ani17 ? 0.5 to av dd + 0.5 note 2 v analog reference input voltage v iref av refp0 , av refp1 ? 0.5 to av dd + 0.5 note 2 v comparator reference input voltage v cref cref0l, cref1l, cref0f, cref1f ? 0.5 to av dd + 0.5 note 2 v in normal operating mode ? 40 to +85 c operating ambient temperature t a in flash memory programming mode ? 40 to +85 c operating ambient temperature t stg ? 40 to +125 c notes 1. p00, p01, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl9, reset, flmd0 2. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output pins (or i/o pins in the output state) of ic products to other output pins (including i/o pins in the out put state), power supply pins such as v dd and ev dd , or gnd pin. direct connection of the output pins be tween an ic product and an external circuit is possible, if the output pins can be set to the high-i mpedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and condit ions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark a = 0, 1 b = 0, 1 k = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1100 28.1.2 capacitance (t a = 25 c, v dd0 = v ss0 = v dd1 = v ss1 = ev dd0 = ev ss0 = ev dd1 = ev ss1 = av dd0 = av ss0 = av dd1 = av ss1 = av dd2 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i note 1 15 pf i/o capacitance c io fc = 1 mhz unmeasured pins returned to 0 v note 2 15 pf notes 1. ani00 to ani05, ani10 to ani17, reset 2. p00, p01, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p70 to p73, pdl0 to pdl9 cautions 1. excludes the flmd0, x1, and x2 pins. 2. in addition to input capaci tance, sampling capacitanc e is added to the ani 00 to ani05, ani10 to ani17, and ani20 to ani27 pins when sampling. 28.1.3 operating conditions (t a = ? 40 to +85 c, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit pll mode 32 64 mhz system clock frequency f xx clock through mode 4 8 mhz pll mode 4 64 mhz cpu clock frequency f cpu clock through mode 0.5 8 mhz v dd , ev dd voltage v dd , ev dd v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 3.5 5.5 v when a/d converters 0 to 2 are operating 4.0 5.5 v av dd voltage av dd when a/d converters 0 to 2 are not operating 3.5 5.5 v
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1101 28.1.4 clock oscilla tor charact eristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) 4 8 mhz after reset release 2 14 /f x ms ceramic /crystal resonator x2 x1 c1 c2 rd oscillation stabilization time after stop mode release note ms note the value varies depending on the setting of the osc illation stabilization time select register (osts). cautions 1. connect the oscillator as clo se to the x1 and x2 pins as possible. 2. do not cross the wiring with the other signal lin es in the area enclosed by the broken lines in the above figure. 3. for the resonator selection a nd oscillator constant, customers ar e requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 4. inputting an external clo ck to the v850e/if3 is prohibited. (i) murata mfg. co., ltd.: ceramic resonator (t a = ? 40 to +85 c) recommended circuit constant oscillation voltage range type part number oscillation frequency f x (mhz) c1 c2 rd (k ) min. (v) max. (v) cstls4m00g56-b0 4 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 cstls5m00g56-b0 5 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 lead cstls8m00g56-b0 8 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 cstcr4m00g55-r0 4 on chip (39 pf) on chip (39 pf) 0 3.5 5.5 cstcr5m00g55-r0 5 on chip (39 pf) on chip (39 pf) 0 3.5 5.5 surface mounting cstce8m00g55-r0 8 on chip (33 pf) on chip (33 pf) 0 3.5 5.5 caution these oscillator constants ar e reference values based on evaluati on under a specific environment by the resonator manufacturer. wh en optimization of the oscilla tor characteristics on the actual application is necessary, requ est evaluation on the mounting circuit from the resonator manufacturer. the oscillation voltage and oscilla tion frequency indicate only osc illator characteris tics, therefore use the v850e/if3 within the dc characteristics and ac charact eristics for internal operation conditions.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1102 28.1.5 regulator characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit input voltage v dd 3.5 5.5 v output voltage v ro 1.5 v output voltage stabilization time t reg stabilizing capacitor: c = 4.7 f note 1 1 note 2 ms notes 1. connect a stabilizing capacitor between the regc0 pin and v ss0 pin, and between the regc1 pin and v ss1 pin. 2. internal reset signal is output until the power-on- clear circuit (poc) output voltage stabilizes during t reg period. v dd v ro t reg
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1103 28.1.6 dc characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v input voltage, high v ih3 note 3 0.7av dd av dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v input voltage, low v il3 note 3 av ss 0.3av dd v i lih1 other than x1 5 a input leakage current, high i lih2 v i = note 4 x1 20 a i lil1 other than x1 ? 5 a input leakage current, low i lil2 v i = 0 v x1 ? 20 a output leakage current, high i loh v o = note 4 5 a output leakage current, low i lol v o = 0 v ? 5 a output voltage, high v oh1 note 5 i oh = ? 1.0 ma ev dd ? 1.0 v output voltage, low v ol1 note 5 i ol = 1.0 ma 0.4 v pull to up resistor r l1 10 30 100 k notes 1. p33, p36, p41, and pdl0 to pdl9 pins 2. p00, p01, p10 to p17, p20 to p27, p30 to p32, p 34, p35, p37, p40, p42 to p47, reset, and flmd0 pins 3. p70 to p73 pins 4. av dd0 = av dd1 = av dd2 = ev dd0 = ev dd1 5. p00, p01, p10 to p17, p20 to p27, p30 to p37, p40 to p47, and pdl0 to pdl9 pins remark the characteristics of alternate-function pins are the same as those of port pins.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1104 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v) (2/2) parameter symbol conditions min. typ. note 1 max. unit i dd1 normal operation 64 93 ma i dd2 halt mode 42 60 ma i dd3 f xx = 64 mhz idle mode 5 10 ma v dd supply current note 2 i dd4 stop mode 40 800 a notes 1. the typ. value is a reference value when v dd0 = v dd1 = 5.0 v and t a = 25 c. 2. the current consumed by the ev dd system (output buffer and pull-up resistor) and the operating currents of a/d converters 0 to 2, the operational amp lifier, and the comparator are not included.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1105 28.1.7 data retention characteristics stop mode (t a = ? 40 to +85 c, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode note 5.5 v data retention current i dddr v dd0 = v dd1 = v dddr 40 800 a supply voltage rise time t rvd 1 s supply voltage fall time t fvd 1 s supply voltage hold time (from stop mode setting) t hvd 0 ms data retention input voltage, high v ihdr all input ports 0.9v dddr v dddr v data retention input voltage, low v ildr all input ports ev ss 0.1v dddr v note when the low-voltage detector (lvi) reset mode is no t used (lvim.lvimd bit = 0): poc detection voltage (v poc0 ) when the low-voltage detector (lvi) reset mode is used (lvim.lvimd bit = 1): lvi detection voltage (v lvi0 /v lvi1 ) t hvd t fvd t rvd stop mode setting v dddr v ihdr v ihdr v ildr reset (input) all input ports (high level) all input ports (low level) v dd0 , v dd1 , ev dd0 , ev dd1 (operating voltage lower limit) 3.5 v
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1106 28.1.8 ac characteristics ac test input measurement points (p ins other than csib0 to csib2) av dd0 , av dd1 , av dd2 , ev dd0 , ev dd1 0 v v ih v il v ih v il measurement points ac test output measurement points (pins other than csib0 to csib2) v oh v ol v oh v ol ev dd0 , ev dd1 0 v measurement points ac test i/o measurement points (csib0 to csib2 pins) 1/2ev dd 1/2ev dd ev dd0 , ev dd1 0 v measurement points load conditions dut (device under measurement) c l = 50 pf caution if the load capacitan ce exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1107 (1) output signal timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit pdl0 to pdl9 8 ns output rise time t or <1> other than above 15 ns pdl0 to pdl9 8 ns output fall time t of <2> other than above 15 ns output signal <1> <2> (2) reset, external interrupt timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit power is on, stop mode is released 500 + t os ns reset low-level width t wrsl <3> other than above 500 ns reset high-level width t wrsh <4> 500 ns n = 00, 01, 08 to 13, 17, 18 (analog noise elimination) 500 ns intpn low-level width t witl <5> n = 14 to 16 (digital noise elimination) 4t smp ns n = 00, 01, 08 to 13, 17, 18 (analog noise elimination) 500 ns intpn high-level width t with <6> n = 14 to 16 (digital noise elimination) 4t smp ns remarks 1. t os : oscillation stabilization time t smp : noise elimination sampling clock cycle (set by intnfcn register) 2. after reset release, a 1 ms oscillation stabilization time is internally secured when the oscillation frequency (f x ) = 8 mhz. the oscillation stab ilization time is therefore (t os + 1) ms. after stop mode release, an oscillation stabilization time half the value se t to the osts register is internally secured. therefore, t os = 0 ns is acceptable if sufficient stabilizatio n time can be secured by the osts register setting.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1108 reset/interrupt reset (input) intpn (input) <4> <3> <6> <5> remark n = 00, 01, 08 to 18
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1109 (3) timer timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit n = b00 to b03, b10 to b13 12t + 10 ns tin high-level width notes 1, 2 t wtihn <7> n = a20, a21, a40, a41 3t smp1 + 10 ns n = b00 to b03, b10 to b13 12t + 10 ns tin low-level width notes 1, 2 t wtiln <8> n = a20, a21, a40, a41 3t smp1 + 10 ns evtbm high-level width note 1 t wevbhm <9> m = 0, 1 12t + 10 ns evtbm low-level width note 1 t wevblm <10> m = 0, 1 12t + 10 ns trgbm high-level width note 1 t wtrhm <11> m = 0, 1 12t + 10 ns trgbm low-level width note 1 t wtrlm <12> m = 0, 1 12t + 10 ns tenc10/tenc11 high-level width note 3 t wench1 <13> 3t smp2 + 10 ns tenc10/tenc11 low-level width note 3 t wencl1 <14> 3t smp2 + 10 ns tecr1 high-level width note 3 t wcrh1 <15> 3t smp2 + 10 ns tecr1 low-level width note 3 t wcrl1 <16> 3t smp2 + 10 ns tit10/tit11 high-level width note 3 t wtith1 <17> 3t smp2 + 10 ns tit10/tit11 low-level width note 3 t wtitl1 <18> 3t smp2 + 10 ns evtt1 high-level width note 3 t wevth1 <19> 3t smp2 + 10 ns evtt1 low-level width note 3 t wevtl1 <20> 3t smp2 + 10 ns tenc10/tenc11 input time differential note 3 t phud1 <21> 3t smp2 + 10 ns notes 1. t = 1/f xx 2. t smp1 : noise elimination sampling clock cycle (s et by tanfc2 and tanfc4 registers) 3. t smp2 : noise elimination sampling clo ck cycle (set by ttnfc1 register) remark the above specification shows a pulse width that is accurately detected as a valid edge. even if a pulse narrower than the above specification is input, t herefore, it may be detected as a valid edge.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1110 timer input timing tin (input) evtbm (input) trgbm (input) tit10 (input) tit11 (input) evtt1 (input) <7>/<9>/<11>/<17>/<19> <8>/<10>/<12>/<18>/<20> <15> <16> tenc10 (input) <13> <14> tenc11 (input) <13> <21> <21> <14> tecr1 (input) remark n = a20, a21, a40, a41, b00 to b03, b10 to b13 m = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1111 (4) csib timing (a) master mode (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle t kcym <22> 125 ns sckbn high-/low-level width t kwhm , t kwlm <23> t kcym /2 ? 10 ns sibn setup time (to sckbn ) 30 ns sibn setup time (to sckbn ) t ssim <24> 30 ns sibn hold time (from sckbn ) 30 ns sibn hold time (from sckbn ) t hsim <25> 30 ns sobn output delay time (from sckbn ) 30 ns sobn output delay time (from sckbn ) t dsom <26> 30 ns sobn output hold time (from sckbn ) t kcym /2 ? 10 ns sobn output hold time (from sckbn ) t hsom <27> t kcym /2 ? 10 ns remark n = 0 to 2 (b) slave mode (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle t kcys <28> 125 ns sckbn high-/low-level width t kwhs , t kwls <29> t kcys /2 ? 10 ns sibn setup time (to sckbn ) 30 ns sibn setup time (to sckbn ) t ssis <30> 30 ns sibn hold time (from sckbn ) 30 ns sibn hold time (from sckbn ) t hsis <31> 30 ns sobn output delay time (from sckbn ) 30 ns sobn output delay time (from sckbn ) t dsos <32> 30 ns sobn output hold time (from sckbn ) t kcys /2 ? 10 ns sobn output hold time (from sckbn ) t hsos <33> t kcys /2 ? 10 ns remark n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1112 csib timing when cbnckp and cbndap bits of cbnctl1 register = 00 <22>, <28> <23>, <29> <23>, <29> <25>, <31> <24>, <30> <26>, <32> <27>, <33> sibn (input) sobn (output) sckbn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 csib timing when cbnckp and cbndap bits of cbnctl1 register = 01 <24>, <30> <25>, <31> <27>, <33> sibn (input) sobn (output) input data output data <22>, <28> <23>, <29> <23>, <29> sckbn (i/o) <26>, <32> remarks 1. broken lines indicate high impedance. 2. n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1113 csib timing when cbnckp and cbndap bits of cbnctl1 register = 10 <22>, <28> <23>, <29> <23>, <29> <24>, <30> <25>, <31> <26>, <32> <27>, <33> sibn (input) sobn (output) sckbn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 csib timing when cbnckp and cbndap bits of cbnctl1 register = 11 <24>, <30> <25>, <31> <27>, <33> sibn (input) sobn (output) input data output data <22>, <28> <23>, <29> <23>, <29> sckbn (i/o) <26>, <32> remarks 1. broken lines indicate high impedance. 2. n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1114 (5) i 2 c bus timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) standard mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk ? 0 100 0 400 khz bus free time (between stop condition and start condition) t buf <34> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <35> 4.0 ? 0.6 ? s scl clock low-level width t low <36> 4.7 ? 1.3 ? s scl clock high-level width t high <37> 4.0 ? 0.6 ? s start/restart condition setup time t su:sta <38> 4.7 ? 0.6 ? s cbus-compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <39> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <40> 250 ? 100 note 4 ? ns sda, scl signal rise time t r <41> ? 1000 20 + 0.1cb note 5 300 ns sda, scl signal fall time t f <42> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <43> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <44> ? ? 0 50 ns each bus line capacitive load cb ? ? 400 ? 400 pf notes 1. the first clock pulse is generated after a hold time during the start condition. 2. the system must internally supply a hold time of at least 300 ns for the sda signal (at v ihmin . of scl signal) to fill the undefined area at the falling edge of scl. 3. if the system does not extend the low hold time (t low ) of the scl signal, the maximum data hold time (t hd:dat ) must be satisfied. 4. the high-speed mode i 2 c bus can be used in the standard mode i 2 c bus system. in this case, make sure that the following conditions are satisfied. ? if system does not extend the low status hold time of the scl signal t su: dat 250 ns ? if system extends the low status hold time of scl signal sends the next data bit to the sda line before the scl line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns: standard mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1115 i 2 c bus timing stop condition start condition restart condition stop condition sda (i/o) <37> <36> <34> <41> <42> <35> <41> <39> <40> <38> <35> <44> <43> <42> scl (i/o) (6) high-impedance control timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit oscillation stop timer output high impedance t clm when clock monitor is operating 65 s input to tobnoff timer output high impedance t htqn 300 ns input to toa2off timer output high impedance t htp2 300 ns input to ani00/ani05 timer output high impedance t ani0 10 s input to ani10/ani15 to ani12/ani17 timer output high impedance t ani1 10 s remark n = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1116 28.1.9 characteristics of a/d converters 0 and 1 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = av refp0 = av refp1 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 12 12 12 bit overall error note 1 10 lsb f ad01 = 16 mhz, adanctc register = 0bh or 0ch 2.0 s conversion time t conv f ad01 = 12 mhz, adanctc register = 00h 7.42 s zero scale error note 1 10 lsb full-scale error note 1 10 lsb integral linearity error note 1 4 lsb differential linearity error note 1 2.5 lsb analog reference voltage av dd 4.0 5.5 v analog input voltage v ian av ss av dd v ai dd operating 4.5 7.5 ma av dd supply current note 2 ai dds in stop mode note 3 3.5 17.5 s notes 1. excludes quantization error ( 0.5 lsb). 2. this value is for only one a/d converter (a/d converter 0 or 1). 3. stop the operation of a/d converters 0 and 1 (adn scm.adnce bit = 0) before setting stop mode. remarks 1. lsb: least significant bit 2. f ad01 : base clock of a/d converters 0 and 1 3. n = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1117 28.1.10 characteristics of a/d converter 2 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 4.0 lsb conversion time t conv 3.88 10 s zero scale error note 1 4.0 lsb full-scale error note 1 4.0 lsb integral linearity error note 1 4.0 lsb differential linearity error note 1 2.0 lsb analog reference voltage av dd 4.0 5.5 v analog input voltage v ian av ss av dd v ai dd during operation 3.5 7 ma av dd supply current ai dds in stop mode note 2 1 10 a notes 1. excludes quantization error ( 0.5 lsb). 2. stop the operation of a/d converter 2 (ad2m0 .ad2ce bit = 0) before setting stop mode. remark lsb: least significant bit
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1118 28.1.11 operational amp lifier characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit input offset voltage v io 9.0 mv gain = 2.500 0.04av dd 0.36av dd v gain = 5.000 0.02av dd 0.18av dd v input voltage range v i gain = 10.00 0.01av dd 0.085av dd v slew rate note 1 s r 10 15 v/ s gain = 2.500 to 4.444 1.0 1.3 % gain = 5.000 to 6.667 1.0 1.5 % note 2 gain = 8.000, 10.00 1.0 1.7 % gain = 2.500 to 4.444 1.0 2.0 % gain = 5.000 to 6.667 1.0 2.1 % gain error note 3 gain = 8.000, 10.00 1.0 2.2 % i opdd during operation 1.8 2.6 ma operating current note 4 a idds in stop mode note 5 1.0 10 a notes 1. inclination characteristic of output voltage from 10% to 90% 2. av dd0 = av dd1 = 4.5 to 5.5 v 3. av dd0 = av dd1 = 4.0 to 5.5 v 4. four operational amplifiers are provided in total. the value shows the operating current per operational amplifier. 5. stop operational amplif ier operation (op0ctl0.op0en bit = 0, op1ctl0.op12en, op11en, and op10en bits = 0)) before setting stop mode. remark power supplies av dd0 and av dd1 are used for the operational amplifier.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1119 28.1.12 comparator characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit input offset voltage v io 3.0 mv input voltage range v i av ss av dd v comparator reference voltage (full range) crefnf 0.02av dd + 0.1 0.92av dd ? 0.1 v comparator reference voltage (low range) crefnl 0.02av dd + 0.1 0.5av dd ? 0.1 v t cr input amplitude = 100 mv, at rising edge note 1 1.0 s response time t cf input amplitude = 100 mv, at falling edge note 2 1.0 s i cpdd during operation 250 a operating current note 3 a idds in stop mode note 4 2.0 20 na notes 1. characteristics of pulse response when anim input changes from the comparator reference voltage ? 100 mv to the comparator reference voltage + 100 mv 2. characteristics of pulse response when anim input changes from the comparat or reference voltage + 100 mv to the comparator reference voltage ? 100 mv 3. four comparators are provided in total. t he value shows the operating current per comparator. 4. stop comparator operation (cmpnctl0 re gister = 00h) before setting stop mode. remarks 1. power supplies for the comparators are av dd0 and av dd1 . 2. m = 05, 15 to 17 n = 0, 1 comparator characteristics output voltage v o input voltage v in comparator ref. voltage ? 100 mv 0 v 5 v +100 mv t cr t cf
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1120 28.1.13 power-on-clear circuit (poc) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit poc detection voltage v poc0 3.5 3.7 3.9 v supply voltage rise time t pth <45> v dd0 , v dd1 = 0 to 3.5 v 2.5 s 1.8 s response time 1 note 1 t pthd <46> after v dd0 and v dd1 reach 3.9 v on power application 3.0 ms response time 2 note 2 t pd <47> after v dd0 and v dd1 drop to 3.5 v on power off 1.0 ms minimum width of v dd0 , v dd1 t pw <48> 0.2 ms notes 1. the time required to release a reset signal (po cres) after the poc detection voltage is detected. 2. the time required to output a reset signal (po cres) after the poc detection voltage is detected. supply voltage (v dd0 , v dd1 ) poc detection voltage (max.) poc detection voltage (typ.) poc detection voltage (min.) <45> <46> <47> <46> <48> time
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1121 28.1.14 low-voltage detector (lvi) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lv i 0 lvis.lvis0 bit = 0 4.2 4.4 4.6 v lvi detection voltage v lv i 1 lvis.lvis0 bit = 1 4.0 4.2 4.4 v response time 1 note t ld <49> after v dd0 and v dd1 reach v lvi 0 /v lv i 1 (max.) or drop to v lv i 0 /v lv i 1 (min.) 0.2 2.0 ms minimum width of v dd0 , v dd1 t lw <50> 0.2 ms reference voltage stabilization wait time t lwait <51> after v dd0 and v dd1 reach poc detection voltage (min.) and the lvim.lvion bit is changed from 0 to 1 0.1 ms note the time required to output an interrupt request signal (intlvil, intlvih) or intern al reset signal (lvires) after the lvi detection voltage is detected. supply voltage (v dd0 , v dd1 ) lvi detection voltage (max.) lvi detection voltage (typ.) lvi detection voltage (min.) poc detection voltage (min.) <50> <49> <49> time <51> lvion bit = 0 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1122 28.1.15 flash memory progr amming characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit rewrite count c erwr note 100 times note rewrite as follows. example when three rewrites: shipped product e p e p e p (p: write, e: erase)
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1123 28.2 v850e/ig3 28.2.1 absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v v ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v ev dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v ev ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v av dd v dda = ev ddb = av ddk ? 0.5 to +6.5 v supply voltage av ss v ssa = ev ssb = av ssk ? 0.5 to +0.5 v v i1 note 1 ? 0.5 to ev dd + 0.5 note 2 v input voltage v i2 x1, x2 ? 0.5 to v ro + 0.35 v per pin 4 ma output current, low i ol all pins total of all pins 63 ma per pin ? 4 ma output current, high i oh all pins total of all pins ? 63 ma analog input voltage v ian p70/ani20 to p77/ani27, ani00 to ani05, ani10 to ani17 ? 0.5 to av dd + 0.5 note 2 v analog reference input voltage v iref av refp0 , av refp1 ? 0.5 to av dd + 0.5 note 2 v comparator reference input voltage v cref cref0l, cref1l, cref0f, cref1f ? 0.5 to av dd + 0.5 note 2 v in normal operating mode ? 40 to +85 c operating ambient temperature t a in flash memory programming mode ? 40 to +85 c operating ambient temperature t stg ? 40 to +125 c notes 1. p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl15, reset, flmd0, drst 2. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output pins (or i/o pins in the output state) of ic products to other output pins (including i/o pins in the out put state), power supply pins such as v dd and ev dd , or gnd pin. direct connection of the output pins be tween an ic product and an external circuit is possible, if the output pins can be set to the high-i mpedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and condit ions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark a = 0, 1 b = 0 to 2 k = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1124 28.2.2 capacitance (t a = 25 c, v dd0 = v ss0 = v dd1 = v ss1 = ev dd0 = ev ss0 = ev dd1 = ev ss1 = ev dd2 = ev ss2 = av dd0 = av ss0 = av dd1 = av ss1 = av dd2 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i note 1 15 pf i/o capacitance c io note 2 15 pf output capacitance c o fc = 1 mhz unmeasured pins returned to 0 v note 3 15 pf notes 1. ani00 to ani05, ani10 to ani17, reset 2. p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p70 to p77, pdl0 to pdl15 3. ddo cautions 1. excludes the flm d0, drst, x1, and x2 pins. 2. in addition to input capaci tance, sampling capacitanc e is added to the ani 00 to ani05, ani10 to ani17, and ani20 to ani27 pins when sampling. 28.2.3 operating conditions (t a = ? 40 to +85 c, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit pll mode 32 64 mhz system clock frequency f xx clock through mode 4 8 mhz pll mode 4 64 mhz cpu clock frequency f cpu clock through mode 0.5 8 mhz when external bus is not used 3.5 5.5 v v dd , ev dd voltage v dd , ev dd note 1 when external bus is used note 2 4.0 5.5 v when a/d converters 0 to 2 are operating 4.0 5.5 v av dd voltage av dd when a/d converters 0 to 2 are not operating 3.5 5.5 v notes 1. v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 2. pd70f3454gc-8ea-a and 70f3454f1-da9-a only
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1125 28.2.4 clock oscilla tor charact eristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) 4 8 mhz after reset release 2 14 /f x ms ceramic /crystal resonator x2 x1 c1 c2 rd oscillation stabilization time after stop mode release note ms note the value varies depending on the setting of the osc illation stabilization time select register (osts). cautions 1. connect the oscillator as clo se to the x1 and x2 pins as possible. 2. do not cross the wiring with the other signal lin es in the area enclosed by the broken lines in the above figure. 3. for the resonator selection a nd oscillator constant, customers ar e requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 4. inputting an external clo ck to the v850e/ig3 is prohibited. (i) murata mfg. co., ltd.: ceramic resonator (t a = ? 40 to +85 c) (products other than pd70f3454f1-da9-a) recommended circuit constant oscillation voltage range type part number oscillation frequency f x (mhz) c1 c2 rd (k ) min. (v) max. (v) cstls4m00g56-b0 4 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 cstls5m00g56-b0 5 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 lead cstls8m00g56-b0 8 on chip (47 pf) on chip (47 pf) 0 3.5 5.5 cstcr4m00g55-r0 4 on chip (39 pf) on chip (39 pf) 0 3.5 5.5 cstcr5m00g55-r0 5 on chip (39 pf) on chip (39 pf) 0 3.5 5.5 surface mounting cstce8m00g55-r0 8 on chip (33 pf) on chip (33 pf) 0 3.5 5.5 caution these oscillator constants ar e reference values based on evaluati on under a specific environment by the resonator manufacturer. wh en optimization of the oscilla tor characteristics on the actual application is necessary, requ est evaluation on the mounting circuit from the resonator manufacturer. the oscillation voltage and oscilla tion frequency indicate only osc illator characteris tics, therefore use the v850e/ig3 within the dc characteristics and ac character istics for internal operation conditions.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1126 28.2.5 regulator characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = 0 v) parameter symbol conditions min. typ. max. unit input voltage v dd 3.5 5.5 v output voltage v ro 1.5 v output voltage stabilization time t reg stabilizing capacitor c = 4.7 f note 1 1 note 2 ms notes 1. connect a stabilizing capacitor between the regc0 pin and v ss0 pin, and between the regc1 pin and v ss1 pin. 2. internal reset signal is output until the power-on- clear circuit (poc) output voltage stabilizes during t reg period. v dd v ro t reg
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1127 28.2.6 dc characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 note 3 2.2 ev dd v input voltage, high v ih4 note 4 0.7av dd av dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 note 3 ev ss 0.8 v input voltage, low v il4 note 4 av ss 0.3av dd v i lih1 other than x1 5 a input leakage current, high i lih2 v i = note 5 , note 6 x1 20 a i lil1 other than x1 ? 5 a input leakage current, low i lil2 v i = 0 v x1 ? 20 a output leakage current, high i loh v o = note 5 5 a output leakage current, low i lol v o = 0 v ? 5 a output voltage, high v oh1 note 7 i oh = ? 1.0 ma total of pins = ? 57 ma ev dd ? 1.0 v output voltage, low v ol1 note 7 i ol = 1.0 ma total of pins = 57 ma 0.4 v pull-up resistor r l1 10 30 100 k pull-down resistor note 8 r l2 10 30 100 k notes 1. p33, p36, p41, and pdl0 to pdl15 pins 2. p00 to p07, p10 to p17, p20 to p27, p30 to p32, p34, p35, p37, p40, p42 to p47, reset, and flmd0 pins 3. drst, ddi, dck, and dms pins 4. p70 to p77 pins 5. av dd0 = av dd1 = av dd2 = ev dd0 = ev dd1 = ev dd2 6. except for drst pin 7. p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, pdl0 to pdl15, and ddo pins 8. drst pin only remark the characteristics of alternate-function pins are the same as those of port pins.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1128 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v) (2/2) parameter symbol conditions min. typ. note 1 max. unit i dd1 normal operation 64 93 ma i dd2 halt mode 42 60 ma i dd3 f xx = 64 mhz idle mode 5 10 ma v dd supply current note 2 i dd4 stop mode 40 800 a notes 1. the typ. value is a reference value when v dd0 = v dd1 = 5.0 v and t a = 25 c. 2. the current consumed by the ev dd system (output buffer and pull-up resistor) and the operating currents of a/d converters 0 to 2, the operational amp lifier, and the comparator are not included.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1129 28.2.7 data retention characteristics stop mode (t a = ? 40 to +85 c, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode note 5.5 v data retention current i dddr v dd0 = v dd1 = v dddr 40 800 a supply voltage rise time t rvd 1 s supply voltage fall time t fvd 1 s supply voltage retention time (from stop mode setting) t hvd 0 ms data retention input voltage, high v ihdr all input ports 0.9v dddr v dddr v data retention input voltage, low v ildr all input ports ev ss 0.1v dddr v note when the low-voltage detector (lvi) reset mode is no t used (lvim.lvimd bit = 0): poc detection voltage (v poc0 ) when the low-voltage detector (lvi) reset mode is used (lvim.lvimd bit = 1): lvi detection voltage (v lvi0 /v lvi1 ) t hvd t fvd t rvd stop mode setting v dddr v ihdr v ihdr v ildr reset (input) all input ports (high level) all input ports (low level) v dd0 , v dd1 , ev dd0 , ev dd1 , ev dd2 (operating voltage lower limit) 3.5 v
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1130 28.2.8 ac characteristics ac test input measurement points (external bus ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only), pins other than csib0 to csib2) av dd0 , av dd1 , av dd2 , ev dd0 , ev dd1 , ev dd2 0 v v ih v il v ih v il measurement points ac test output measurement points (external bus ( pd70f3454gc-8ea-a and 70f3454f1- da9-a only), pins other than csib0 to csib2) v oh v ol v oh v ol ev dd0 , ev dd1 , ev dd2 0 v measurement points ac test i/o measurement points (external bus ( pd70f3454gc-8ea-a and 70f3454f 1-da9-a only), csib0 to csib2 pins) 1/2ev dd 1/2ev dd ev dd0 , ev dd1 , ev dd2 0 v measurement points load conditions dut (device under measurement) c l = 50 pf caution if the load capacitan ce exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1131 (1) output signal timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit p07, pdl0 to pdl15, ddo 8 ns output rise time t or <1> other than above 15 ns p07, pdl0 to pdl15, ddo 8 ns output fall time t of <2> other than above 15 ns output signal <1> <2> (2) reset, external interrupt timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit power is on, stop mode is released 500 + t os ns reset low-level width t wrsl <3> other than above 500 ns reset high-level width t wrsh <4> 500 ns n = 00 to 13, 17, 18 (analog noise elimination) 500 ns intpn low-level width t witl <5> n = 14 to 16 (digital noise elimination) 4t smp ns n = 00 to 13, 17, 18 (analog noise elimination) 500 ns intpn high-level width t with <6> n = 14 to 16 (digital noise elimination) 4t smp ns remarks 1. t os : oscillation stabilization time t smp : noise elimination sampling clock cycle (set by intnfcn register) 2. after reset release, a 1 ms oscillation stabilization time is internally secured when the oscillation frequency (f x ) = 8 mhz. the oscillation stab ilization time is therefore (t os + 1) ms. after stop mode release, an oscillation stabilization time half the value se t to the osts register is internally secured. therefore, t os = 0 ns is acceptable if sufficient stabilizatio n time can be secured by the osts register setting.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1132 reset/interrupt reset (input) intpn (input) <4> <3> <6> <5> remark n = 00 to 18 (3) clkout output timing ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <7> 31.25 ns 8 s low-level width t wkh <8> t cyk /2 ? 6.2 ns high-level width t wkl <9> t cyk /2 ? 6.2 ns clkout (output) <9> <7> <8>
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1133 (4) bus timing ( pd70f3454gc-8ea-a and 70f3454f1-da9-a only) (a) read cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from address to astb t dast2 <10> (0.5 + w as ) t ? 20 ns astb high-level width t wsth <11> (1 + w as + i) t ? 17 ns address hold time from astb t hsta <12> (0.5 + w ah ) t ? 19 ns address hold time from rd t hrda2 <13> (1 + i) t ? 29 ns delay time from address to rd t dard2 <14> (1 + w as + w ah ) t ? 36 ns delay time from rd to address float t frda <15> 16 ns data input setup time from address t daid2 <16> (2 + w d + w + w as + w ah ) t ? 37 ns data input setup time from astb t dstid <17> (1.5 + w d + w + w ah ) t ? 37 ns data input setup time from rd t drdid2 <18> (1 + w d + w) t ? 37 ns delay time from astb to rd t dstrd3 <19> (0.5 + w ah ) t ? 16 ns data input hold time (from rd ) t hrdid2 <20> 2 ns delay time from rd to bus output t drdod2 <21> (1 + i) t ? 19 ns delay time from rd to astb t drdst <22> 0.5t ? 16 ns rd low-level width t wrdl2 <23> (1 + w d + w) t ? 20 ns rd high-level width t wrdh2 <24> (2 + i + w as + w ah ) t ? 20 ns high-level hold time from rd to wrn t hrdwr2 <25> (2 + i + w as + w ah ) t ? 20 ns wait setup time (to address ) t dawt2 <26> (1.5 + w d + w + w as + w ah ) t ? 45 ns wait hold time (from address ) t hawt2 <27> (1.5 + w d + w + w as + w ah ) t ? 1 ns wait setup time (to astb ) t dstwt <28> (1 + w d + w + w ah ) t ? 37 ns wait hold time (from astb ) t hstwt <29> (1 + w d + w + w ah ) t + 2 ns wait setup time (to rd ) t drdwt2 <30> (0.5 + w d + w) t ? 37 ns wait hold time (from rd ) t hrdwt2 <31> (0.5 + w d + w) t + 2 ns cautions 1. set t in accordan ce with the follo wing condition. 31.25 ns t 2. be sure to insert the addres s setup waits and address hold waits. remarks 1. w as : number of address setup waits by the awc register w ah : number of address hold waits by the awc register w d : number of data waits by the dwc0 register w: number of external waits by the wait pin 2. t = 1/f cpu (f cpu : cpu clock frequency) 3. n = 0, 1 4. i: number of idle states
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1134 read cycle (clkout asynchronous) <13> <10> <12> <20> clkout (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) wr0, wr1 (output) a0 to a7 (output) cs0, cs1 (output) <16> <27> <26> <29> <28> <18> <22> <14> <15> <30> <31> <25> <19> <24> <23> <21> <17> <11> t3 tasw t1 tahw t2 twdw twwt t3 ti t1 remark the above timing chart shows the timing when the num ber of address setup waits is 1, number of address hold waits is 1, number of data waits is 1, number of waits by wait pin is 1 (when an active level (low level) is input for one cycle during the det ermined wait period), and num ber of idle states is 1.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1135 (b) read cycle (clkout synchronous) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka2 <32> 22 ns address hold time from clkout t hka2 <33> ? 5 ns address hold time from clkout t hka3 <34> ? 8 ns delay time from clkout to address float t fka <35> 15 ns data input setup time (to clkout ) t sidk2 <36> 30 ns data input hold time (from clkout ) t hkid2 <37> 9 ns delay time from clkout to astb t dkst3 <38> ? 8 18 ns delay time from clkout to astb t dkst4 <39> ? 8 18 ns delay time from clkout to rd t dkrd3 <40> ? 10 17 ns delay time from clkout to rd t dkrd4 <41> ? 10 17 ns wait setup time (to clkout ) t swtk2 <42> 30 ns wait hold time (from clkout ) t hkwt2 <43> 9 ns caution be sure to insert the addr ess setup waits and address hold waits.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1136 read cycle (clkout synchronous) <35> clkout (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) wr0, wr1 (output) a0 to a7 (output) cs0, cs1 (output) <34> <36> <37> <42> <43> <40> <41> <39> <38> t3 tasw t1 tahw t2 twdw twwt t3 ti t1 <32> <33> remark the above timing chart shows the timing when the num ber of address setup waits is 1, number of address hold waits is 1, number of data waits is 1, number of waits by wait pin is 1 (when an active level (low level) is input for one cycle during the det ermined wait period), and num ber of idle states is 1.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1137 (c) write cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from address to astb t dast2 <10> (0.5 + w as ) t ? 20 ns astb high-level width t wsth <11> (1 + w as + i) t ? 16 ns address hold time from astb t hsta <12> (0.5 + w ah ) t ? 19 ns address hold time from wrn t hwra2 <44> t ? 19 ns delay time from address to wrn t dawr2 <45> (1 + w as + w ah ) t ? 36 ns delay time from wrn to data output t dwrod3 <46> 15 ns delay time from astb to wrn t dstwr3 <47> (0.5 + w ah ) t ? 16 ns delay time from data output to wrn t dodwr2 <48> (1 + w d + w) t ? 25 ns data output hold time from wrn t hwrod2 <49> t ? 19 ns delay time from wrn to astb t dwrst <50> 0.5t ? 16 ns wrn low-level width t wwrl2 <51> (1 + w d + w) t ? 20 ns wrn high-level width t wwrh2 <52> (2 + w as + w ah ) t ? 20 ns high-level hold time from wrn to rd t hwrrd2 <53> (2 + w as + w ah ) t ? 20 ns wait setup time (to address ) t dawt2 <26> (1.5 + w d + w + w as + w ah ) t ? 45 ns wait hold time (from address ) t hawt2 <27> (1.5 + w d + w + w as + w ah ) t ? 1 ns wait setup time (to astb ) t dstwt <28> (1 + w d + w + w ah ) t ? 37 ns wait hold time (from astb ) t hstwt <29> (1 + w d + w + w ah ) t + 2 ns wait setup time (to wrn ) t dwrwt2 <54> (0.5 + w d + w) t ? 37 ns wait hold time (from wrn ) t hwrwt2 <55> (0.5 + w d + w) t + 2 ns cautions 1. set t in accordan ce with the follo wing condition. 31.25 ns t 2. be sure to insert the addres s setup waits and address hold waits. remarks 1. w as : number of address setup waits by the awc register w ah : number of address hold waits by the awc register w d : number of data waits by the dwc0 register w: number of external waits by the wait pin 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n = 0, 1 4. i: number of idle states
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1138 write cycle (clkout asynchronous) <44> <10> <12> <48> <49> clkout (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) wr0, wr1 (output) a0 to a7 (output) cs0, cs1 (output) <27> <26> <29> <28> <50> <46> <54> <55> <52> <51> <11> t3 tasw t1 tahw t2 twdw twwt t3 t1 <47> <53> <45> remark the above timing chart shows the timing when the num ber of address setup waits is 1, number of address hold waits is 1, number of data waits is 1, and number of waits by wait pin is 1 (when an active level (low level) is input for one cycle during the determined wait period).
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1139 (d) write cycle (clkout synchronous) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka2 <32> 22 ns address hold time from clkout t hka2 <33> ? 5 ns address hold time from clkout t hka3 <34> ? 8 ns delay time from clkout to astb t dkst3 <38> ? 8 18 ns delay time from clkout to astb t dkst4 <39> ? 8 18 ns delay time from clkout to data output t dkod3 <56> 22 ns data output hold time from clkout t hkod2 <57> ? 9 ns delay time from clkout to wrn t dkwr3 <58> ? 10 17 ns delay time from clkout to wrn t dkwr4 <59> ? 10 17 ns wait setup time (to clkout ) t swtk2 <42> 30 ns wait hold time (from clkout ) t hkwt2 <43> 9 ns caution be sure to insert the addr ess setup waits and address hold waits. remark n = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1140 write cycle (clkout synchronous) <56> clkout (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) wr0, wr1 (output) a0 to a7 (output) cs0, cs1 (output) <34> <57> <42> <43> <39> <38> t3 tasw t1 tahw t2 twdw twwt t3 t1 <32> <33> <59> <58> remark the above timing chart shows the timing when the num ber of address setup waits is 1, number of address hold waits is 1, number of data waits is 1, and number of waits by wait pin is 1 (when an active level (low level) is input for one cycle during the determined wait period).
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1141 (5) timer timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit n = b00 to b03, b10 to b13 12t + 10 ns tin high-level width notes 1, 2 t wtihn <60> n = a20, a21, a30, a31, a40, a41 3t smp1 + 10 ns n = b00 to b03, b10 to b13 12t + 10 ns tin low-level width notes 1, 2 t wtiln <61> n = a20, a21, a30, a31, a40, a41 3t smp1 + 10 ns evtbm high-level width note 1 t wevbhm <62> m = 0, 1 12t + 10 ns evtbm low-level width note 1 t wevblm <63> m = 0, 1 12t + 10 ns trgbm high-level width note 1 t wtrhm <64> m = 0, 1 12t + 10 ns trgbm low-level width note 1 t wtrlm <65> m = 0, 1 12t + 10 ns tencm0/tencm1 high-level width note 3 t wenchm <66> m = 0, 1 3t smp2 + 10 ns tencm0/tencm1 low-level width note 3 t wenclm <67> m = 0, 1 3t smp2 + 10 ns tecrm high-level width note 3 t wcrhm <68> m = 0, 1 3t smp2 + 10 ns tecrm low-level width note 3 t wcrlm <69> m = 0, 1 3t smp2 + 10 ns titm0/titm1 high-level width note 3 t wtithm <70> m = 0, 1 3t smp2 + 10 ns titm0/titm1 low-level width note 3 t wtitlm <71> m = 0, 1 3t smp2 + 10 ns evttm high-level width note 3 t wevthm <72> m = 0, 1 3t smp2 + 10 ns evttm low-level width note 3 t wevtlm <73> m = 0, 1 3t smp2 + 10 ns tencm0/tencm1 input time differential note 3 t phudm <74> m = 0, 1 3t smp2 + 10 ns notes 1. t = 1/f xx 2. t smp1 : noise elimination sampling clock cycle (s et by tanfc2 to tanfc4 registers) 3. t smp2 : noise elimination sampling clock cycle (set by ttnfc0 and ttnfc1 registers) remark the above specification shows a pulse width that is accurately detected as a valid edge. even if a pulse narrower than the above specification is input, t herefore, it may be detected as a valid edge.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1142 timer input timing tin (input) evtbm (input) trgbm (input) titm0 (input) titm1 (input) evttm (input) <60>/<62>/<64>/<70>/<72> <61>/<63>/<65>/<71>/<73> <68> <69> tencm0 (input) <66> <67> tencm1 (input) <66> <74> <74> <67> tecrm (input) remark n = a20, a21, a30, a31, a40, a41, b00 to b03, b10 to b13 m = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1143 (6) csib timing (a) master mode (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle t kcym <75> 125 ns sckbn high-/low-level width t kwhm , t kwlm <76> t kcym /2 ? 10 ns sibn setup time (to sckbn ) 30 ns sibn setup time (to sckbn ) t ssim <77> 30 ns sibn hold time (from sckbn ) 30 ns sibn hold time (from sckbn ) t hsim <78> 30 ns sobn output delay time (from sckbn ) 30 ns sobn output delay time (from sckbn ) t dsom <79> 30 ns sobn output hold time (from sckbn ) t kcym /2 ? 10 ns sobn output hold time (from sckbn ) t hsom <80> t kcym /2 ? 10 ns remark n = 0 to 2 (b) slave mode (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle t kcys <81> 125 ns sckbn high-/low-level width t kwhs , t kwls <82> t kcys /2 ? 10 ns sibn setup time (to sckbn ) 30 ns sibn setup time (to sckbn ) t ssis <83> 30 ns sibn hold time (from sckbn ) 30 ns sibn hold time (from sckbn ) t hsis <84> 30 ns sobn output delay time (from sckbn ) 30 ns sobn output delay time (from sckbn ) t dsos <85> 30 ns sobn output hold time (from sckbn ) t kcys /2 ? 10 ns sobn output hold time (from sckbn ) t hsos <86> t kcys /2 ? 10 ns remark n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1144 csib timing when cbnckp and cbndap bits of cbnctl1 register = 00 <75>, <81> <76>, <82> <76>, <82> <78>, <84> <77>, <83> <79>, <85> <80>, <86> sibn (input) sobn (output) sckbn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 csib timing when cbnckp and cbndap bits of cbnctl1 register = 01 <77>, <83> <78>, <84> <80>, <86> sibn (input) sobn (output) input data output data <75>, <81> <76>, <82> <76>, <82> sckbn (i/o) <79>, <85> remarks 1. broken lines indicate high impedance. 2. n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1145 csib timing when cbnckp and cbndap bits of cbnctl1 register = 10 <75>, <81> <76>, <82> <76>, <82> <77>, <83> <78>, <84> <79>, <85> <80>, <86> sibn (input) sobn (output) sckbn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 csib timing when cbnckp and cbndap bits of cbnctl1 register = 11 <77>, <83> <78>, <84> <80>, <86> sibn (input) sobn (output) input data output data <75>, <81> <76>, <82> <76>, <82> sckbn (i/o) <79>, <85> remarks 1. broken lines indicate high impedance. 2. n = 0 to 2
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1146 (7) i 2 c bus timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) standard mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk ? 0 100 0 400 khz bus free time (between stop condition and start condition) t buf <87> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <88> 4.0 ? 0.6 ? s scl clock low-level width t low <89> 4.7 ? 1.3 ? s scl clock high-level width t high <90> 4.0 ? 0.6 ? s start/restart condition setup time t su:sta <91> 4.7 ? 0.6 ? s cbus-compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <92> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <93> 250 ? 100 note 4 ? ns sda, scl signal rise time t r <94> ? 1000 20 + 0.1cb note 5 300 ns sda, scl signal fall time t f <95> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <96> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <97> ? ? 0 50 ns each bus line capacitive load cb ? ? 400 ? 400 pf notes 1. the first clock pulse is generated after a hold time during the start condition. 2. the system must internally supply a hold time of at least 300 ns for the sda signal (at v ihmin . of scl signal) to fill the undefined area at the falling edge of scl. 3. if the system does not extend the low hold time (t low ) of the scl signal, the maximum data hold time (t hd:dat ) must be satisfied. 4. the high-speed mode i 2 c bus can be used in the standard mode i 2 c bus system. in this case, make sure that the following conditions are satisfied. ? if system does not extend the low stat us hold time of the scl signal t su: dat 250 ns ? if system extends the low status hold time of scl signal sends the next data bit to the sda line before the scl line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns: standard mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1147 i 2 c bus timing stop condition start condition restart condition stop condition sda (i/o) <90> <89> <87> <94> <95> <88> <94> <92> <93> <91> <88> <97> <96> <95> scl (i/o) (8) high-impedance control timing (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit oscillation stop timer output high impedance t clm when clock monitor is operating 65 s input to tobnoff timer output high impedance t htqn 300 ns input to toamoff timer output high impedance t htpm 300 ns input to ani00/ani05 timer output high impedance t ani0 10 s input to ani10/ani15 to ani12/ani17 timer output high impedance t ani1 10 s remark n = 0, 1 m = 2, 3
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1148 28.2.9 characteristics of a/d converters 0, 1 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = av refp0 = av refp1 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 12 12 12 bit overall error note 1 10 lsb f ad01 = 16 mhz, adanctc register = 0bh or 0ch 2.0 s conversion time t conv f ad01 = 12 mhz, adanctc register = 00h 7.42 s zero scale error note 1 10 lsb full-scale error note 1 10 lsb integral linearity error note 1 4 lsb differential linearity error note 1 2.5 lsb analog reference voltage av dd 4.0 5.5 v analog input voltage v ian av ss av dd v ai dd during operation 4.5 7.5 ma av dd supply current note 2 ai dds in stop mode note 3 3.5 17.5 a notes 1. excludes quantization error ( 0.5 lsb). 2. this value is for only one a/d converter (a/d converter 0 or 1). 3. stop the operation of a/d converters 0 and 1 (a dnscm.adnce bit = 0) before setting stop mode. remarks 1. lsb: least significant bit 2. f ad01 : base clock of a/d converters 0 and 1 3. n = 0, 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1149 28.2.10 characteristics of a/d converter 2 (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 4.0 lsb conversion time t conv 3.88 10 s zero scale error note 1 4.0 lsb full-scale error note 1 4.0 lsb integral linearity error note 1 4.0 lsb differential linearity error note 1 2.0 lsb analog reference voltage av dd 4.0 5.5 v analog input voltage v ian av ss av dd v ai dd during operation 3.5 7 ma av dd supply current ai dds in stop mode note 2 1 10 a notes 1. excludes quantization error ( 0.5lsb). 2. stop the operation of a/d converter 2 (ad2m0 .ad2ce bit = 0) before setting stop mode. remark lsb: least significant bit
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1150 28.2.11 operational amp lifier characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit input offset voltage v io 9.0 mv gain = 2.500 0.04av dd 0.36av dd v gain = 5.000 0.02av dd 0.18av dd v input voltage range v i gain = 10.00 0.01av dd 0.085av dd v slew rate note 1 s r 10 15 v/ s gain = 2.500 to 4.444 1.0 1.3 % gain = 5.000 to 6.667 1.0 1.5 % note 2 gain = 8.000, 10.00 1.0 1.7 % gain = 2.500 to 4.444 1.0 2.0 % gain = 5.000 to 6.667 1.0 2.1 % gain error note 3 gain = 8.000, 10.00 1.0 2.2 % i opdd during operation 1.8 2.6 ma operating current note 4 a idds in stop mode note 5 1.0 10 a notes 1. inclination characteristic of 10% to 90% of output voltage 2. av dd0 = av dd1 = 4.5 to 5.5 v 3. av dd0 = av dd1 = 4.0 to 5.5 v 4. four operational amplifiers are provided in total. the value shows the operating current per operational amplifier. 5. stop operational amplif ier operation (op0ctl0.op0en bit = 0, op1ctl0.op12en, op11en, and op10en bits = 0)) before setting stop mode. remark power supplies av dd0 and av dd1 are used for the operational amplifier.
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1151 28.2.12 comparator characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 4.0 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit input offset voltage v io 3.0 mv input voltage range v i av ss av dd v comparator reference voltage (full range) crefnf 0.02av dd + 0.1 0.92av dd ? 0.1 v comparator reference voltage (low range) crefnl 0.02av dd + 0.1 0.5av dd ? 0.1 v t cr input amplitude = 100 mv, at rising edge note 1 1.0 s response time t cf input amplitude = 100 mv, at falling edge note 2 1.0 s i cpdd during operation 250 a operating current note 3 a idds in stop mode note 4 2.0 20 na notes 1. characteristics of pulse response when anim i nput changes from the com parator reference voltage ? 100 mv to the comparator reference voltage + 100 mv 2. characteristics of pulse response when anim input changes from the comparat or reference voltage + 100 mv to the comparator reference voltage ? 100 mv 3. four comparators are provided in total. the value shows the operating current per comparator. 4. stop comparator operation (cmpnctl0 re gister = 00h) before setting stop mode. remarks 1. power supplies for the comparators are av dd0 and av dd1 . 2. m = 05, 15 to 17 n = 0, 1 comparator characteristics output voltage v o input voltage v in ? 100 mv 0 v 5 v +100 mv t cr t cf comparator ref. voltage
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1152 28.2.13 power-on-clear circuit (poc) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit poc detection voltage v poc0 3.5 3.7 3.9 v supply voltage rise time t pth <98> v dd0 , v dd1 = 0 to 3.5 v 2.5 s 1.8 s response time 1 note 1 t pthd <99> after v dd0 and v dd1 reach 3.9 v on power application 3.0 ms response time 2 note 2 t pd <100> after v dd0 and v dd1 drop to 3.5 v on power off 1.0 ms minimum width of v dd0 , v dd1 t pw <101> 0.2 ms notes 1. the time required to release a reset signal (po cres) after the poc detection voltage is detected. 2. the time required to output a reset signal (po cres) after the poc detection voltage is detected. supply voltage (v dd0 , v dd1 ) poc detection voltage (max.) poc detection voltage (typ.) poc detection voltage (min.) <98> <99> <100> <99> <101> time
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1153 28.2.14 low-voltage detector (lvi) (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lv i 0 lvis.lvis0 bit = 0 4.2 4.4 4.6 v lvi detection voltage v lv i 1 lvis.lvis0 bit = 1 4.0 4.2 4.4 v response time 1 note t ld <102> after v dd0 and v dd1 reach v lvi 0 /v lv i 1 (max.) or drop to v lv i 0 /v lv i 1 (min.) 0.2 2.0 ms minimum width of v dd0 , v dd1 t lw <103> 0.2 ms reference voltage stabilization wait time t lwait <104> after v dd0 and v dd1 reach poc detection voltage (min.) and the lvim.lvion bit is changed from 0 to 1 0.1 ms note the time required to output an interrupt request signal (intlvil, intlvih) or intern al reset signal (lvires) after the lvi detection voltage is detected. supply voltage (v dd0 , v dd1 ) lvi detection voltage (max.) lvi detection voltage (typ.) lvi detection voltage (min.) poc detection voltage (min.) <103> <102> <102> time <104> lvion bit = 0 1
chapter 28 electrical specifications user?s manual u18279ej3v0ud 1154 28.2.15 flash memory progr amming characteristics (t a = ? 40 to +85 c, v dd0 = v dd1 = ev dd0 = ev dd1 = ev dd2 = av dd0 = av dd1 = av dd2 = 3.5 to 5.5 v, v ss0 = v ss1 = ev ss0 = ev ss1 = ev ss2 = av ss0 = av ss1 = av ss2 = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit rewrite count c erwr note 100 times note rewrite as follows. example when three rewrites: shipped product e p e p e p (p: write, e: erase)
user?s manual u18279ej3v0ud 1155 chapter 29 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.17 + 0.03 ? 0.06 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-ubt 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 80-pin plastic lqfp(14x14) 0.32 0.06 b 20 40 80 21 41 61 60 1
chapter 29 package drawings user?s manual u18279ej3v0ud 1156 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
chapter 29 package drawings user?s manual u18279ej3v0ud 1157 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.04 0.08 0.075 0.025 0.25 c e x y zd ze 0.65 0.13 0.10 0.575 0.825 l lp l1 0.50 0.60 0.15 5 3 1.00 0.20 p100gf-65-gas 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 0.30 b + + + 30 50 1 100 31 51 81 80 100-pin plastic lqfp (14x20)
chapter 29 package drawings user?s manual u18279ej3v0ud 1158 item dimensions d e w a a1 a2 e 10.00 0.10 10.00 0.10 0.65 0.08 0.10 0.20 0.775 0.775 0.20 0.30 0.05 0.05 1.41 0.10 1.11 p161f1-65-da9 nec electronics corporation 2007 0.40 (unit:mm) x y y1 zd ze b 161-pin plastic fbga (10x10) zd ze a index mark a2 a1 e s w a s wb b a s y s y1 s s x bab m 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p d e
user?s manual u18279ej3v0ud 1159 chapter 30 recommended soldering conditions the v850e/if3 and v850e/ig3 should be soldered and m ounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 30-1. surface mounting type soldering cond itions (1/2) (1) pd70f3451gc-ubt-a: 80-pin plastic lqfp (14 14) pd70f3452gc-ubt-a: 80-pin plastic lqfp (14 14) pd70f3453gc-8ea-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3454gc-8ea-a: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir60-107-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with -a at the end of the par t number are lead-free products. 2. for soldering methods and conditions other t han those recommended above, please contact an nec electronics sales representative.
chapter 30 recommended soldering conditions user?s manual u18279ej3v0ud 1160 table 30-1. surface mounting type soldering cond itions (2/2) (2) pd70f3453gf-gas-ax: 100-pin plastic lqfp (14 20) pd70f3454gf-gas-ax: 100-pin plastic lqfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with -ax at the end of the part number are lead-free products. 2. for soldering methods and conditions other t han those recommended above, please contact an nec electronics sales representative. (3) pd70f3454f1-da9-a: 161-pin plastic fbga (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 wave soldering for details, contact an nec electronics sales representative. ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together. remarks 1. products with -a at the end of the par t number are lead-free products. 2. for soldering methods and conditions other t han those recommended above, please contact an nec electronics sales representative.
user?s manual u18279ej3v0ud 1161 appendix a cautions a.1 restriction on conflict between sl d instruction and interrupt request a.1.1 description if a conflict occurs between the decode oper ation of an instruction in <2> imm ediately before the sld instruction following an instruction in <1> and an interr upt request before the instru ction in <1> is complete, the execution result of the instruction in <1> ma y not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflic t before execution of the ld instruction is complete, the execution result of in struction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 a.1.2 countermeasure (1) when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corres ponding instruction sequence can be automatically suppressed. (2) for assembler when executing the sld instruction imm ediately after instruction , avoi d the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instruction destination regi ster in the above instruction executed immediately befor e the sld instruction. ? ? ?
user?s manual u18279ej3v0ud 1162 appendix b register index (1/13) symbol name unit page ad0ch1 a/d converter 0 channel specification register 1 adc0 634 ad0ch2 a/d converter 0 channel specification register 2 adc0 636 ad0chen a/d converter 0 conversion chan nel specification register adc0 626 ad0chenh a/d converter 0 conversion chan nel specification register h adc0 626 ad0chenl a/d converter 0 conversion chan nel specification register l adc0 626 ad0cr0 a/d0 conversion result register 0 adc0 628 ad0cr0h a/d0 conversion result register 0h adc0 628 ad0cr1 a/d0 conversion result register 1 adc0 628 ad0cr10 a/d0 conversion result register 10 adc0 628 ad0cr10h a/d0 conversion result register 10h adc0 628 ad0cr11 a/d0 conversion result register 11 adc0 628 ad0cr11h a/d0 conversion result register 11h adc0 628 ad0cr12 a/d0 conversion result register 12 adc0 628 ad0cr12h a/d0 conversion result register 12h adc0 628 ad0cr13 a/d0 conversion result register 13 adc0 628 ad0cr13h a/d0 conversion result register 13h adc0 628 ad0cr14 a/d0 conversion result register 14 adc0 628 ad0cr14h a/d0 conversion result register 14h adc0 628 ad0cr15 a/d0 conversion result register 15 adc0 628 ad0cr15h a/d0 conversion result register 15h adc0 628 ad0cr1h a/d0 conversion result register 1h adc0 628 ad0cr2 a/d0 conversion result register 2 adc0 628 ad0cr2h a/d0 conversion result register 2h adc0 628 ad0cr3 a/d0 conversion result register 3 adc0 628 ad0cr3h a/d0 conversion result register 3h adc0 628 ad0cr4 a/d0 conversion result register 4 adc0 628 ad0cr4h a/d0 conversion result register 4h adc0 628 ad0cr5 a/d0 conversion result register 5 adc0 628 ad0cr5h a/d0 conversion result register 5h adc0 628 ad0cr6 a/d0 conversion result register 6 adc0 628 ad0cr6h a/d0 conversion result register 6h adc0 628 ad0cr7 a/d0 conversion result register 7 adc0 628 ad0cr7h a/d0 conversion result register 7h adc0 628 ad0cr8 a/d0 conversion result register 8 adc0 628 ad0cr8h a/d0 conversion result register 8h adc0 628 ad0cr9 a/d0 conversion result register 9 adc0 628 ad0cr9h a/d0 conversion result register 9h adc0 628 ad0ctc a/d converter 0 conversion time control register adc0 625 ad0ctl0 a/d converter 0 control register adc0 632
appendix b register index user?s manual u18279ej3v0ud 1163 (2/13) symbol name unit page ad0ecr0 a/d0 conversion result extension register 0 adc0 638 ad0ecr0h a/d0 conversion result extension register 0h adc0 638 ad0ecr1 a/d0 conversion result extension register 1 adc0 638 ad0ecr1h a/d0 conversion result extension register 1h adc0 638 ad0ecr2 a/d0 conversion result extension register 2 adc0 638 ad0ecr2h a/d0 conversion result extension register 2h adc0 638 ad0ecr3 a/d0 conversion result extension register 3 adc0 638 ad0ecr3h a/d0 conversion result extension register 3h adc0 638 ad0ecr4 a/d0 conversion result extension register 4 adc0 638 ad0ecr4h a/d0 conversion result extension register 4h adc0 638 ad0flg a/d converter 0 flag register adc0 640 ad0flgb a/d converter 0 flag buffer register adc0 641 ad0ic interrupt control register intc 1000 ad0ocks a/d converter 0 clock select register adc0 643 ad0scm a/d converter 0 scan mode register adc0 623 ad0scmh a/d converter 0 scan mode register h adc0 623 ad0scml a/d converter 0 scan mode register l adc0 623 ad0tsel a/d converter 0 trigger select register adc0 633 ad1ch1 a/d converter 1 channel specification register 1 adc1 634 ad1ch2 a/d converter 1 channel specification register 2 adc1 636 ad1chen a/d converter 1 conversion chan nel specification register adc1 626 ad1chenh a/d converter 1 conversion chan nel specification register h adc1 626 ad1chenl a/d converter 1 conversion chan nel specification register l adc1 626 ad1cr0 a/d1 conversion result register 0 adc1 628 ad1cr0h a/d1 conversion result register 0h adc1 628 ad1cr1 a/d1 conversion result register 1 adc1 628 ad1cr10 a/d1 conversion result register 10 adc1 628 ad1cr10h a/d1 conversion result register 10h adc1 628 ad1cr11 a/d1 conversion result register 11 adc1 628 ad1cr11h a/d1 conversion result register 11h adc1 628 ad1cr12 a/d1 conversion result register 12 adc1 628 ad1cr12h a/d1 conversion result register 12h adc1 628 ad1cr13 a/d1 conversion result register 13 adc1 628 ad1cr13h a/d1 conversion result register 13h adc1 628 ad1cr14 a/d1 conversion result register 14 adc1 628 ad1cr14h a/d1 conversion result register 14h adc1 628 ad1cr15 a/d1 conversion result register 15 adc1 628 ad1cr15h a/d1 conversion result register 15h adc1 628 ad1cr1h a/d1 conversion result register 1h adc1 628 ad1cr2 a/d1 conversion result register 2 adc1 628 ad1cr2h a/d1 conversion result register 2h adc1 628 ad1cr3 a/d1 conversion result register 3 adc1 628 ad1cr3h a/d1 conversion result register 3h adc1 628 ad1cr4 a/d1 conversion result register 4 adc1 628
appendix b register index user?s manual u18279ej3v0ud 1164 (3/13) symbol name unit page ad1cr4h a/d1 conversion result register 4h adc1 628 ad1cr5 a/d1 conversion result register 5 adc1 628 ad1cr5h a/d1 conversion result register 5h adc1 628 ad1cr6 a/d1 conversion result register 6 adc1 628 ad1cr6h a/d1 conversion result register 6h adc1 628 ad1cr7 a/d1 conversion result register 7 adc1 628 ad1cr7h a/d1 conversion result register 7h adc1 628 ad1cr8 a/d1 conversion result register 8 adc1 628 ad1cr8h a/d1 conversion result register 8h adc1 628 ad1cr9 a/d1 conversion result register 9 adc1 628 ad1cr9h a/d1 conversion result register 9h adc1 628 ad1ctc a/d converter 1 conversion time control register adc1 625 ad1ctl0 a/d converter 1 control register adc1 632 ad1ecr0 a/d1 conversion result extension register 0 adc1 638 ad1ecr0h a/d1 conversion result extension register 0h adc1 638 ad1ecr1 a/d1 conversion result extension register 1 adc1 638 ad1ecr1h a/d1 conversion result extension register 1h adc1 638 ad1ecr2 a/d1 conversion result extension register 2 adc1 638 ad1ecr2h a/d1 conversion result extension register 2h adc1 638 ad1ecr3 a/d1 conversion result extension register 3 adc1 638 ad1ecr3h a/d1 conversion result extension register 3h adc1 638 ad1ecr4 a/d1 conversion result extension register 4 adc1 638 ad1ecr4h a/d1 conversion result extension register 4h adc1 638 ad1flg a/d converter 1 flag register adc1 640 ad1flgb a/d converter 1 flag buffer register adc1 641 ad1ic interrupt control register intc 1000 ad1ocks a/d converter 1 clock select register adc1 643 ad1scm a/d converter 1 scan mode register adc1 623 ad1scmh a/d converter 1 scan mode register h adc1 623 ad1scml a/d converter 1 scan mode register l adc1 623 ad1tsel a/d converter 1 trigger select register adc1 633 ad2cr0 a/d2 conversion result register 0 adc2 695 ad2cr0h a/d2 conversion result register 0h adc2 695 ad2cr1 a/d2 conversion result register 1 adc2 695 ad2cr1h a/d2 conversion result register 1h adc2 695 ad2cr2 a/d2 conversion result register 2 adc2 695 ad2cr2h a/d2 conversion result register 2h adc2 695 ad2cr3 a/d2 conversion result register 3 adc2 695 ad2cr3h a/d2 conversion result register 3h adc2 695 ad2cr4 a/d2 conversion result register 4 adc2 695 ad2cr4h a/d2 conversion result register 4h adc2 695 ad2cr5 a/d2 conversion result register 5 adc2 695 ad2cr5h a/d2 conversion result register 5h adc2 695 ad2cr6 a/d2 conversion result register 6 adc2 695
appendix b register index user?s manual u18279ej3v0ud 1165 (4/13) symbol name unit page ad2cr6h a/d2 conversion result register 6h adc2 695 ad2cr7 a/d2 conversion result register 7 adc2 695 ad2cr7h a/d2 conversion result register 7h adc2 695 ad2ic interrupt control register intc 1000 ad2m0 a/d converter 2 mode register 0 adc2 692 ad2m1 a/d converter 2 mode register 1 adc2 693 ad2s a/d converter 2 channel specification register adc2 694 adlts1 a/d ldtrg1 input select register adc0, adc1 642 adlts2 a/d ldtrg2 input select register adc0, adc1 642 adt0ic interrupt control register intc 1000 adt1ic interrupt control register intc 1000 adtf a/d trigger falling edge specification register adc0, adc1 644 adtr a/d trigger rising edge specification register adc0, adc1 644 awc address wait control register bcu 943 bcc bus cycle control register bcu 946 bct0 bus cycle type configuration register 0 bcu 931 bsc bus size configuration register bcu 933 cb0ctl0 csib0 control register 0 csib 812 cb0ctl1 csib0 control register 1 csib 815 cb0ctl2 csib0 control register 2 csib 816 cb0reic interrupt control register intc 1000 cb0ric interrupt control register intc 1000 cb0rx csib0 receive data register csib 811 cb0rxl csib0 receive data register l csib 811 cb0str csib0 status register csib 818 cb0tic interrupt control register intc 992 cb0tx csib0 transmit data register csib 811 cb0txl csib0 transmit data register l csib 811 cb1ctl0 csib1 control register 0 csib 812 cb1ctl1 csib1 control register 1 csib 815 cb1ctl2 csib1 control register 2 csib 816 cb1reic interrupt control register intc 1000 cb1ric interrupt control register intc 1000 cb1rx csib1 receive data register csib 811 cb1rxl csib1 receive data register l csib 811 cb1str csib1 status register csib 818 cb1tic interrupt control register intc 1000 cb1tx csib1 transmit data register csib 811 cb1txl csib1 transmit data register l csib 811 cb2ctl0 csib2 control register 0 csib 812 cb2ctl1 csib2 control register 1 csib 815 cb2ctl2 csib2 control register 2 csib 816 cb2reic interrupt control register intc 1000 cb2ric interrupt control register intc 1000
appendix b register index user?s manual u18279ej3v0ud 1166 (5/13) symbol name unit page cb2rx csib2 receive data register csib 811 cb2rxl csib2 receive data register l csib 811 cb2str csib2 status register csib 818 cb2tic interrupt control register intc 1000 cb2tx csib2 transmit data register csib 811 cb2txl csib2 transmit data register l csib 811 clm clock monitor mode register cg 183 cmp0ctl0 comparator 0 control register 0 adc0 647 cmp0ctl1 comparator 0 control register 1 adc0 649 cmp0ctl2 comparator 0 control register 2 adc0 651 cmp0ctl3 comparator 0 control register 3 adc0 652 cmp1ctl0 comparator 1 control register 0 adc1 647 cmp1ctl1 comparator 1 control register 1 adc1 649 cmp1ctl2 comparator 1 control register 2 adc1 651 cmp1ctl3 comparator 1 control register 3 adc1 652 cmpic0f interrupt control register intc 1000 cmpic0l interrupt control register intc 1000 cmpic1f interrupt control register intc 1000 cmpic1l interrupt control register intc 1000 cmpnfc0f comparator output digital noi se elimination register 0f adc0 654 cmpnfc0l comparator output digital noi se elimination register 0l adc0 654 cmpnfc1f comparator output digital noi se elimination register 1f adc1 654 cmpnfc1l comparator output digital noi se elimination register 1l adc1 654 cmpof comparator output interrupt falling edge specification register adc0, adc1 655 cmpor comparator output interrupt rising edge specification register adc0, adc1 655 dadc0 dma addressing control register 0 dmac 966 dadc1 dma addressing control register 1 dmac 966 dadc2 dma addressing control register 2 dmac 966 dadc3 dma addressing control register 3 dmac 966 dbc0 dma transfer count register 0 dmac 965 dbc1 dma transfer count register 1 dmac 965 dbc2 dma transfer count register 2 dmac 965 dbc3 dma transfer count register 3 dmac 965 dchc0 dma channel control register 0 dmac 967 dchc1 dma channel control register 1 dmac 967 dchc2 dma channel control register 2 dmac 967 dchc3 dma channel control register 3 dmac 967 dda0h dma destination address register 0h dmac 963 dda0l dma destination address register 0l dmac 964 dda1h dma destination address register 1h dmac 963 dda1l dma destination address register 1l dmac 964 dda2h dma destination address register 2h dmac 963 dda2l dma destination address register 2l dmac 964 dda3h dma destination address register 3h dmac 963
appendix b register index user?s manual u18279ej3v0ud 1167 (6/13) symbol name unit page dda3l dma destination address register 3l dmac 964 dmaic0 interrupt control register intc 1000 dmaic1 interrupt control register intc 1000 dmaic2 interrupt control register intc 1000 dmaic3 interrupt control register intc 1000 dsa0h dma source address register 0h dmac 961 dsa0l dma source address register 0l dmac 962 dsa1h dma source address register 1h dmac 961 dsa1l dma source address register 1l dmac 962 dsa2h dma source address register 2h dmac 961 dsa2l dma source address register 2l dmac 962 dsa3h dma source address register 3h dmac 961 dsa3l dma source address register 3l dmac 962 dtfr0 dma trigger factor register 0 dmac 969 dtfr1 dma trigger factor register 1 dmac 969 dtfr2 dma trigger factor register 2 dmac 969 dtfr3 dma trigger factor register 3 dmac 969 dvc bus clock division control register bcu 947 dwc0 data wait control register 0 bcu 941 hza0ctl0 high-impedance output control register 00 timer 556 hza0ctl1 high-impedance output control register 01 timer 556 hza1ctl0 high-impedance output control register 10 timer 556 hza1ctl1 high-impedance output control register 11 timer 556 hza2ctl0 high-impedance output control register 20 timer 556 hza2ctl1 high-impedance output control register 21 timer 556 hza3ctl0 high-impedance output control register 30 timer 556 hza3ctl1 high-impedance output control register 31 timer 556 iic0 iic shift register 0 i 2 c 857 iicc0 iic control register 0 i 2 c 860 iiccl0 iic clock select register 0 i 2 c 869 iicf0 iic flag register 0 i 2 c 867 iicic interrupt control register intc 1000 iicocks iicops clock select register i 2 c 870 iics0 iic status register 0 i 2 c 864 iicx0 iic function expansion register 0 i 2 c 870 imr0 interrupt mask register 0 intc 1005 imr0h interrupt mask register 0h intc 1005 imr0l interrupt mask register 0l intc 1005 imr1 interrupt mask register 1 intc 1005 imr1h interrupt mask register 1h intc 1005 imr1l interrupt mask register 1l intc 1005 imr2 interrupt mask register 2 intc 1005 imr2h interrupt mask register 2h intc 1005 imr2l interrupt mask register 2l intc 1005
appendix b register index user?s manual u18279ej3v0ud 1168 (7/13) symbol name unit page imr3 interrupt mask register 3 intc 1005 imr3h interrupt mask register 3h intc 1005 imr3l interrupt mask register 3l intc 1005 imr4 interrupt mask register 4 intc 1005 imr4h interrupt mask register 4h intc 1005 imr4l interrupt mask register 4l intc 1005 imr5 interrupt mask register 5 intc 1005 imr5h interrupt mask register 5h intc 1005 imr5l interrupt mask register 5l intc 1005 intf0 external interrupt falling edge specification register 0 intc 1011 intf1 external interrupt falling edge specification register 1 intc 1012 intf2 external interrupt falling edge specification register 2 intc 1013 intnfc14 digital noise eliminati on 0 control register 14 port 169 intnfc15 digital noise eliminati on 0 control register 15 port 169 intnfc16 digital noise eliminati on 0 control register 16 port 169 intr0 external interrupt rising edge specification register 0 intc 1011 intr1 external interrupt rising edge specification register 1 intc 1012 intr2 external interrupt rising edge specification register 2 intc 1013 ispr in-service priority register intc 1008 lvihic interrupt control register intc 1000 lvilic interrupt control register intc 1000 lvim low-voltage detection register lvi 1042 lvis low-voltage detection level select register lvi 1043 op0ctl0 operational amplifier 0 control register 0 adc0 645 op1ctl0 operational amplifier 1 control register 0 adc0 645 osts oscillation stabilization time select register cg 182 p0 port 0 register port 108 p1 port 1 register port 114 p2 port 2 register port 120 p3 port 3 register port 126 p4 port 4 register port 132 p7 port 7 register port 138 pcc processor clock control register cg 179 pdl port dl register port 140 pdlh port dlh register port 140 pdll port dll register port 140 pf3 port 3 function register port 130 pfc0 port 0 function control register port 110 pfc1 port 1 function control register port 116 pfc2 port 2 function control register port 122 pfc3 port 3 function control register port 128 pfc4 port 4 function control register port 134 pfce0 port 0 function control expansion register port 110 pfce1 port 1 function control expansion register port 116
appendix b register index user?s manual u18279ej3v0ud 1169 (8/13) symbol name unit page pfce2 port 2 function control expansion register port 122 pfce3 port 3 function control expansion register port 128 pfce4 port 4 function control expansion register port 134 pic00 interrupt control register intc 1000 pic01 interrupt control register intc 1000 pic02 interrupt control register intc 1000 pic03 interrupt control register intc 1000 pic04 interrupt control register intc 1000 pic05 interrupt control register intc 1000 pic06 interrupt control register intc 1000 pic07 interrupt control register intc 1000 pic08 interrupt control register intc 1000 pic09 interrupt control register intc 1000 pic10 interrupt control register intc 1000 pic11 interrupt control register intc 1000 pic12 interrupt control register intc 1000 pic13 interrupt control register intc 1000 pic14 interrupt control register intc 1000 pic15 interrupt control register intc 1000 pic16 interrupt control register intc 1000 pic17 interrupt control register intc 1000 pic18 interrupt control register intc 1000 pllctl pll control register cg 178 pm0 port 0 mode register port 108 pm1 port 1 mode register port 114 pm2 port 2 mode register port 120 pm3 port 3 mode register port 126 pm4 port 4 mode register port 132 pmc0 port 0 mode control register port 109 pmc1 port 1 mode control register port 115 pmc2 port 2 mode control register port 121 pmc3 port 3 mode control register port 127 pmc4 port 4 mode control register port 133 pmc7 port 7 mode control register port 138 pmcdl port dl mode control register port 142 pmcdlh port dl mode control register h port 142 pmcdll port dl mode control register l port 142 pmdl port dl mode register port 141 pmdlh port dl mode register h port 141 pmdll port dl mode register l port 141 prcmd command register cpu 95 psc power save control register cpu 180, 1027 psmr power save mode register cpu 181, 1028 pu0 pull-up resistor option register 0 port 112
appendix b register index user?s manual u18279ej3v0ud 1170 (9/13) symbol name unit page pu1 pull-up resistor option register 1 port 118 pu2 pull-up resistor option register 2 port 124 pu3 pull-up resistor option register 3 port 130 pu4 pull-up resistor option register 4 port 136 pudl pull-up resistor option register dl port 143 pudlh pull-up resistor option register dlh port 143 pudll pull-up resistor option register dll port 143 resf reset source flag register reset 1036 sva0 slave address register 0 i 2 c 857 sys system status register cpu 96 ta0ccic0 interrupt control register intc 1000 ta0ccic1 interrupt control register intc 1000 ta0ovic interrupt control register intc 1000 ta1ccic0 interrupt control register intc 1000 ta1ccic1 interrupt control register intc 1000 ta1ovic interrupt control register intc 1000 ta2ccic0 interrupt control register intc 1000 ta2ccic1 interrupt control register intc 1000 ta2ovic interrupt control register intc 1000 ta3ccic0 interrupt control register intc 1000 ta3ccic1 interrupt control register intc 1000 ta3ovic interrupt control register intc 1000 ta4ccic0 interrupt control register intc 1000 ta4ccic1 interrupt control register intc 1000 ta4ovic interrupt control register intc 1000 taa0ccr0 taa0 capture/compare register 0 taa 207 taa0ccr1 taa0 capture/compare register 1 taa 209 taa0cnt taa0 counter read buffer register taa 211 taa0ctl0 taa0 control register 0 taa 199 taa0ctl1 taa0 control register 1 taa 200 taa0opt0 taa0 option register 0 taa 206 taa1ccr0 taa1 capture/compare register 0 taa 207 taa1ccr1 taa1 capture/compare register 1 taa 209 taa1cnt taa1 counter read buffer register taa 211 taa1ctl0 taa1 control register 0 taa 199 taa1ctl1 taa1 control register 1 taa 200 taa1opt0 taa1 option register 0 taa 206 taa2ccr0 taa2 capture/compare register 0 taa 207 taa2ccr1 taa2 capture/compare register 1 taa 209 taa2cnt taa2 counter read buffer register taa 211 taa2ctl0 taa2 control register 0 taa 199 taa2ctl1 taa2 control register 1 taa 200 taa2ioc0 taa2 i/o control register 0 taa 202 taa2ioc1 taa2 i/o control register 1 taa 204
appendix b register index user?s manual u18279ej3v0ud 1171 (10/13) symbol name unit page taa2ioc2 taa2 i/o control register 2 taa 205 taa2opt0 taa2 option register 0 taa 206 taa3ccr0 taa3 capture/compare register 0 taa 207 taa3ccr1 taa3 capture/compare register 1 taa 209 taa3cnt taa3 counter read buffer register taa 211 taa3ctl0 taa3 control register 0 taa 199 taa3ctl1 taa3 control register 1 taa 200 taa3ioc0 taa3 i/o control register 0 taa 202 taa3ioc1 taa3 i/o control register 1 taa 204 taa3ioc2 taa3 i/o control register 2 taa 205 taa3opt0 taa3 option register 0 taa 206 taa4ccr0 taa4 capture/compare register 0 taa 207 taa4ccr1 taa4 capture/compare register 1 taa 209 taa4cnt taa4 counter read buffer register taa 211 taa4ctl0 taa4 control register 0 taa 199 taa4ctl1 taa4 control register 1 taa 200 taa4ioc0 taa4 i/o control register 0 taa 202 taa4ioc1 taa4 i/o control register 1 taa 204 taa4ioc2 taa4 i/o control register 2 taa 205 taa4opt0 taa4 option register 0 taa 206 tab0ccr0 tab0 capture/compare register 0 tab 303 tab0ccr1 tab0 capture/compare register 1 tab 305 tab0ccr2 tab0 capture/compare register 2 tab 307 tab0ccr3 tab0 capture/compare register 3 tab 309 tab0cnt tab0 counter read buffer register tab 311 tab0ctl0 tab0 control register 0 tab 297 tab0ctl1 tab0 control register 1 tab 298 tab0dtc tab0 dead-time compare register timer 547 tab0ioc0 tab0 i/o control register 0 tab 299 tab0ioc1 tab0 i/o control register 1 tab 300 tab0ioc2 tab0 i/o control register 2 tab 301 tab0ioc3 tab0 i/o control register 3 timer 553 tab0opt0 tab0 option register 0 tab 302, 549 tab0opt1 tab0 option register 1 timer 549 tab0opt2 tab0 option register 2 timer 550 tab0opt3 tab0 option register 3 timer 552 tab1ccr0 tab1 capture/compare register 0 tab 303 tab1ccr1 tab1 capture/compare register 1 tab 305 tab1ccr2 tab1 capture/compare register 2 tab 307 tab1ccr3 tab1 capture/compare register 3 tab 309 tab1cnt tab1 counter read buffer register tab 311 tab1ctl0 tab1 control register 0 tab 297 tab1ctl1 tab1 control register 1 tab 298 tab1dtc tab1 dead-time compare register tab 547
appendix b register index user?s manual u18279ej3v0ud 1172 (11/13) symbol name unit page tab1ioc0 tab1 i/o control register 0 tab 299 tab1ioc1 tab1 i/o control register 1 tab 300 tab1ioc2 tab1 i/o control register 2 tab 301 tab1ioc3 tab1 i/o control register 3 tab 553 tab1opt0 tab1 option register 0 tab 302, 549 tab1opt1 tab1 option register 1 tab 549 tab1opt2 tab1 option register 2 tab 550 tab1opt3 tab1 option register 3 tab 552 tanfc2 digital noise eliminati on 1 control register 2 port 170 tanfc3 digital noise eliminati on 1 control register 3 port 170 tanfc4 digital noise eliminati on 1 control register 4 port 170 tb0ccic0 interrupt control register intc 1000 tb0ccic1 interrupt control register intc 1000 tb0ccic2 interrupt control register intc 1000 tb0ccic3 interrupt control register intc 1000 tb0ovic interrupt control register intc 1000 tb1ccic0 interrupt control register intc 1000 tb1ccic1 interrupt control register intc 1000 tb1ccic2 interrupt control register intc 1000 tb1ccic3 interrupt control register intc 1000 tb1ovic interrupt control register intc 1000 tm0cmp0 tmm0 compare register 0 tmm 536 tm0ctl0 tmm0 control register 0 tmm 537 tm0eqic0 interrupt control register intc 1000 tm1cmp0 tmm1 compare register 0 tmm 536 tm1ctl0 tmm1 control register 0 tmm 537 tm1eqic0 interrupt control register intc 1000 tm2cmp0 tmm2 compare register 0 tmm 536 tm2ctl0 tmm2 control register 0 tmm 537 tm2eqic0 interrupt control register intc 1000 tm3cmp0 tmm3 compare register 0 tmm 536 tm3ctl0 tmm3 control register 0 tmm 537 tm3eqic0 interrupt control register intc 1000 tt0ccic0 interrupt control register intc 1000 tt0ccic1 interrupt control register intc 1000 tt0ccr0 tmt0 capture/compare register 0 tmt 423 tt0ccr1 tmt0 capture/compare register 1 tmt 425 tt0cnt tmt0 counter read buffer register tmt 427 tt0ctl0 tmt0 control register 0 tmt 408 tt0ctl1 tmt0 control register 1 tmt 409 tt0ctl2 tmt0 control register 2 tmt 411 tt0iecic interrupt control register intc 1000 tt0ioc0 tmt0 i/o control register 0 tmt 413 tt0ioc1 tmt0 i/o control register 1 tmt 415
appendix b register index user?s manual u18279ej3v0ud 1173 (12/13) symbol name unit page tt0ioc2 tmt0 i/o control register 2 tmt 416 tt0ioc3 tmt0 i/o control register 3 tmt 417 tt0opt0 tmt0 option register 0 tmt 419 tt0opt1 tmt0 option register 1 tmt 420 tt0ovic interrupt control register intc 1000 tt0tcw tmt0 counter write register tmt 427 tt1ccic0 interrupt control register intc 1000 tt1ccic1 interrupt control register intc 1000 tt1ccr0 tmt1 capture/compare register 0 tmt 423 tt1ccr1 tmt1 capture/compare register 1 tmt 425 tt1cnt tmt1 counter read buffer register tmt 427 tt1ctl0 tmt1 control register 0 tmt 408 tt1ctl1 tmt1 control register 1 tmt 409 tt1ctl2 tmt1 control register 2 tmt 411 tt1iecic interrupt control register intc 1000 tt1ioc0 tmt1 i/o control register 0 tmt 413 tt1ioc1 tmt1 i/o control register 1 tmt 415 tt1ioc2 tmt1 i/o control register 2 tmt 416 tt1ioc3 tmt1 i/o control register 3 tmt 417 tt1opt0 tmt1 option register 0 tmt 419 tt1opt1 tmt1 option register 1 tmt 420 tt1ovic interrupt control register intc 1000 tt1tcw tmt1 counter write register tmt 427 ttisl0 tmt0 capture input select register tmt 422 ttisl1 tmt1 capture input select register tmt 422 ttnfc0 digital noise elimination 2 control register 0 port 171 ttnfc1 digital noise elimination 2 control register 1 port 171 ua0ctl0 uarta0 control register 0 uarta 723 ua0ctl1 uarta0 control register 1 uarta 739 ua0ctl2 uarta0 control register 2 uarta 740 ua0opt0 uarta0 option control register 0 uarta 725 ua0reic interrupt control register intc 1000 ua0ric interrupt control register intc 1000 ua0rx uarta0 receive data register uarta 727 ua0str uarta0 status register uarta 725 ua0tic interrupt control register intc 1000 ua0tx uarta0 transmit data register uarta 727 ua1ctl0 uarta1 control register 0 uarta 723 ua1ctl1 uarta1 control register 1 uarta 739 ua1ctl2 uarta1 control register 2 uarta 740 ua1opt0 uarta1 option control register 0 uarta 725 ua1reic interrupt control register intc 1000 ua1ric interrupt control register intc 1000 ua1rx uarta1 receive data register uarta 727
appendix b register index user?s manual u18279ej3v0ud 1174 (13/13) symbol name unit page ua1str uarta1 status register uarta 725 ua1tic interrupt control register intc 1000 ua1tx uarta1 transmit data register uarta 727 ua2ctl0 uarta2 control register 0 uarta 723 ua2ctl1 uarta2 control register 1 uarta 739 ua2ctl2 uarta2 control register 2 uarta 740 ua2opt0 uarta2 option control register 0 uarta 725 ua2reic interrupt control register intc 1000 ua2ric interrupt control register intc 1000 ua2rx uarta2 receive data register uarta 727 ua2str uarta2 status register uarta 725 ua2tic interrupt control register intc 1000 ua2tx uarta2 transmit data register uarta 727 ubctl0 uartb control register 0 uartb 749 ubctl2 uartb control register 2 uartb 757 ubfic0 uartb fifo control register 0 uartb 761 ubfic1 uartb fifo control register 1 uartb 763 ubfic2 uartb fifo control register 2 uartb 764 ubfic2h uartb fifo control register 2h uartb 764 ubfic2l uartb fifo control register 2l uartb 764 ubfis0 uartb fifo status register 0 uartb 766 ubfis1 uartb fifo status register 1 uartb 767 ubrx uartb receive data register uartb 759 ubrxap uartb receive data register ap uartb 759 ubstr uartb status register uartb 755 ubtx uartb transmit data register uartb 758 uific interrupt control register intc 1000 ureic interrupt control register intc 1000 uric interrupt control register intc 1000 utic interrupt control register intc 1000 utoic interrupt control register intc 1000 vswc system wait control register bcu 97 wdte watchdog timer enable register wdt 609 wdtm watchdog timer mode register wdt 608
user?s manual u18279ej3v0ud 1175 appendix c instruction set list c.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division results and the higher order 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (sp) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list
appendix c instruction set list user?s manual u18279ej3v0ud 1176 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
appendix c instruction set list user?s manual u18279ej3v0ud 1177 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
appendix c instruction set list user?s manual u18279ej3v0ud 1178 c.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 0 when conditions are satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23:16) ll gr[reg2] (31:24) ll gr[reg2] (7:0) ll gr[reg2] (15:8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7:0) ll gr[reg2] (15:8) ll gr [reg2] (23:16) ll gr[reg2] (31:24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 5 5 5 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 4 4 4 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 4 4 4 r r r r r
appendix c instruction set list user?s manual u18279ej3v0ud 1179 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2(return pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15:0) ll gr[reg2] (31:16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 3 3 3 jmp [reg1] 00000000011rrrrr pc gr[reg1] 4 4 4 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 3 3 3 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
appendix c instruction set list user?s manual u18279ej3v0ud 1180 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 14 2 mul note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 2 note 14 2 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 1 4 2 mulu note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 2 note 1 4 2 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
appendix c instruction set list user?s manual u18279ej3v0ud 1181 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) gr[reg in list 12] load-memory(sp,word) sp sp+4 repeat 2 step above until a ll regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend(imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
appendix c instruction set list user?s manual u18279ej3v0ud 1182 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
appendix c instruction set list user?s manual u18279ej3v0ud 1183 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr[reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory(adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7:0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15:0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4(return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend(imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend(gr[reg1] (7:0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend(gr[reg1] (15:0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 4 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
appendix c instruction set list user?s manual u18279ej3v0ud 1184 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. in the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not wri tten in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. 22. do not make a combination that satisfies all the following conditions when using the ?mul reg1, reg2, reg3? instruction and ?mulu reg1, reg2, reg3? in struction. operation is not guaranteed when an instruction that satisfies the fo llowing conditions is executed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0
user?s manual u18279ej3v0ud 1185 appendix d revision history d.1 major revisions in this edition page description p. 183 deletion of description in 5.3 (6) clock monitor mode register (clm) p. 564 modification of description in figure 10-6 timing chart of 6-phase pwm output mode p. 582 modification of description in figure 10-21 timing of reflecting rewritten value p. 600 modification of description in 10.4.5 (3) when not tuning taan p. 608 addition of description to 11.3 (1) watchdog timer mode register (wdtm) p. 609 deletion of description in 11.4 operation p. 614 modification of description in figure 12-3 block diagram of operational amplifier for input level amplification and overvoltage detection comparator in a/d converter 0 p. 615 modification of description in figure 12-4 block diagram of operational amplifier for input level amplification and overvoltage detection comparator in a/d converter 1 p. 616 addition of figure 12-5 cmpnctl3 register selector circuit configuration p. 624 modification of description in 12.3 (1) a/d converter n scan mode register (adnscm) pp. 645, 646 addition of description to 12.3 (16) operational amplifier n control register 0 (opnctl0) p. 648 modification of description in 12.3 (17) comparator n control register 0 (cmpnctl0) p. 679 modification of description in 12.5 internal equivalent circuit p. 713 modification of description in figure 13-12 processing of analog input pin p. 810 modification of figure in figure 16-4 block diagram of csibn p. 912 modification of description in 17.15 (4) procedure for starting or stopping i 2 c operation p. 944 addition of description to 18.6.3 relationship between programmable wait and external wait pp. 944, 945 modification of description in figure 18-1 example of inserting wait states p. 981 addition of description to 19.12 (3) bus arbitration for cpu pp. 1036, 1037 modification of description in 22.2 (1) reset source flag register (resf) p. 1040 deletion of description in 22.3 (3) reset operation (lvires) by low-voltage detector (lvi) p. 1040 deletion of description in 22.3 (4) reset operation (pocres) by power-on-clear circuit (poc) p. 1042 modification of description in 23.3 (1) low-voltage detection register (lvim) p. 1044 modification of description in 23.4.1 to use for internal reset signal p. 1046 modification of description in 23.4.2 to use for interrupt p. 1058 modification of description in 26.1.4 cautions p. 1070 modification of description in 26.3.2 setting p. 1072 addition of 27.2 memory configuration p. 1073 addition of description to 27.3 functional overview pp. 1094 to 1096, 1098 modification of description in 27.9 rewriting by self programming p. 1158 modification of description in chapter 29 package drawings
appendix d revision history user?s manual u18279ej3v0ud 1186 d.2 revision history up to previous edition the following table shows the revision history up to this editi on. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/3) edition description applied to: ? addition of product pd70f3454f1-da9-a ? addition of package 161-pin plastic fbga (10 10) ? addition of flash memory programmers pg-fp5 and fl-pr5 throughout addition of note to 1.3.4 pin configuration (v850e/ig3) chapter 1 introduction modification of description in 3.2.2 (2) nmi status saving registers (fepc, fepsw) chapter 3 cpu function modification of cautions 1 and 2 in table 4-15 noise eliminator (1/2) modification of cautions 1 and 2 in table 4-15 noise eliminator (2/2) addition of note to 4.6 (1) digital noise elimination 0 control register n (intnfcn) chapter 4 port functions modification of description in 6.6 (1) (a) counter start operation addition of caution 2 to figure 6-19 register setting for operation in external event count mode (2/2) modification of description in, addition of caution to figure 6-24 configuration in external trigger pulse output mode modification of description in figure 6-26 setting of registers in external trigger pulse output mode (1/2) modification of description in figure 6-26 setting of registers in external trigger pulse output mode (2/2) modification of description in, addition of caution to figure 6-28 configuration in one- shot pulse output mode modification of description in figure 6-30 setting of registers in one-shot pulse output mode (1/2) modification of description in, addition of caution to figure 6-30 setting of registers in one-shot pulse output mode (2/2) addition of description to figure 6-31 software processing flow in one-shot pulse output mode modification of description in, addition of caution to figure 6-42 configuration in pulse width measurement mode modification of description in figure 6-44 register setting in pulse width measurement mode (1/2) modification of description in figure 6-44 register setting in pulse width measurement mode (2/2) modification of description in figure 6-45 <1> count operation start flow chapter 6 16-bit timer/event counter aa (taa) modification of description in 7.6 (1) (a) counter start operation 2nd edition addition of caution to figure 7-26 register setting in one-shot pulse output mode (3/3) chapter 7 16-bit timer/event counter ab (tab)
appendix d revision history user?s manual u18279ej3v0ud 1187 (2/3) edition description applied to: modification of description in 8.6 (1) (a) counter start operation addition of caution to figure 8-16 (f) tmtm capture/compare register 1 (ttmccr1) addition of caution to 8.6.2 (2) operation timing in external event count mode addition of caution to figure 8-27 setting of registers in one-shot pulse output mode (2/2) modification of figure in figure 8-28 software processing flow in one-shot pulse output mode addition of 8.6.8 (1) pwm output of 0%/100% chapter 8 16-bit timer/event counter t (tmt) modification of description in, addition of note to 10.3 (2) tabn option register 1 (tabnopt1) chapter 10 motor control function addition of note to 12.3 (20) comparator output digital noise elimination register nl, nf (cmpnfcnl, cmpnfcnf) modification of description in 12.6.8 a/d conversion result hysteresis characteristics chapter 12 a/d converters 0 and 1 modification of caution in 13.3 (2) a/d converter 2 mode register 1 (ad2m1) modification of description in 13.7 (11) a/d conversion result hysteresis characteristics chapter 13 a/d converter 2 modification of description in figure 14-4 block diagram of uartan modification of description in figure 14-8 continuous transmission operation timing chapter 14 asynchronous serial interface a (uarta) modification of figure in figure 17-21 (a) start condition ~ address modification of figure in figure 17-21 (b) data modification of figure in figure 17-21 (c) stop condition modification of figure in figure 17-22 (a) start condition ~ address modification of figure in figure 17-22 (b) data modification of figure in figure 17-22 (c) stop condition chapter 17 i 2 c bus modification of caution 1 in 19.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) modification of note in table 19-1 dma start factors (1/2) modification of description in 19.12 (3) bus arbitration for cpu addition of 19.12 (4) dma start factors chapter 19 dma functions (dma controller) modification of caution 2 in 20.3.4 interrupt control registers (xxicn) chapter 20 interrupt/ exception processing function deletion of description in 26.3.2 setting chapter 26 on-chip debug function addition of 28.1.4 (i) murata mfg. co., ltd.: ceramic resonator (t a = ? 40 to +85 c) addition of 28.2.4 (i) murata mfg. co., ltd.: ceramic resonator (t a = ? 40 to +85 c) (products other than pd70f3454f1-da9-a) addition of caution to 28.2.8 (4) (b) read cycle (clkout synchronous) 2nd edition addition of caution to 28.2.8 (4) (d) write cycle (clkout synchronous) chapter 28 electrical specifications
appendix d revision history user?s manual u18279ej3v0ud 1188 (3/3) edition description applied to: addition of description to chapter 30 recommended soldering conditions chapter 30 recommended soldering conditions 2nd edition addition of appendix d revision history appendix d revision history
published by: nec electronics co rporation (http://www.necel.com/) contact: http://www.necel.com/support/


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